| /drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| D | dce_clk_mgr.c | 278 if (bp->integrated_info) in dce_clock_read_integrated_info()
279 clk_mgr_dce->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; in dce_clock_read_integrated_info()
314 if (bp->integrated_info) in dce_clock_read_integrated_info()
315 if (bp->integrated_info->disp_clk_voltage[i].max_supported_clk >= 100000) in dce_clock_read_integrated_info()
317 bp->integrated_info->disp_clk_voltage[i].max_supported_clk; in dce_clock_read_integrated_info()
320 if (!debug->disable_dfs_bypass && bp->integrated_info) in dce_clock_read_integrated_info()
321 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) in dce_clock_read_integrated_info()
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| /drivers/gpu/drm/amd/display/dc/link/ |
| D | link_dpms.c | 218 struct integrated_info *integrated_info = in get_ext_hdmi_settings() local
219 pipe_ctx->stream->ctx->dc_bios->integrated_info; in get_ext_hdmi_settings()
221 if (integrated_info == NULL) in get_ext_hdmi_settings()
231 if (integrated_info->gpu_cap_info & 0x20) { in get_ext_hdmi_settings()
234 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; in get_ext_hdmi_settings()
235 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; in get_ext_hdmi_settings()
236 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; in get_ext_hdmi_settings()
238 integrated_info->dp0_ext_hdmi_reg_settings, in get_ext_hdmi_settings()
239 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); in get_ext_hdmi_settings()
241 integrated_info->dp0_ext_hdmi_6g_reg_settings, in get_ext_hdmi_settings()
[all …]
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| D | link_factory.c | 477 struct integrated_info info = { 0 }; in construct_phy()
692 if (bios->integrated_info) in construct_phy()
693 info = *bios->integrated_info; in construct_phy()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| D | rv1_clk_mgr.c | 336 if (bp->integrated_info) in rv1_clk_mgr_construct()
337 clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; in rv1_clk_mgr_construct()
344 if (!debug->disable_dfs_bypass && bp->integrated_info) in rv1_clk_mgr_construct()
345 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) in rv1_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_bios_types.h | 182 struct integrated_info *integrated_info; member
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| D | dcn201_clk_mgr.c | 205 if (!debug->disable_dfs_bypass && bp->integrated_info) in dcn201_clk_mgr_construct()
206 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) in dcn201_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_clk_mgr.c | 347 struct integrated_info info = { { { 0 } } }; in dce_clock_read_integrated_info()
351 if (bp->integrated_info) in dce_clock_read_integrated_info()
352 info = *bp->integrated_info; in dce_clock_read_integrated_info()
396 if (!debug->disable_dfs_bypass && bp->integrated_info) in dce_clock_read_integrated_info()
397 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) in dce_clock_read_integrated_info()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 479 struct integrated_info *bios_info, in dcn316_clk_mgr_helper_populate_bw_params()
633 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { in dcn316_clk_mgr_construct()
654 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { in dcn316_clk_mgr_construct()
657 ctx->dc_bios->integrated_info, in dcn316_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.c | 559 struct integrated_info *bios_info, in vg_clk_mgr_helper_populate_bw_params()
717 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { in vg_clk_mgr_construct()
731 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { in vg_clk_mgr_construct()
734 ctx->dc_bios->integrated_info, in vg_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.c | 639 …struct clk_bw_params *bw_params, struct dpm_clocks *clock_table, struct integrated_info *bios_info) in rn_clk_mgr_helper_populate_bw_params()
743 if (ctx->dc_bios->integrated_info->memory_type == LpDdr4MemType) { in rn_clk_mgr_construct()
775 ctx->dc_bios && ctx->dc_bios->integrated_info) { in rn_clk_mgr_construct()
776 …r_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info); in rn_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 556 struct integrated_info *bios_info, in dcn31_clk_mgr_helper_populate_bw_params()
726 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { in dcn31_clk_mgr_construct()
787 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { in dcn31_clk_mgr_construct()
790 ctx->dc_bios->integrated_info, in dcn31_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 481 struct integrated_info *bios_info, in dcn315_clk_mgr_helper_populate_bw_params()
654 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) { in dcn315_clk_mgr_construct()
715 if (ctx->dc_bios && ctx->dc_bios->integrated_info) { in dcn315_clk_mgr_construct()
718 ctx->dc_bios->integrated_info, in dcn315_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/dc/bios/ |
| D | bios_parser2.c | 93 kfree(bp->base.integrated_info); in bios_parser2_destruct()
1018 if (bp->base.integrated_info) { in get_ss_info_v4_5()
1019 …DC_LOG_BIOS("gpuclk_ss_percentage (unit of 0.001 percent): %d\n", bp->base.integrated_info->gpuclk… in get_ss_info_v4_5()
1021 bp->base.integrated_info->gpuclk_ss_percentage; in get_ss_info_v4_5()
1023 bp->base.integrated_info->gpuclk_ss_type; in get_ss_info_v4_5()
2432 struct integrated_info *info) in get_integrated_info_v11()
2649 struct integrated_info *info) in get_integrated_info_v2_1()
2811 struct integrated_info *info) in get_integrated_info_v2_2()
2931 struct integrated_info *info) in construct_integrated_info()
3099 static struct integrated_info *bios_parser_create_integrated_info( in bios_parser_create_integrated_info()
[all …]
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| D | bios_parser.c | 116 kfree(bp->base.integrated_info); in bios_parser_destruct()
2239 struct integrated_info *info) in get_integrated_info_v8()
2389 struct integrated_info *info) in get_integrated_info_v9()
2526 struct integrated_info *info) in construct_integrated_info()
2575 static struct integrated_info *bios_parser_create_integrated_info( in bios_parser_create_integrated_info()
2579 struct integrated_info *info; in bios_parser_create_integrated_info()
2581 info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); in bios_parser_create_integrated_info()
2926 bp->base.integrated_info = bios_parser_create_integrated_info(&bp->base); in bios_parser_construct()
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| /drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 568 struct integrated_info *bios_info, in dcn314_clk_mgr_helper_populate_bw_params()
770 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) in dcn314_clk_mgr_construct()
830 …if (ctx->dc_bios && ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == fa… in dcn314_clk_mgr_construct()
833 ctx->dc_bios->integrated_info, in dcn314_clk_mgr_construct()
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| /drivers/gpu/drm/amd/display/include/ |
| D | grph_object_ctrl_defs.h | 299 struct integrated_info { struct
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_resource.c | 1053 if (link->ctx->dc_bios->integrated_info) in dcn201_link_init()
1054 link->dp_ss_off = !link->ctx->dc_bios->integrated_info->dp_ss_control; in dcn201_link_init()
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