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Searched refs:internal (Results 1 – 25 of 180) sorted by relevance

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/drivers/media/dvb-frontends/
Dstb0899_algo.c50 struct stb0899_internal *internal = &state->internal;
55 return stb0899_calc_srate(internal->master_clk, sfr);
122 struct stb0899_internal *internal = &state->internal; in stb0899_carr_width() local
124 return (internal->srate + (internal->srate * internal->rolloff) / 100); in stb0899_carr_width()
133 struct stb0899_internal *internal = &state->internal; in stb0899_first_subrange() local
148 internal->sub_range = min(internal->srch_range, range); in stb0899_first_subrange()
150 internal->sub_range = 0; in stb0899_first_subrange()
152 internal->freq = params->freq; in stb0899_first_subrange()
153 internal->tuner_offst = 0L; in stb0899_first_subrange()
154 internal->sub_dir = 1; in stb0899_first_subrange()
[all …]
Dstb0899_drv.c558 struct stb0899_internal *internal = &state->internal; in stb0899_set_mclk() local
566 internal->master_clk = stb0899_get_mclk(state); in stb0899_set_mclk()
568 dprintk(state->verbose, FE_DEBUG, 1, "MasterCLOCK=%d", internal->master_clk); in stb0899_set_mclk()
630 struct stb0899_internal *internal = &state->internal; in stb0899_init_calc() local
640 internal->t_agc1 = 0; in stb0899_init_calc()
641 internal->t_agc2 = 0; in stb0899_init_calc()
642 internal->master_clk = master_clk; in stb0899_init_calc()
643 internal->mclk = master_clk / 65536L; in stb0899_init_calc()
644 internal->rolloff = stb0899_get_alpha(state); in stb0899_init_calc()
648 internal->agc_gain = 8154; in stb0899_init_calc()
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Dstv090x.c35 struct stv090x_internal *internal; member
52 ((temp_dev->internal->i2c_adap != i2c_adap) || in find_dev()
53 (temp_dev->internal->i2c_addr != i2c_addr))) { in find_dev()
62 static void remove_dev(struct stv090x_internal *internal) in remove_dev() argument
65 struct stv090x_dev *del_dev = find_dev(internal->i2c_adap, in remove_dev()
66 internal->i2c_addr); in remove_dev()
83 static struct stv090x_dev *append_internal(struct stv090x_internal *internal) in append_internal() argument
90 new_dev->internal = internal; in append_internal()
768 mutex_lock(&state->internal->tuner_lock); in stv090x_i2c_gate_ctrl()
789 mutex_unlock(&state->internal->tuner_lock); in stv090x_i2c_gate_ctrl()
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Dstv0900_core.c29 struct stv0900_internal *internal; member
47 ((temp_chip->internal->i2c_adap != i2c_adap) || in find_inode()
48 (temp_chip->internal->i2c_addr != i2c_addr))) in find_inode()
58 static void remove_inode(struct stv0900_internal *internal) in remove_inode() argument
61 struct stv0900_inode *del_node = find_inode(internal->i2c_adap, in remove_inode()
62 internal->i2c_addr); in remove_inode()
83 static struct stv0900_inode *append_internal(struct stv0900_internal *internal) in append_internal() argument
103 new_node->internal = internal; in append_internal()
350 struct stv0900_internal *intp = state->internal; in stv0900_i2c_gate_ctrl()
642 struct stv0900_internal *internal = state->internal; in stv0900_read_signal_strength() local
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Ddib7000p.c472 dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff)); in dib7000p_reset_pll()
473 dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff)); in dib7000p_reset_pll()
482 u32 internal = (u32) dib7000p_read_word(state, 18) << 16; in dib7000p_get_internal_freq() local
483 internal |= (u32) dib7000p_read_word(state, 19); in dib7000p_get_internal_freq()
484 internal /= 1000; in dib7000p_get_internal_freq()
486 return internal; in dib7000p_get_internal_freq()
494 u32 internal, xtal; in dib7000p_update_pll() local
509 internal = dib7000p_get_internal_freq(state); in dib7000p_update_pll()
510 xtal = (internal / loopdiv) * prediv; in dib7000p_update_pll()
511 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ in dib7000p_update_pll()
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Ddib8000.c677 (u16) (((bw->internal * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
679 (u16) ((bw->internal * 1000) & 0xffff)); in dib8000_reset_pll_common()
681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
683 (u16) ((bw->internal / 2 * 1000) & 0xffff)); in dib8000_reset_pll_common()
751 u32 internal, xtal; in dib8000_update_pll() local
773 internal = dib8000_read32(state, 23) / 1000; in dib8000_update_pll()
774 dprintk("Old Internal = %d\n", internal); in dib8000_update_pll()
775 xtal = 2 * (internal / loopdiv) * prediv; in dib8000_update_pll()
776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
777 … Fmem = %d New Fdemod = %d, New Fsampling = %d\n", xtal, internal/1000, internal/2000, internal/80… in dib8000_update_pll()
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/drivers/media/pci/cx23885/
Daltera-ci.c111 struct fpga_internal *internal; member
119 struct fpga_internal *internal; member
132 struct fpga_internal *internal; member
151 (temp_chip->internal->dev != dev)) in find_inode()
183 if (temp_chip->internal != NULL) { in find_dinode()
184 temp_int = temp_chip->internal; in find_dinode()
198 static void remove_inode(struct fpga_internal *internal) in remove_inode() argument
201 struct fpga_inode *del_node = find_inode(internal->dev); in remove_inode()
222 static struct fpga_inode *append_internal(struct fpga_internal *internal) in append_internal() argument
242 new_node->internal = internal; in append_internal()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c216 static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *cl… in vg_dump_clk_registers_internal() argument
220 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT); in vg_dump_clk_registers_internal()
221 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL); in vg_dump_clk_registers_internal()
223 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in vg_dump_clk_registers_internal()
224 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS); in vg_dump_clk_registers_internal()
226 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT); in vg_dump_clk_registers_internal()
227 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL); in vg_dump_clk_registers_internal()
229 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT); in vg_dump_clk_registers_internal()
230 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL); in vg_dump_clk_registers_internal()
232 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT); in vg_dump_clk_registers_internal()
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/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c284 static void rn_dump_clk_registers_internal(struct rn_clk_internal *internal, struct clk_mgr *clk_mg… in rn_dump_clk_registers_internal() argument
288 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT); in rn_dump_clk_registers_internal()
289 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL); in rn_dump_clk_registers_internal()
291 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL); //dcf deep sleep divider in rn_dump_clk_registers_internal()
292 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS); in rn_dump_clk_registers_internal()
294 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT); in rn_dump_clk_registers_internal()
295 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL); in rn_dump_clk_registers_internal()
297 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT); in rn_dump_clk_registers_internal()
298 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL); in rn_dump_clk_registers_internal()
300 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT); in rn_dump_clk_registers_internal()
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/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_0.c140 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
141 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
142 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
143 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
144 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
145 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
147 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
149 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
151 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
153 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v2_0_sw_init()
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Dvcn_v3_0.c159 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
160 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
161 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
162 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
163 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
164 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
166 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
168 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
170 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
172 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET; in vcn_v3_0_sw_init()
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/drivers/net/ethernet/freescale/fman/
DKconfig23 internal resource leak thus stopping further packet processing.
24 The FMAN internal queue can overflow when FMAN splits single
27 to interconnect. When the FMAN internal queue overflows, it can
/drivers/gpu/drm/imx/ipuv3/
DKconfig24 Choose this to enable the internal Television Encoder (TVe)
33 Choose this to enable the internal LVDS Display Bridge (LDB)
/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dbus.c215 const bool internal = false; in nvkm_i2c_bus_ctor() local
217 const bool internal = true; in nvkm_i2c_bus_ctor() local
234 !nvkm_boolopt(device->cfgopt, "NvI2C", internal)) { in nvkm_i2c_bus_ctor()
/drivers/gpu/drm/bridge/cadence/
DKconfig11 Support Cadence DPI to DSI bridge. This is an internal
33 Support Cadence DPI to DP bridge. This is an internal
/drivers/gpu/drm/bridge/imx/
DKconfig13 Choose this to enable the internal LVDS Display Bridge(LDB) found in
23 Choose this to enable the internal LVDS Display Bridge(LDB) found in
/drivers/net/ethernet/intel/i40e/
Di40e_debugfs.c1298 &desc->params.internal.param0, in i40e_dbg_command_write()
1299 &desc->params.internal.param1, in i40e_dbg_command_write()
1300 &desc->params.internal.param2, in i40e_dbg_command_write()
1301 &desc->params.internal.param3); in i40e_dbg_command_write()
1326 desc->params.internal.param0, in i40e_dbg_command_write()
1327 desc->params.internal.param1, in i40e_dbg_command_write()
1328 desc->params.internal.param2, in i40e_dbg_command_write()
1329 desc->params.internal.param3); in i40e_dbg_command_write()
1346 &desc->params.internal.param0, in i40e_dbg_command_write()
1347 &desc->params.internal.param1, in i40e_dbg_command_write()
[all …]
/drivers/pci/controller/
DKconfig263 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
264 There are 3 internal PCI controllers available with a single
279 Say Y here if you want internal PCI support on Rockchip SoC.
280 There is 1 internal PCIe port available to support GEN2 with
292 endpoint mode on Rockchip SoC. There is 1 internal PCIe port
306 Say Y here if you want internal PCI support on APM X-Gene SoC.
307 There are 5 internal PCIe ports available. Each port is GEN3 capable
/drivers/net/ethernet/broadcom/
DKconfig55 tristate "Broadcom BCM4908 internal mac support"
63 tristate "Broadcom 63xx internal mac support"
72 tristate "Broadcom GENET internal MAC support"
195 tristate "Broadcom SYSTEMPORT internal MAC support"
204 Broadcom BCM7xxx Set Top Box family chipset using an internal
/drivers/staging/media/ipu3/
Dipu3-css-fw.c41 bi->info.isp.sp.internal.max_width, in imgu_css_fw_show_binary()
42 bi->info.isp.sp.internal.max_height); in imgu_css_fw_show_binary()
59 unsigned int width = DIV_ROUND_UP(bi->info.isp.sp.internal.max_width, in imgu_css_fw_obgrid_size()
61 unsigned int height = DIV_ROUND_UP(bi->info.isp.sp.internal.max_height, in imgu_css_fw_obgrid_size()
/drivers/net/phy/
DKconfig130 tristate "Broadcom 63xx SOCs internal PHY"
137 tristate "Broadcom 7xxx SOCs internal PHYs"
154 tristate "Broadcom Cygnus/Omega SoC internal PHY"
159 This PHY driver is for the 1G internal PHYs of the Broadcom
162 Currently supports internal PHY's used in the BCM11300,
328 Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
/drivers/usb/gadget/udc/aspeed-vhub/
Dep0.c369 if (!u_req || (!u_req->complete && !req->internal)) { in ast_vhub_ep0_queue()
373 u_req->complete, req->internal); in ast_vhub_ep0_queue()
387 if (u_req->length && !u_req->buf && !req->internal) { in ast_vhub_ep0_queue()
504 ep->ep0.req.internal = true; in ast_vhub_init_ep0()
/drivers/net/ethernet/sun/
Dsunbmac.c270 if (bp->tcvr_type == internal) { in write_tcvr_bit()
295 if (bp->tcvr_type == internal) { in read_tcvr_bit()
318 if (bp->tcvr_type == internal) { in read_tcvr_bit2()
356 case internal: in bigmac_tcvr_write()
372 ((bp->tcvr_type == internal) ? in bigmac_tcvr_write()
395 case internal: in bigmac_tcvr_read()
411 ((bp->tcvr_type == internal) ? in bigmac_tcvr_read()
478 bp->tcvr_type = internal; in bigmac_tcvr_init()
/drivers/phy/tegra/
Dxusb.h318 bool internal; member
338 bool internal; member
365 bool internal; member
/drivers/gpu/drm/i915/display/
Dintel_load_detect.c129 to_intel_atomic_state(state)->internal = true; in intel_load_detect_get_pipe()
132 to_intel_atomic_state(restore_state)->internal = true; in intel_load_detect_get_pipe()

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