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Searched refs:io_base (Results 1 – 25 of 141) sorted by relevance

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/drivers/staging/vt6655/
Dmac.c100 void __iomem *io_base = priv->port_offset; in vt6655_mac_is_reg_bits_off() local
102 return !(ioread8(io_base + reg_offset) & mask); in vt6655_mac_is_reg_bits_off()
121 void __iomem *io_base = priv->port_offset; in vt6655_mac_set_short_retry_limit() local
123 iowrite8(retry_limit, io_base + MAC_REG_SRT); in vt6655_mac_set_short_retry_limit()
143 void __iomem *io_base = priv->port_offset; in MACvSetLongRetryLimit() local
145 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); in MACvSetLongRetryLimit()
164 void __iomem *io_base = priv->port_offset; in vt6655_mac_set_loopback_mode() local
168 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | loopback_mode, io_base + MAC_REG_TEST); in vt6655_mac_set_loopback_mode()
186 void __iomem *io_base = priv->port_offset; in vt6655_mac_save_context() local
189 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0); in vt6655_mac_save_context()
[all …]
/drivers/gpu/drm/meson/
Dmeson_venc.c1046 priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_venc_hdmi_mode_set()
1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1057 priv->io_base + _REG(ENCI_CFILT_CTRL)); in meson_venc_hdmi_mode_set()
1060 priv->io_base + _REG(ENCI_CFILT_CTRL2)); in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1066 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1067 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1071 priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN)); in meson_venc_hdmi_mode_set()
1073 priv->io_base + _REG(ENCI_SYNC_HSO_END)); in meson_venc_hdmi_mode_set()
[all …]
Dmeson_viu.c86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
[all …]
Dmeson_crtc.c100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_g12a_crtc_atomic_enable()
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_g12a_crtc_atomic_enable()
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE)); in meson_g12a_crtc_atomic_enable()
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE)); in meson_g12a_crtc_atomic_enable()
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE)); in meson_g12a_crtc_atomic_enable()
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE)); in meson_crtc_atomic_enable()
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END)); in meson_crtc_atomic_enable()
143 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_enable()
192 priv->io_base + _REG(VPP_MISC)); in meson_crtc_atomic_disable()
246 priv->io_base + _REG(VPP_MISC)); in meson_crtc_enable_osd1()
[all …]
Dmeson_vpp.c38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL)); in meson_vpp_setup_mux()
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX)); in meson_vpp_write_scaling_filter_coefs()
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
100 priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 priv->io_base + _REG(VPP_DUMMY_DATA)); in meson_vpp_init()
[all …]
Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
Dmeson_osd_afbcd.c85 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
133 writel_relaxed(mode, priv->io_base + _REG(OSD1_AFBCD_MODE)); in meson_gxm_afbcd_setup()
139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
163 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
[all …]
/drivers/watchdog/
Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
60 outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
61 outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL); in ni903x_start()
70 outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2); in ni903x_wdd_set_timeout()
71 outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1); in ni903x_wdd_set_timeout()
72 outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0); in ni903x_wdd_set_timeout()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
[all …]
Dnic7018_wdt.c46 u16 io_base; member
96 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
111 control = inb(wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
112 outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_start()
114 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
116 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
117 outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL); in nic7018_start()
126 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
127 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
128 outb(0xF0, wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_stop()
[all …]
/drivers/crypto/hisilicon/hpre/
Dhpre_main.c467 val1 = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
468 val2 = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
476 writel_relaxed(val1, qm->io_base + HPRE_DATA_RUSER_CFG); in hpre_config_pasid()
477 writel_relaxed(val2, qm->io_base + HPRE_DATA_WUSER_CFG); in hpre_config_pasid()
520 qm->io_base + offset + HPRE_CORE_ENB); in hpre_set_cluster()
521 writel(0x1, qm->io_base + offset + HPRE_CORE_INI_CFG); in hpre_set_cluster()
522 ret = readl_relaxed_poll_timeout(qm->io_base + offset + in hpre_set_cluster()
547 val = readl(qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
550 writel(val, qm->io_base + QM_PEH_AXUSER_CFG); in disable_flr_of_bme()
551 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in disable_flr_of_bme()
[all …]
/drivers/crypto/hisilicon/sec2/
Dsec_main.c428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
444 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
447 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
450 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
454 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
457 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
460 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
462 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
469 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
[all …]
/drivers/crypto/intel/keembay/
Docs-hcu.c173 return readl_poll_timeout(hcu_dev->io_base + OCS_HCU_STATUS, val, in ocs_hcu_wait_busy()
182 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_done_irq_en()
186 hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_done_irq_en()
192 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_DMA_MSI_ISR); in ocs_hcu_dma_irq_en()
196 hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_dma_irq_en()
198 writel(HCU_DMA_MSI_UNMASK, hcu_dev->io_base + OCS_HCU_DMA_MSI_MASK); in ocs_hcu_dma_irq_en()
203 writel(HCU_IRQ_DISABLE, hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_irq_dis()
204 writel(HCU_DMA_MSI_DISABLE, hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_irq_dis()
270 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_intermediate_data()
272 data->msg_len_lo = readl(hcu_dev->io_base + OCS_HCU_MSG_LEN_LO); in ocs_hcu_get_intermediate_data()
[all …]
/drivers/fpga/
Dts73xx-fpga.c31 void __iomem *io_base; member
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
59 ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG, in ts73xx_fpga_write()
65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
88 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
[all …]
/drivers/hwspinlock/
Du8500_hsem.c90 void __iomem *io_base; in u8500_hsem_probe() local
97 io_base = devm_platform_ioremap_resource(pdev, 0); in u8500_hsem_probe()
98 if (IS_ERR(io_base)) in u8500_hsem_probe()
99 return PTR_ERR(io_base); in u8500_hsem_probe()
102 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
106 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
129 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
/drivers/mtd/spi-nor/controllers/
Dnxp-spifi.c56 void __iomem *io_base; member
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
114 writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD); in nxp_spifi_set_memory_mode_on()
115 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_set_memory_mode_on()
140 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
143 *buf++ = readb(spifi->io_base + SPIFI_DATA); in nxp_spifi_read_reg()
164 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
167 writeb(*buf++, spifi->io_base + SPIFI_DATA); in nxp_spifi_write_reg()
[all …]
/drivers/mtd/nand/raw/
Dlpc32xx_slc.c219 void __iomem *io_base; member
241 writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base)); in lpc32xx_nand_setup()
245 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
246 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
248 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
264 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
277 tmp = readl(SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
282 writel(tmp, SLC_CFG(host->io_base)); in lpc32xx_nand_cmd_ctrl()
286 writel(cmd, SLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
288 writel(cmd, SLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
Dlpc32xx_mlc.c180 void __iomem *io_base; member
236 writel(MLCCMD_RESET, MLC_CMD(host->io_base)); in lpc32xx_nand_setup()
246 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
250 writel(tmp, MLC_ICR(host->io_base)); in lpc32xx_nand_setup()
254 writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base)); in lpc32xx_nand_setup()
265 writel(tmp, MLC_TIME_REG(host->io_base)); in lpc32xx_nand_setup()
269 MLC_IRQ_MR(host->io_base)); in lpc32xx_nand_setup()
272 writel(MLCCEH_NORMAL, MLC_CEH(host->io_base)); in lpc32xx_nand_setup()
285 writel(cmd, MLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
287 writel(cmd, MLC_ADDR(host->io_base)); in lpc32xx_nand_cmd_ctrl()
[all …]
Dsocrates_nand.c28 void __iomem *io_base; member
45 out_be32(host->io_base, FPGA_NAND_ENABLE | in socrates_nand_write_buf()
66 out_be32(host->io_base, val); in socrates_nand_read_buf()
68 buf[i] = (in_be32(host->io_base) >> in socrates_nand_read_buf()
106 out_be32(host->io_base, val); in socrates_nand_cmd_ctrl()
116 if (in_be32(host->io_base) & FPGA_NAND_BUSY) in socrates_nand_device_ready()
149 host->io_base = of_iomap(ofdev->dev.of_node, 0); in socrates_nand_probe()
150 if (host->io_base == NULL) { in socrates_nand_probe()
198 iounmap(host->io_base); in socrates_nand_probe()
215 iounmap(host->io_base); in socrates_nand_remove()
Dorion_nand.c54 void __iomem *io_base = chip->legacy.IO_ADDR_R; in orion_nand_read_buf() local
61 *buf++ = readb(io_base); in orion_nand_read_buf()
74 asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base)); in orion_nand_read_buf()
79 readsl(io_base, buf, len/4); in orion_nand_read_buf()
83 buf[i++] = readb(io_base); in orion_nand_read_buf()
105 void __iomem *io_base; in orion_nand_probe() local
121 io_base = devm_platform_ioremap_resource(pdev, 0); in orion_nand_probe()
123 if (IS_ERR(io_base)) in orion_nand_probe()
124 return PTR_ERR(io_base); in orion_nand_probe()
155 nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base; in orion_nand_probe()
/drivers/mtd/devices/
Dspear_smi.c174 void __iomem *io_base; member
229 ctrlreg1 = readl(dev->io_base + SMI_CR1); in spear_smi_read_sr()
231 writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1); in spear_smi_read_sr()
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
248 writel(ctrlreg1, dev->io_base + SMI_CR1); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
301 status = readl(dev->io_base + SMI_SR); in spear_smi_int_handler()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
[all …]
/drivers/crypto/hisilicon/zip/
Dzip_main.c477 val = readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
484 writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); in hisi_zip_set_high_perf()
485 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, in hisi_zip_set_high_perf()
503 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
505 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
507 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_PREFETCH_CFG, in hisi_zip_open_sva_prefetch()
522 val = readl_relaxed(qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
524 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
526 ret = readl_relaxed_poll_timeout(qm->io_base + HZIP_SVA_TRANS, in hisi_zip_close_sva_prefetch()
540 val = readl(qm->io_base + HZIP_CLOCK_GATE_CTRL); in hisi_zip_enable_clock_gate()
[all …]
/drivers/input/keyboard/
Dspear-keyboard.c57 void __iomem *io_base; member
76 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
86 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
97 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
121 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
122 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
127 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
140 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
[all …]
/drivers/spi/
Dspi-stm32-qspi.c104 void __iomem *io_base; member
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
184 ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, in stm32_qspi_tx_poll()
192 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
247 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
259 writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
270 writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
[all …]
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_ptp.c12 ptp->cycle.quo = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG) & in hclge_ptp_get_cycle()
14 ptp->cycle.numer = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); in hclge_ptp_get_cycle()
15 ptp->cycle.den = readl(hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_get_cycle()
45 hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG); in hclge_ptp_adjfine()
46 writel(numerator, hdev->ptp->io_base + HCLGE_PTP_CYCLE_NUM_REG); in hclge_ptp_adjfine()
47 writel(cycle->den, hdev->ptp->io_base + HCLGE_PTP_CYCLE_DEN_REG); in hclge_ptp_adjfine()
49 hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG); in hclge_ptp_adjfine()
81 ns = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_NSEC_REG) & in hclge_ptp_clean_tx_hwts()
83 lo = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_L_REG); in hclge_ptp_clean_tx_hwts()
84 hi = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_H_REG) & in hclge_ptp_clean_tx_hwts()
[all …]
/drivers/mfd/
Dtqmx86.c183 void __iomem *io_base; in tqmx86_probe() local
204 io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE); in tqmx86_probe()
205 if (!io_base) in tqmx86_probe()
208 board_id = ioread8(io_base + TQMX86_REG_BOARD_ID); in tqmx86_probe()
209 sauc = ioread8(io_base + TQMX86_REG_SAUC); in tqmx86_probe()
211 rev = ioread8(io_base + TQMX86_REG_BOARD_REV); in tqmx86_probe()
227 iowrite8(io_ext_int_val, io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_probe()
228 readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_probe()

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