| /drivers/accel/habanalabs/gaudi/ |
| D | gaudi_security.c | 489 u32 pb_addr, mask; in gaudi_init_mme_protection_bits() local
515 mask = 1U << ((mmMME0_CTRL_RESET & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
516 mask |= 1U << ((mmMME0_CTRL_QM_STALL & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
517 mask |= 1U << ((mmMME0_CTRL_SYNC_OBJECT_FIFO_TH & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
518 mask |= 1U << ((mmMME0_CTRL_EUS_ROLLUP_CNT_ADD & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
519 mask |= 1U << ((mmMME0_CTRL_INTR_CAUSE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
520 mask |= 1U << ((mmMME0_CTRL_INTR_MASK & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
521 mask |= 1U << ((mmMME0_CTRL_LOG_SHADOW & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
522 mask |= 1U << ((mmMME0_CTRL_PCU_RL_DESC0 & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
523 mask |= 1U << ((mmMME0_CTRL_PCU_RL_TOKEN_UPDATE & 0x7F) >> 2); in gaudi_init_mme_protection_bits()
[all …]
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| /drivers/accel/habanalabs/goya/ |
| D | goya_security.c | 30 u32 pb_addr, mask; in goya_init_mme_protection_bits() local
69 mask = 1 << ((mmMME_DUMMY & 0x7F) >> 2); in goya_init_mme_protection_bits()
70 mask |= 1 << ((mmMME_RESET & 0x7F) >> 2); in goya_init_mme_protection_bits()
71 mask |= 1 << ((mmMME_STALL & 0x7F) >> 2); in goya_init_mme_protection_bits()
72 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_LOW & 0x7F) >> 2); in goya_init_mme_protection_bits()
73 mask |= 1 << ((mmMME_SM_BASE_ADDRESS_HIGH & 0x7F) >> 2); in goya_init_mme_protection_bits()
74 mask |= 1 << ((mmMME_DBGMEM_ADD & 0x7F) >> 2); in goya_init_mme_protection_bits()
75 mask |= 1 << ((mmMME_DBGMEM_DATA_WR & 0x7F) >> 2); in goya_init_mme_protection_bits()
76 mask |= 1 << ((mmMME_DBGMEM_DATA_RD & 0x7F) >> 2); in goya_init_mme_protection_bits()
77 mask |= 1 << ((mmMME_DBGMEM_CTRL & 0x7F) >> 2); in goya_init_mme_protection_bits()
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) argument
34 #define SetBF(mask,value) ((value) << (0?mask)) argument
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
54 #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
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| /drivers/mfd/ |
| D | sec-irq.c | 22 .mask = S2MPS11_IRQ_PWRONF_MASK,
26 .mask = S2MPS11_IRQ_PWRONR_MASK,
30 .mask = S2MPS11_IRQ_JIGONBF_MASK,
34 .mask = S2MPS11_IRQ_JIGONBR_MASK,
38 .mask = S2MPS11_IRQ_ACOKBF_MASK,
42 .mask = S2MPS11_IRQ_ACOKBR_MASK,
46 .mask = S2MPS11_IRQ_PWRON1S_MASK,
50 .mask = S2MPS11_IRQ_MRB_MASK,
54 .mask = S2MPS11_IRQ_RTC60S_MASK,
58 .mask = S2MPS11_IRQ_RTCA1_MASK,
[all …]
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| D | wm8350-irq.c | 37 int mask; member
45 .mask = WM8350_OC_LS_EINT,
51 .mask = WM8350_UV_DC1_EINT,
56 .mask = WM8350_UV_DC2_EINT,
61 .mask = WM8350_UV_DC3_EINT,
66 .mask = WM8350_UV_DC4_EINT,
71 .mask = WM8350_UV_DC5_EINT,
76 .mask = WM8350_UV_DC6_EINT,
81 .mask = WM8350_UV_LDO1_EINT,
86 .mask = WM8350_UV_LDO2_EINT,
[all …]
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| D | wm831x-irq.c | 28 int mask; member
35 .mask = WM831X_TEMP_THW_EINT,
40 .mask = WM831X_GP1_EINT,
45 .mask = WM831X_GP2_EINT,
50 .mask = WM831X_GP3_EINT,
55 .mask = WM831X_GP4_EINT,
60 .mask = WM831X_GP5_EINT,
65 .mask = WM831X_GP6_EINT,
70 .mask = WM831X_GP7_EINT,
75 .mask = WM831X_GP8_EINT,
[all …]
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| D | da9052-irq.c | 38 .mask = DA9052_IRQ_MASK_POS_1,
42 .mask = DA9052_IRQ_MASK_POS_2,
46 .mask = DA9052_IRQ_MASK_POS_3,
50 .mask = DA9052_IRQ_MASK_POS_4,
54 .mask = DA9052_IRQ_MASK_POS_5,
58 .mask = DA9052_IRQ_MASK_POS_6,
62 .mask = DA9052_IRQ_MASK_POS_7,
66 .mask = DA9052_IRQ_MASK_POS_8,
70 .mask = DA9052_IRQ_MASK_POS_1,
74 .mask = DA9052_IRQ_MASK_POS_2,
[all …]
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| D | wm5110-tables.c | 285 .mask = ARIZONA_MICD_CLAMP_FALL_EINT1
288 .mask = ARIZONA_MICD_CLAMP_RISE_EINT1
290 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
291 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
292 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
293 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
310 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
311 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
312 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
313 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
[all …]
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| D | palmas.c | 48 .mask = TPS65917_RESERVED,
51 .mask = TPS65917_INT1_STATUS_PWRON,
54 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
57 .mask = TPS65917_RESERVED,
60 .mask = TPS65917_INT1_STATUS_PWRDOWN,
63 .mask = TPS65917_INT1_STATUS_HOTDIE,
66 .mask = TPS65917_INT1_STATUS_VSYS_MON,
69 .mask = TPS65917_RESERVED,
73 .mask = TPS65917_RESERVED,
77 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
[all …]
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| /drivers/net/ethernet/chelsio/cxgb4/ |
| D | cxgb4_tc_u32_parse.h | 41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask);
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos() argument
49 f->mask.tos = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag() argument
61 mask_val = ntohl(mask) & 0x0000FFFF; in cxgb4_fill_ipv4_frag()
65 f->mask.frag = 1; in cxgb4_fill_ipv4_frag()
68 f->mask.frag = 1; in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto() argument
80 f->mask.proto = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip() argument
[all …]
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_matcher.c | 116 dr_mask_is_tnl_vxlan_gpe(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_vxlan_gpe() argument
119 return dr_mask_is_vxlan_gpe_set(&mask->misc3) && in dr_mask_is_tnl_vxlan_gpe()
157 dr_mask_is_tnl_geneve(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_geneve() argument
160 return dr_mask_is_tnl_geneve_set(&mask->misc) && in dr_mask_is_tnl_geneve()
174 static bool dr_mask_is_tnl_gtpu(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_gtpu() argument
177 return dr_mask_is_tnl_gtpu_set(&mask->misc3) && in dr_mask_is_tnl_gtpu()
186 static bool dr_mask_is_tnl_gtpu_dw_0(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_gtpu_dw_0() argument
189 return mask->misc3.gtpu_dw_0 && in dr_mask_is_tnl_gtpu_dw_0()
198 static bool dr_mask_is_tnl_gtpu_teid(struct mlx5dr_match_param *mask, in dr_mask_is_tnl_gtpu_teid() argument
201 return mask->misc3.gtpu_teid && in dr_mask_is_tnl_gtpu_teid()
[all …]
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| D | dr_ste.c | 11 u8 mask[DR_STE_SIZE_MASK]; member
79 memcpy(hw_ste->mask, bit_mask, DR_STE_SIZE_MASK); in mlx5dr_ste_set_bit_mask()
85 memset(&hw_ste->mask, 0, sizeof(hw_ste->mask)); in dr_ste_set_always_hit()
91 hw_ste->mask[0] = 0; in dr_ste_set_always_miss()
715 struct mlx5dr_match_param *mask, in mlx5dr_ste_build_pre_check() argument
722 if (mask->misc.source_port && mask->misc.source_port != 0xffff) { in mlx5dr_ste_build_pre_check()
727 if (mask->misc.source_eswitch_owner_vhca_id && in mlx5dr_ste_build_pre_check()
728 mask->misc.source_eswitch_owner_vhca_id != 0xffff) { in mlx5dr_ste_build_pre_check()
736 dr_ste_build_pre_check_spec(dmn, &mask->outer)) in mlx5dr_ste_build_pre_check()
740 dr_ste_build_pre_check_spec(dmn, &mask->inner)) in mlx5dr_ste_build_pre_check()
[all …]
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| D | dr_ste_v1.h | 37 struct mlx5dr_match_param *mask);
39 struct mlx5dr_match_param *mask);
41 struct mlx5dr_match_param *mask);
43 struct mlx5dr_match_param *mask);
45 struct mlx5dr_match_param *mask);
47 struct mlx5dr_match_param *mask);
49 struct mlx5dr_match_param *mask);
51 struct mlx5dr_match_param *mask);
53 struct mlx5dr_match_param *mask);
55 struct mlx5dr_match_param *mask);
[all …]
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| /drivers/iio/imu/st_lsm6dsx/ |
| D | st_lsm6dsx_core.c | 107 .mask = BIT(0),
111 .mask = BIT(7),
115 .mask = BIT(6),
142 .mask = GENMASK(7, 5),
155 .mask = GENMASK(7, 5),
170 .mask = GENMASK(4, 3),
181 .mask = GENMASK(4, 3),
193 .mask = BIT(3),
197 .mask = BIT(3),
201 .mask = BIT(5),
[all …]
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| /drivers/iio/accel/ |
| D | st_accel_core.c | 128 .mask = 0xf0,
142 .mask = 0xf0,
147 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
151 .mask = 0x30,
177 .mask = 0x80,
182 .mask = 0x10,
188 .mask = 0x07,
210 .mask = 0x18,
220 .mask = 0xe0,
226 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
[all …]
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| /drivers/platform/x86/ |
| D | mlx-platform.c | 394 .mask = MLXPLAT_CPLD_I2C_CAP_MASK,
409 .mask = MLXPLAT_CPLD_AGGR_MASK_COMEX,
649 .mask = BIT(0),
655 .mask = BIT(1),
665 .mask = BIT(0),
671 .mask = BIT(1),
680 .mask = BIT(0),
687 .mask = BIT(1),
697 .mask = BIT(0),
703 .mask = BIT(1),
[all …]
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| /drivers/video/fbdev/ |
| D | c2p_core.h | 23 unsigned int shift, u32 mask) in _transp() argument
25 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; in _transp()
62 u32 mask = get_mask(n); in transp8() local
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
81 _transp(d, 4, 6, n, mask); in transp8()
[all …]
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| /drivers/gpu/drm/amd/display/dc/gpio/dce60/ |
| D | hw_translate_dce60.c | 48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
166 *en = index_from_vector(mask); in offset_to_id()
[all …]
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| /drivers/gpu/drm/amd/display/dc/gpio/dce80/ |
| D | hw_translate_dce80.c | 48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
166 *en = index_from_vector(mask); in offset_to_id()
[all …]
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| /drivers/input/joystick/ |
| D | analog.c | 93 int mask; member
102 unsigned char mask; member
124 if (analog->mask & ANALOG_HAT_FCS) in analog_decode()
132 if (analog->mask & (0x10 << i)) in analog_decode()
135 if (analog->mask & ANALOG_HBTN_CHF) in analog_decode()
139 if (analog->mask & ANALOG_BTN_TL) in analog_decode()
141 if (analog->mask & ANALOG_BTN_TR) in analog_decode()
143 if (analog->mask & ANALOG_BTN_TL2) in analog_decode()
145 if (analog->mask & ANALOG_BTN_TR2) in analog_decode()
149 if (analog->mask & (1 << i)) in analog_decode()
[all …]
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| /drivers/media/pci/ivtv/ |
| D | ivtv-gpio.c | 149 u16 mask, data; in subdev_s_clock_freq() local
151 mask = itv->card->gpio_audio_freq.mask; in subdev_s_clock_freq()
164 if (mask) in subdev_s_clock_freq()
165 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); in subdev_s_clock_freq()
172 u16 mask; in subdev_g_tuner() local
174 mask = itv->card->gpio_audio_detect.mask; in subdev_g_tuner()
175 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) in subdev_g_tuner()
186 u16 mask, data; in subdev_s_tuner() local
188 mask = itv->card->gpio_audio_mode.mask; in subdev_s_tuner()
205 if (mask) in subdev_s_tuner()
[all …]
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| /drivers/memory/tegra/ |
| D | tegra114.c | 22 .mask = 0xff,
38 .mask = 0xff,
54 .mask = 0xff,
70 .mask = 0xff,
86 .mask = 0xff,
102 .mask = 0xff,
118 .mask = 0xff,
134 .mask = 0xff,
150 .mask = 0xff,
166 .mask = 0xff,
[all …]
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| D | tegra210.c | 27 .mask = 0xff,
43 .mask = 0xff,
59 .mask = 0xff,
75 .mask = 0xff,
91 .mask = 0xff,
107 .mask = 0xff,
123 .mask = 0xff,
139 .mask = 0xff,
155 .mask = 0xff,
171 .mask = 0xff,
[all …]
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| /drivers/soc/ixp4xx/ |
| D | ixp4xx-qmgr.c | 209 u32 mask = 1 << (queue & (HALF_QUEUES - 1)); in qmgr_enable_irq() local
212 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, in qmgr_enable_irq()
221 u32 mask = 1 << (queue & (HALF_QUEUES - 1)); in qmgr_disable_irq() local
224 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, in qmgr_disable_irq()
226 __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ in qmgr_disable_irq()
230 static inline void shift_mask(u32 *mask) in shift_mask() argument
232 mask[3] = mask[3] << 1 | mask[2] >> 31; in shift_mask()
233 mask[2] = mask[2] << 1 | mask[1] >> 31; in shift_mask()
234 mask[1] = mask[1] << 1 | mask[0] >> 31; in shift_mask()
235 mask[0] <<= 1; in shift_mask()
[all …]
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| /drivers/pinctrl/spear/ |
| D | pinctrl-spear320.c | 36 .mask = 0x00000007,
44 .mask = 0x00000007,
52 .mask = 0x00000007,
60 .mask = 0x00000007,
68 .mask = 0x00000001,
465 .mask = PMX_PL_69_MASK,
469 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
477 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
483 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
522 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
[all …]
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