Home
last modified time | relevance | path

Searched refs:masks (Results 1 – 25 of 140) sorted by relevance

123456

/drivers/clk/mmp/
Dclk-frac.c35 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_round_rate()
54 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_recalc_rate() local
61 num = (val >> masks->num_shift) & masks->num_mask; in clk_factor_recalc_rate()
64 den = (val >> masks->den_shift) & masks->den_mask; in clk_factor_recalc_rate()
71 do_div(rate, num * factor->masks->factor); in clk_factor_recalc_rate()
81 struct mmp_clk_factor_masks *masks = factor->masks; in clk_factor_set_rate() local
90 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_set_rate()
103 val &= ~(masks->num_mask << masks->num_shift); in clk_factor_set_rate()
104 val |= (factor->ftbl[i].num & masks->num_mask) << masks->num_shift; in clk_factor_set_rate()
106 val &= ~(masks->den_mask << masks->den_shift); in clk_factor_set_rate()
[all …]
/drivers/clk/spear/
Dclk-aux-synth.c77 eqn = (val >> aux->masks->eq_sel_shift) & aux->masks->eq_sel_mask; in clk_aux_recalc_rate()
78 if (eqn == aux->masks->eq1_mask) in clk_aux_recalc_rate()
82 num = (val >> aux->masks->xscale_sel_shift) & in clk_aux_recalc_rate()
83 aux->masks->xscale_sel_mask; in clk_aux_recalc_rate()
86 den *= (val >> aux->masks->yscale_sel_shift) & in clk_aux_recalc_rate()
87 aux->masks->yscale_sel_mask; in clk_aux_recalc_rate()
111 ~(aux->masks->eq_sel_mask << aux->masks->eq_sel_shift); in clk_aux_set_rate()
112 val |= (rtbl[i].eq & aux->masks->eq_sel_mask) << in clk_aux_set_rate()
113 aux->masks->eq_sel_shift; in clk_aux_set_rate()
114 val &= ~(aux->masks->xscale_sel_mask << aux->masks->xscale_sel_shift); in clk_aux_set_rate()
[all …]
/drivers/net/dsa/microchip/
Dksz8795.c165 const u32 *masks; in ksz8_r_mib_cnt() local
172 masks = dev->info->masks; in ksz8_r_mib_cnt()
187 if (check & masks[MIB_COUNTER_VALID]) { in ksz8_r_mib_cnt()
189 if (check & masks[MIB_COUNTER_OVERFLOW]) in ksz8_r_mib_cnt()
201 const u32 *masks; in ksz8795_r_mib_pkt() local
208 masks = dev->info->masks; in ksz8795_r_mib_pkt()
225 if (check & masks[MIB_COUNTER_VALID]) { in ksz8795_r_mib_pkt()
234 if (check & masks[MIB_COUNTER_OVERFLOW]) { in ksz8795_r_mib_pkt()
240 if (check & masks[MIB_COUNTER_OVERFLOW]) in ksz8795_r_mib_pkt()
386 const u32 *masks; in ksz8_valid_dyn_entry() local
[all …]
Dksz9477.c670 const u32 *masks; in ksz9477_mdb_add() local
677 masks = dev->info->masks; in ksz9477_mdb_add()
688 masks[ALU_STAT_READ] | ALU_STAT_START; in ksz9477_mdb_add()
749 const u32 *masks; in ksz9477_mdb_del() local
756 masks = dev->info->masks; in ksz9477_mdb_del()
767 masks[ALU_STAT_READ] | ALU_STAT_START; in ksz9477_mdb_del()
1067 const u32 *masks; in ksz9477_enable_stp_addr() local
1071 masks = dev->info->masks; in ksz9477_enable_stp_addr()
1082 data = ALU_STAT_START | ALU_RESV_MCAST_ADDR | masks[ALU_STAT_WRITE]; in ksz9477_enable_stp_addr()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c119 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
121 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
214 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
216 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
261 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
263 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
265 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
267 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
270 reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
272 reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B; in dpp1_cm_get_reg_field()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_i2c_hw.c41 dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
80 else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK) in get_channel_status()
82 else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT) in get_channel_status()
84 else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED) in get_channel_status()
86 else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE) in get_channel_status()
287 if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL) in set_speed()
622 const struct dce_i2c_mask *masks) in dce_i2c_hw_construct() argument
629 dce_i2c_hw->masks = masks; in dce_i2c_hw_construct()
645 const struct dce_i2c_mask *masks) in dce100_i2c_hw_construct() argument
652 masks); in dce100_i2c_hw_construct()
[all …]
Ddce_i2c_hw.h292 const struct dce_i2c_mask *masks; member
301 const struct dce_i2c_mask *masks);
309 const struct dce_i2c_mask *masks);
317 const struct dce_i2c_mask *masks);
325 const struct dce_i2c_mask *masks);
333 const struct dce_i2c_mask *masks);
Ddce_hwseq.c38 hws->shifts->field_name, hws->masks->field_name
75 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
129 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
Ddce_audio.c44 aud->shifts->field_name, aud->masks->field_name
1052 const struct dce_audio_mask *masks in dce_audio_create() argument
1068 audio->masks = masks; in dce_audio_create()
1078 const struct dce_audio_mask *masks in dce60_audio_create() argument
1094 audio->masks = masks; in dce60_audio_create()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dwb_cm.c53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B; in dwb3_get_reg_field_ogam()
73 reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in dwb3_get_reg_field_ogam()
[all …]
Ddcn30_dpp_cm.c177 reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B; in dpp3_gamcor_reg_field()
179 reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B; in dpp3_gamcor_reg_field()
182 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET; in dpp3_gamcor_reg_field()
184 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
186 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET; in dpp3_gamcor_reg_field()
188 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp3_gamcor_reg_field()
191 reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B; in dpp3_gamcor_reg_field()
193 reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B; in dpp3_gamcor_reg_field()
195 reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B; in dpp3_gamcor_reg_field()
197 reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B; in dpp3_gamcor_reg_field()
[all …]
Ddcn30_mpc.c180 reg->masks.field_region_start_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; in mpc3_ogam_get_reg_field()
182 reg->masks.field_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_OFFSET_B; in mpc3_ogam_get_reg_field()
185 reg->masks.exp_region0_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc3_ogam_get_reg_field()
187 reg->masks.exp_region0_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
189 reg->masks.exp_region1_lut_offset = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc3_ogam_get_reg_field()
191 reg->masks.exp_region1_num_segments = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc3_ogam_get_reg_field()
194 reg->masks.field_region_end = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc3_ogam_get_reg_field()
196 reg->masks.field_region_end_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc3_ogam_get_reg_field()
198 reg->masks.field_region_end_base = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; in mpc3_ogam_get_reg_field()
200 reg->masks.field_region_linear_slope = mpc30->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; in mpc3_ogam_get_reg_field()
[all …]
/drivers/net/ethernet/intel/ice/
Dice_flex_pipe.c1173 for (i = hw->blk[blk].masks.first; i < hw->blk[blk].masks.first + in ice_prof_has_mask_idx()
1174 hw->blk[blk].masks.count; i++) in ice_prof_has_mask_idx()
1176 if (hw->blk[blk].masks.masks[i].in_use && in ice_prof_has_mask_idx()
1177 hw->blk[blk].masks.masks[i].idx == idx) { in ice_prof_has_mask_idx()
1179 if (hw->blk[blk].masks.masks[i].mask == mask) in ice_prof_has_mask_idx()
1203 ice_prof_has_mask(struct ice_hw *hw, enum ice_block blk, u8 prof, u16 *masks) in ice_prof_has_mask() argument
1209 if (!ice_prof_has_mask_idx(hw, blk, prof, i, masks[i])) in ice_prof_has_mask()
1225 struct ice_fv_word *fv, u16 *masks, u8 *prof_id) in ice_find_prof_id_with_mask() argument
1243 if (masks && !ice_prof_has_mask(hw, blk, i, masks)) in ice_find_prof_id_with_mask()
1472 mutex_init(&hw->blk[blk].masks.lock); in ice_init_prof_masks()
[all …]
/drivers/virtio/
Dvirtio_vdpa.c306 struct cpumask *masks = NULL; in create_affinity_masks() local
319 masks = kcalloc(nvecs, sizeof(*masks), GFP_KERNEL); in create_affinity_masks()
320 if (!masks) in create_affinity_masks()
325 cpumask_setall(&masks[curvec]); in create_affinity_masks()
333 kfree(masks); in create_affinity_masks()
338 cpumask_copy(&masks[curvec + j], &result[j]); in create_affinity_masks()
351 cpumask_setall(&masks[curvec]); in create_affinity_masks()
353 return masks; in create_affinity_masks()
367 struct cpumask *masks; in virtio_vdpa_find_vqs() local
373 masks = create_affinity_masks(nvqs, desc ? desc : &default_affd); in virtio_vdpa_find_vqs()
[all …]
/drivers/clk/uniphier/
Dclk-uniphier-mux.c17 const unsigned int *masks; member
27 return regmap_write_bits(mux->regmap, mux->reg, mux->masks[index], in uniphier_clk_mux_set_parent()
44 if ((mux->masks[i] & val) == mux->vals[i]) in uniphier_clk_mux_get_parent()
77 mux->masks = data->masks; in uniphier_clk_register_mux()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mpc.c165 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_output_csc()
167 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_output_csc()
223 ocsc_regs.masks.csc_c11 = mpc20->mpc_mask->MPC_OCSC_C11_A; in mpc2_set_ocsc_default()
225 ocsc_regs.masks.csc_c12 = mpc20->mpc_mask->MPC_OCSC_C12_A; in mpc2_set_ocsc_default()
251 reg->masks.exp_region0_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in mpc2_ogam_get_reg_field()
253 reg->masks.exp_region0_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
255 reg->masks.exp_region1_lut_offset = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in mpc2_ogam_get_reg_field()
257 reg->masks.exp_region1_num_segments = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in mpc2_ogam_get_reg_field()
259 reg->masks.field_region_end = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_B; in mpc2_ogam_get_reg_field()
261 reg->masks.field_region_end_slope = mpc20->mpc_mask->MPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in mpc2_ogam_get_reg_field()
[all …]
Ddcn20_dpp_cm.c190 gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11; in program_gamut_remap()
192 gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12; in program_gamut_remap()
285 icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11; in dpp2_program_input_csc()
287 icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12; in dpp2_program_input_csc()
363 reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
365 reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
367 reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
369 reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
372 reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
374 reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
[all …]
/drivers/s390/char/
Dsclp.h98 u8 masks[4 * 1021]; /* variable length */ member
109 static inline sccb_mask_t sccb_get_mask(u8 *masks, size_t len, int i) in sccb_get_mask() argument
113 memcpy(&res, masks + i * len, min(sizeof(res), len)); in sccb_get_mask()
117 static inline void sccb_set_mask(u8 *masks, size_t len, int i, sccb_mask_t val) in sccb_set_mask() argument
119 memset(masks + i * len, 0, len); in sccb_set_mask()
120 memcpy(masks + i * len, &val, min(sizeof(val), len)); in sccb_set_mask()
127 sccb_get_mask(__sccb->masks, __sccb->mask_length, i); \
138 sccb_set_mask(__sccb->masks, __sccb->mask_length, i, val); \
/drivers/pci/msi/
Dmsi.c282 struct irq_affinity_desc *masks) in msi_setup_msi_desc() argument
304 desc.affinity = masks; in msi_setup_msi_desc()
350 struct irq_affinity_desc *masks = NULL; in msi_capability_init() local
366 masks = irq_create_affinity_masks(nvec, affd); in msi_capability_init()
369 ret = msi_setup_msi_desc(dev, nvec, masks); in msi_capability_init()
407 kfree(masks); in msi_capability_init()
614 int nvec, struct irq_affinity_desc *masks) in msix_setup_msi_descs() argument
622 for (i = 0, curmsk = masks; i < nvec; i++, curmsk++) { in msix_setup_msi_descs()
624 desc.affinity = masks ? curmsk : NULL; in msix_setup_msi_descs()
663 struct irq_affinity_desc *masks = NULL; in msix_setup_interrupts() local
[all …]
/drivers/clk/starfive/
Dclk-starfive-jh7110-pll.c103 } masks; member
122 .masks = { \
285 ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd; in jh7110_pll_regvals_get()
286 ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd; in jh7110_pll_regvals_get()
289 ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv; in jh7110_pll_regvals_get()
379 regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd, in jh7110_pll_set_rate()
381 regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd, in jh7110_pll_set_rate()
385 regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv, in jh7110_pll_set_rate()
/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_hubbub.c38 hubbub1->shifts->field_name, hubbub1->masks->field_name
48 hubbub1->shifts->field_name, hubbub1->masks->field_name
79 hubbub3->masks = hubbub_mask; in hubbub301_construct()
/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_hubbub.c41 hubbub1->shifts->field_name, hubbub1->masks->field_name
51 hubbub1->shifts->field_name, hubbub1->masks->field_name
103 hubbub->masks = hubbub_mask; in hubbub201_construct()
/drivers/edac/
Ddmc520_edac.c173 int masks[NUMBER_OF_IRQS]; member
436 mask = pvt->masks[idx]; in dmc520_isr()
477 int masks[NUMBER_OF_IRQS] = { 0 }; in dmc520_edac_probe() local
494 masks[idx] = dmc520_irq_configs[idx].mask; in dmc520_edac_probe()
533 memcpy(pvt->masks, masks, sizeof(masks)); in dmc520_edac_probe()
622 irq_mask_all |= pvt->masks[idx]; in dmc520_edac_remove()
/drivers/char/agp/
Dintel-agp.c461 .masks = intel_generic_masks,
488 .masks = intel_generic_masks,
515 .masks = intel_generic_masks,
542 .masks = intel_generic_masks,
569 .masks = intel_generic_masks,
596 .masks = intel_generic_masks,
623 .masks = intel_generic_masks,
650 .masks = intel_generic_masks,
677 .masks = intel_generic_masks,
/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
Dhw_factory_dcn10.c157 generic->masks = &generic_mask[en]; in define_generic_registers()
182 ddc->masks = &ddc_mask; in define_ddc_registers()
192 hpd->masks = &hpd_mask; in define_hpd_registers()

123456