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Searched refs:match_value (Results 1 – 25 of 38) sorted by relevance

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/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_dpipe.c125 struct devlink_dpipe_value *match_value, in mlxsw_sp_erif_entry_prepare() argument
130 entry->match_values = match_value; in mlxsw_sp_erif_entry_prepare()
136 match_value->match = match; in mlxsw_sp_erif_entry_prepare()
137 match_value->value_size = sizeof(u32); in mlxsw_sp_erif_entry_prepare()
138 match_value->value = kmalloc(match_value->value_size, GFP_KERNEL); in mlxsw_sp_erif_entry_prepare()
139 if (!match_value->value) in mlxsw_sp_erif_entry_prepare()
150 kfree(match_value->value); in mlxsw_sp_erif_entry_prepare()
195 struct devlink_dpipe_value match_value, action_value; in mlxsw_sp_dpipe_table_erif_entries_dump() local
204 memset(&match_value, 0, sizeof(match_value)); in mlxsw_sp_dpipe_table_erif_entries_dump()
208 err = mlxsw_sp_erif_entry_prepare(&entry, &match_value, &match, in mlxsw_sp_dpipe_table_erif_entries_dump()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
Dfs_tcp.c32 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_TCP); in accel_fs_tcp_set_ipv4_flow()
34 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, 4); in accel_fs_tcp_set_ipv4_flow()
35 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv4_flow()
38 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv4_flow()
51 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_TCP); in accel_fs_tcp_set_ipv6_flow()
53 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, 6); in accel_fs_tcp_set_ipv6_flow()
54 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv6_flow()
57 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in accel_fs_tcp_set_ipv6_flow()
126 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_dport, in mlx5e_accel_fs_add_sk()
128 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_sport, in mlx5e_accel_fs_add_sk()
Dipsec_fs.c238 MLX5_SET(fte_match_param, spec->match_value, in ipsec_rx_status_pass_create()
924 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, 4); in setup_fte_addr4()
927 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_addr4()
934 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_addr4()
950 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, 6); in setup_fte_addr6()
953 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_addr6()
960 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in setup_fte_addr6()
973 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_ESP); in setup_fte_esp()
984 MLX5_SET(fte_match_param, spec->match_value, in setup_fte_spi()
989 MLX5_SET(fte_match_param, spec->match_value, in setup_fte_spi()
[all …]
/drivers/pwm/
Dpwm-omap-dmtimer.c157 u32 load_value, match_value; in pwm_omap_dmtimer_config() local
229 match_value = load_value + duty_cycles - 1; in pwm_omap_dmtimer_config()
232 omap->pdata->set_match(omap->dm_timer, true, match_value); in pwm_omap_dmtimer_config()
235 load_value, load_value, match_value, match_value); in pwm_omap_dmtimer_config()
/drivers/net/ethernet/mellanox/mlx5/core/
Den_arfs.c534 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, in arfs_add_rule()
550 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_dport, in arfs_add_rule()
552 MLX5_SET(fte_match_param, spec->match_value, outer_headers.tcp_sport, in arfs_add_rule()
559 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_dport, in arfs_add_rule()
561 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_sport, in arfs_add_rule()
565 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
569 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
578 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
582 memcpy(MLX5_ADDR_OF(fte_match_param, spec->match_value, in arfs_add_rule()
Den_fs.c248 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 1); in __mlx5e_add_vlan_rule()
254 MLX5_SET(fte_match_param, spec->match_value, outer_headers.svlan_tag, 1); in __mlx5e_add_vlan_rule()
260 MLX5_SET(fte_match_param, spec->match_value, outer_headers.svlan_tag, 1); in __mlx5e_add_vlan_rule()
263 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, in __mlx5e_add_vlan_rule()
270 MLX5_SET(fte_match_param, spec->match_value, outer_headers.cvlan_tag, 1); in __mlx5e_add_vlan_rule()
273 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, in __mlx5e_add_vlan_rule()
974 mv_dmac = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5e_add_l2_flow_rule()
Deswitch_offloads.c109 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_clear_rule_source_port()
146 misc2 = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_set_rule_source_port()
155 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5_eswitch_set_rule_source_port()
946 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5_eswitch_add_send_to_vport_rule()
958 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_2); in mlx5_eswitch_add_send_to_vport_rule()
968 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5_eswitch_add_send_to_vport_rule()
1045 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_1, in mlx5_eswitch_add_send_to_vport_meta_rule()
1052 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_eswitch_add_send_to_vport_meta_rule()
1132 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in peer_miss_rules_setup()
1161 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in esw_set_peer_miss_rule_source_port()
[all …]
Den_tc.c189 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval; in mlx5e_tc_match_to_reg_match()
236 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval; in mlx5e_tc_match_to_reg_get_match()
1017 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); in mlx5e_hairpin_get_prio()
1922 spec->match_value, in mlx5_flow_has_geneve_opt()
2274 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); in mlx5e_tc_get_ip_version()
2276 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers); in mlx5e_tc_get_ip_version()
2484 return MLX5_ADDR_OF(fte_match_param, spec->match_value, in get_match_inner_headers_value()
2496 return MLX5_ADDR_OF(fte_match_param, spec->match_value, in get_match_outer_headers_value()
2581 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in __parse_cls_flower()
2585 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in __parse_cls_flower()
[all …]
Deswitch_offloads_termtbl.c208 port_value = MLX5_GET(fte_match_param, spec->match_value, in mlx5_eswitch_offload_is_uplink_port()
/drivers/net/ethernet/mellanox/mlx5/core/esw/
Dbridge_mcast.c88 dmac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, outer_headers.dmac_47_16); in mlx5_esw_bridge_mdb_flow_create()
97 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_mdb_flow_create()
102 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_mdb_flow_create()
107 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_mdb_flow_create()
527 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_esw_bridge_mcast_flow_with_esw_create()
600 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_mcast_vlan_flow_create()
605 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_mcast_vlan_flow_create()
609 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, vlan->vid); in mlx5_esw_bridge_mcast_vlan_flow_create()
900 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.ip_version, 4); in mlx5_esw_bridge_ingress_igmp_fh_create()
902 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.ip_protocol, IPPROTO_IGMP); in mlx5_esw_bridge_ingress_igmp_fh_create()
[all …]
Dbridge.c593 smac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_flow_with_esw_create()
602 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_esw_bridge_ingress_flow_with_esw_create()
614 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_flow_with_esw_create()
619 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_flow_with_esw_create()
624 MLX5_SET(fte_match_param, rule_spec->match_value, outer_headers.first_vid, in mlx5_esw_bridge_ingress_flow_with_esw_create()
705 smac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_filter_flow_create()
714 MLX5_SET(fte_match_param, rule_spec->match_value, misc_parameters_2.metadata_reg_c_0, in mlx5_esw_bridge_ingress_filter_flow_create()
720 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_filter_flow_create()
725 MLX5_SET_TO_ONES(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_ingress_filter_flow_create()
762 dmac_v = MLX5_ADDR_OF(fte_match_param, rule_spec->match_value, in mlx5_esw_bridge_egress_flow_create()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dmacsec_fs.c450 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, ETH_P_PAE); in macsec_fs_tx_create()
516 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_4, 0); in macsec_fs_tx_create()
599 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_a, in macsec_fs_tx_setup_fte()
1174 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.macsec_syndrome, 0); in macsec_fs_rx_create_check_decap_rule()
1177 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_2.metadata_reg_c_4, 0); in macsec_fs_rx_create_check_decap_rule()
1185 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_5.macsec_tag_0, in macsec_fs_rx_create_check_decap_rule()
1340 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_UDP); in macsec_fs_rx_roce_jump_to_rdma_rules_create()
1342 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_dport, ROCE_V2_UDP_DPORT); in macsec_fs_rx_roce_jump_to_rdma_rules_create()
1693 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, ETH_P_MACSEC); in macsec_fs_rx_setup_fte()
1700 MLX5_SET(fte_match_param, spec->match_value, misc_parameters_5.macsec_tag_0, in macsec_fs_rx_setup_fte()
[all …]
Dfs_ttc.c211 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, proto); in mlx5_generate_ttc_rule()
218 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, ipv); in mlx5_generate_ttc_rule()
222 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, etype); in mlx5_generate_ttc_rule()
377 MLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_version, ipv); in mlx5_generate_inner_ttc_rule()
383 MLX5_SET(fte_match_param, spec->match_value, inner_headers.ip_protocol, proto); in mlx5_generate_inner_ttc_rule()
Dsmfs.c57 value.match_buf = (u64 *)spec->match_value; in mlx5_smfs_rule_create()
Dipsec_fs_roce.c41 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_UDP); in ipsec_fs_roce_setup_udp_dport()
43 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_dport, dport); in ipsec_fs_roce_setup_udp_dport()
/drivers/net/ethernet/mellanox/mlx5/core/en/
Dtc_tun_geneve.c133 misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_geneve_vni()
170 misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_geneve_options()
172 misc_3_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_3); in mlx5e_tc_tun_parse_geneve_options()
292 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_geneve_params()
Dfs_tt_redirect.c68 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_protocol, IPPROTO_UDP); in fs_udp_set_dport_flow()
70 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, in fs_udp_set_dport_flow()
73 MLX5_SET(fte_match_param, spec->match_value, outer_headers.udp_dport, udp_dport); in fs_udp_set_dport_flow()
360 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ethertype, ether_type); in fs_any_set_ethertype_flow()
Dtc_tun_vxlan.c148 misc5_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters_5); in mlx5e_tc_tun_parse_vxlan_gbp_option()
169 misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_vxlan()
Dtc_tun_gre.c62 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, misc_parameters); in mlx5e_tc_tun_parse_gretap()
Dtc_tun_mplsoudp.c84 misc2_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in parse_tunnel()
/drivers/clocksource/
Dsh_cmt.c101 u32 match_value; member
458 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
476 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
487 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
542 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
570 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
657 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
934 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
Dhelper.c66 MLX5_SET_TO_ONES(fte_match_param, spec->match_value, outer_headers.cvlan_tag); in esw_egress_acl_vlan_create()
68 MLX5_SET(fte_match_param, spec->match_value, outer_headers.first_vid, vlan_id); in esw_egress_acl_vlan_create()
/drivers/net/ethernet/mellanox/mlx5/core/en/tc/
Dct_fs_smfs.c326 tcp = MLX5_GET(fte_match_param, spec->match_value, in mlx5_ct_fs_smfs_ct_rule_add()
328 gre = MLX5_GET(fte_match_param, spec->match_value, in mlx5_ct_fs_smfs_ct_rule_add()
/drivers/infiniband/hw/mlx5/
Dfs.c191 u32 *match_v = spec->match_value; in parse_flow_attr()
820 MLX5_SET(fte_match_param, &spec->match_value, in set_vhca_port_spec()
839 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_ecn, in set_ecn_ce_spec()
843 MLX5_SET(fte_match_param, spec->match_value, outer_headers.ip_version, in set_ecn_ce_spec()
861 MLX5_SET(fte_match_param, spec->match_value, misc_parameters.bth_opcode, in set_cnp_spec()
992 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, in set_underlay_qp()
1013 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5_ib_set_rule_source_port()
1025 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value, in mlx5_ib_set_rule_source_port()
1537 memcpy(spec->match_value, cmd_in, inlen); in _create_raw_flow_rule()
/drivers/pci/
Dpci-acpi.c423 u32 match_value; member
541 if ((match_reg & reg->match_mask_and) != reg->match_value) in program_hpx_type3_register()
582 hpx3_reg->match_value = reg_fields[10].integer.value; in parse_hpx3_register()

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