Searched refs:mbox0_ok (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/nouveau/nvkm/falcon/ |
| D | ga102.c | 107 ga102_flcn_fw_boot(struct nvkm_falcon_fw *fw, u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr) in ga102_flcn_fw_boot() argument
116 return gm200_flcn_fw_boot(fw, mbox0, mbox1, mbox0_ok, irqsclr); in ga102_flcn_fw_boot()
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| D | gm200.c | 218 gm200_flcn_fw_boot(struct nvkm_falcon_fw *fw, u32 *pmbox0, u32 *pmbox1, u32 mbox0_ok, u32 irqsclr) in gm200_flcn_fw_boot() argument
239 if (FLCN_ERRON(falcon, ret || mbox0 != mbox0_ok, "mbox %08x %08x", mbox0, mbox1)) in gm200_flcn_fw_boot()
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| D | fw.c | 75 bool release, u32 *pmbox0, u32 *pmbox1, u32 mbox0_ok, u32 irqsclr) in nvkm_falcon_fw_boot() argument
113 ret = fw->func->boot(fw, pmbox0, pmbox1, mbox0_ok, irqsclr); in nvkm_falcon_fw_boot()
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| /drivers/gpu/drm/nouveau/include/nvkm/core/ |
| D | falcon.h | 94 u32 *mbox0, u32 *mbox1, u32 mbox0_ok, u32 irqsclr);
147 bool release, u32 *pmbox0, u32 *pmbox1, u32 mbox0_ok, u32 irqsclr);
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