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Searched refs:mg_clktop2_hsclkctl (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h215 u32 mg_clktop2_hsclkctl; member
Dintel_dpll_mgr.c2836 state->mg_clktop2_hsclkctl = in icl_mg_pll_find_divisors()
3090 switch (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3105 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); in icl_ddi_mg_pll_get_freq()
3109 div2 = (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3426 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3428 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3489 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3491 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3675 hw_state->mg_clktop2_hsclkctl); in icl_mg_pll_write()
3721 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
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Dintel_display_debugfs.c675 pll->state.hw_state.mg_clktop2_hsclkctl); in i915_shared_dplls_info()
Dintel_display.c5340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); in intel_pipe_config_compare()