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Searched refs:mg_pll_div0 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.c2961 pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) | in icl_calc_mg_pll_state()
2968 pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val); in icl_calc_mg_pll_state()
2987 pll_state->mg_pll_div0 = in icl_calc_mg_pll_state()
3066 m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; in icl_ddi_mg_pll_get_freq()
3068 m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3079 m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; in icl_ddi_mg_pll_get_freq()
3081 if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { in icl_ddi_mg_pll_get_freq()
3082 m2_frac = pll_state->mg_pll_div0 & in icl_ddi_mg_pll_get_freq()
3434 hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); in mg_pll_get_hw_state()
3502 hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port)); in dkl_pll_get_hw_state()
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Dintel_dpll_mgr.h216 u32 mg_pll_div0; member
Dintel_display_debugfs.c677 pll->state.hw_state.mg_pll_div0); in i915_shared_dplls_info()
Dintel_display.c5341 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); in intel_pipe_config_compare()