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Searched refs:mmMC_SEQ_MISC5 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_6_0_d.h896 #define mmMC_SEQ_MISC5 0x0A95 macro
Dgmc_7_1_d.h796 #define mmMC_SEQ_MISC5 0xa95 macro
Dgmc_8_1_d.h900 #define mmMC_SEQ_MISC5 0xa95 macro
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Diceland_smumgr.c1309 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
1317 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in iceland_populate_single_memory_level()
Dtonga_smumgr.c1049 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in tonga_populate_single_memory_level()
1060 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in tonga_populate_single_memory_level()
Dci_smumgr.c1263 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()
1271 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; in ci_populate_single_memory_level()