Searched refs:mmVM_L2_CNTL3 (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 205 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp); in gfxhub_v1_0_init_cache_regs()
367 WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0); in gfxhub_v1_0_gart_disable()
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| D | mmhub_v1_0.c | 191 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, tmp); in mmhub_v1_0_init_cache_regs()
366 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); in mmhub_v1_0_gart_disable()
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| D | gmc_v6_0.c | 496 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_enable()
597 WREG32(mmVM_L2_CNTL3, in gmc_v6_0_gart_disable()
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| D | gmc_v7_0.c | 641 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v7_0_gart_enable()
645 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v7_0_gart_enable()
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| D | gmc_v8_0.c | 857 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
861 WREG32(mmVM_L2_CNTL3, tmp); in gmc_v8_0_gart_enable()
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| /drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_7_0_d.h | 543 #define mmVM_L2_CNTL3 0x502 macro
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| D | gmc_8_2_d.h | 601 #define mmVM_L2_CNTL3 0x502 macro
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| D | gmc_6_0_d.h | 1259 #define mmVM_L2_CNTL3 0x0502 macro
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| D | gmc_7_1_d.h | 576 #define mmVM_L2_CNTL3 0x502 macro
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| D | gmc_8_1_d.h | 599 #define mmVM_L2_CNTL3 0x502 macro
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| /drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| D | mmhub_9_1_offset.h | 1300 #define mmVM_L2_CNTL3 … macro
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| D | mmhub_9_3_0_offset.h | 1284 #define mmVM_L2_CNTL3 … macro
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| D | mmhub_1_0_offset.h | 1268 #define mmVM_L2_CNTL3 … macro
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| /drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_9_0_offset.h | 1169 #define mmVM_L2_CNTL3 … macro
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| D | gc_9_2_1_offset.h | 1133 #define mmVM_L2_CNTL3 … macro
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| D | gc_9_1_offset.h | 1195 #define mmVM_L2_CNTL3 … macro
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