| /drivers/video/fbdev/i810/ |
| D | i810_main.c | 168 static void i810_screen_off(u8 __iomem *mmio, u8 mode) in i810_screen_off() argument
173 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
174 val = i810_readb(SR_DATA, mmio); in i810_screen_off()
178 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--); in i810_screen_off()
179 i810_writeb(SR_INDEX, mmio, SR01); in i810_screen_off()
180 i810_writeb(SR_DATA, mmio, val); in i810_screen_off()
192 static void i810_dram_off(u8 __iomem *mmio, u8 mode) in i810_dram_off() argument
196 val = i810_readb(DRAMCH, mmio); in i810_dram_off()
199 i810_writeb(DRAMCH, mmio, val); in i810_dram_off()
211 static void i810_protect_regs(u8 __iomem *mmio, int mode) in i810_protect_regs() argument
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| D | i810_accel.c | 36 static inline void i810_report_error(u8 __iomem *mmio) in i810_report_error() argument
43 i810_readw(IIR, mmio), in i810_report_error()
44 i810_readb(EIR, mmio), in i810_report_error()
45 i810_readl(PGTBL_ER, mmio), in i810_report_error()
46 i810_readl(IPEIR, mmio), in i810_report_error()
47 i810_readl(IPEHR, mmio)); in i810_report_error()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space() local
67 head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK; in wait_for_space()
76 i810_report_error(mmio); in wait_for_space()
93 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_engine_idle() local
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| D | i810-i2c.c | 46 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setscl() local
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
59 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_setsda() local
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
72 u8 __iomem *mmio = par->mmio_start_virtual; in i810i2c_getscl() local
74 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK); in i810i2c_getscl()
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| /drivers/net/ethernet/amd/ |
| D | amd8111e.c | 101 void __iomem *mmio = lp->mmio; in amd8111e_read_phy() local
105 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
107 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
110 ((reg & 0x1f) << 16), mmio + PHY_ACCESS); in amd8111e_read_phy()
112 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_read_phy()
131 void __iomem *mmio = lp->mmio; in amd8111e_write_phy() local
134 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
136 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
139 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); in amd8111e_write_phy()
142 reg_val = readl(mmio + PHY_ACCESS); in amd8111e_write_phy()
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| /drivers/phy/mediatek/ |
| D | phy-mtk-ufs.c | 41 void __iomem *mmio; member
62 void __iomem *mmio = phy->mmio; in ufs_mtk_phy_set_active() local
65 mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON); in ufs_mtk_phy_set_active()
66 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON); in ufs_mtk_phy_set_active()
69 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN); in ufs_mtk_phy_set_active()
70 mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN); in ufs_mtk_phy_set_active()
73 mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON); in ufs_mtk_phy_set_active()
74 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON); in ufs_mtk_phy_set_active()
77 mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN); in ufs_mtk_phy_set_active()
78 mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN); in ufs_mtk_phy_set_active()
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| /drivers/comedi/drivers/ |
| D | ni_pcidio.c | 311 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_request_di_mite_channel()
327 dev->mmio + DMA_LINE_CONTROL_GROUP1); in ni_pcidio_release_di_mite_channel()
393 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS); in nidio_interrupt()
394 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
408 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL); in nidio_interrupt()
420 writeb(0x00, dev->mmio + in nidio_interrupt()
425 auxdata = readl(dev->mmio + GROUP_1_FIFO); in nidio_interrupt()
427 flags = readb(dev->mmio + GROUP_1_FLAGS); in nidio_interrupt()
432 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR); in nidio_interrupt()
435 writeb(0x00, dev->mmio + OP_MODE); in nidio_interrupt()
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| D | rtd520.c | 464 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list()
465 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
468 dev->mmio + LAS0_CGT_WRITE); in rtd_load_channelgain_list()
471 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list()
473 dev->mmio + LAS0_CGL_WRITE); in rtd_load_channelgain_list()
488 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
491 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth()
496 writew(0, dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
498 fifo_status = readl(dev->mmio + LAS0_ADC); in rtd520_probe_fifo_depth()
508 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth()
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| D | ni_6527.c | 89 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0)); in ni6527_set_filter_interval()
91 dev->mmio + NI6527_FILT_INTERVAL_REG(1)); in ni6527_set_filter_interval()
93 dev->mmio + NI6527_FILT_INTERVAL_REG(2)); in ni6527_set_filter_interval()
95 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG); in ni6527_set_filter_interval()
104 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0)); in ni6527_set_filter_enable()
105 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1)); in ni6527_set_filter_enable()
106 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2)); in ni6527_set_filter_enable()
150 val = readb(dev->mmio + NI6527_DI_REG(0)); in ni6527_di_insn_bits()
151 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8); in ni6527_di_insn_bits()
152 val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16); in ni6527_di_insn_bits()
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| D | dt3000.c | 231 writew(cmd, dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
234 status = readw(dev->mmio + DPR_CMD_MBX); in dt3k_send_cmd()
250 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_readsingle()
252 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_readsingle()
253 writew(gain, dev->mmio + DPR_PARAMS(1)); in dt3k_readsingle()
257 return readw(dev->mmio + DPR_PARAMS(2)); in dt3k_readsingle()
263 writew(subsys, dev->mmio + DPR_SUBSYS); in dt3k_writesingle()
265 writew(chan, dev->mmio + DPR_PARAMS(0)); in dt3k_writesingle()
266 writew(0, dev->mmio + DPR_PARAMS(1)); in dt3k_writesingle()
267 writew(data, dev->mmio + DPR_PARAMS(2)); in dt3k_writesingle()
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| D | me_daq.c | 176 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_dio_insn_config()
186 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A_REG; in me_dio_insn_bits()
187 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B_REG; in me_dio_insn_bits()
221 status = readw(dev->mmio + ME_STATUS_REG); in me_ai_eoc()
251 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
253 writew(0x00, dev->mmio + ME_STATUS_REG); /* clear interrupts */ in me_ai_insn_read()
257 writew(devpriv->ctrl2, dev->mmio + ME_CTRL2_REG); in me_ai_insn_read()
265 writew(val, dev->mmio + ME_AI_FIFO_REG); in me_ai_insn_read()
269 writew(devpriv->ctrl1, dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
273 readw(dev->mmio + ME_CTRL1_REG); in me_ai_insn_read()
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| D | daqboard2000.c | 261 writew(entry & 0x00ff, dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO); in db2k_write_acq_scan_list_entry()
263 dev->mmio + DB2K_REG_ACQ_SCAN_LIST_FIFO); in db2k_write_acq_scan_list_entry()
311 status = readw(dev->mmio + DB2K_REG_ACQ_STATUS); in db2k_ai_status()
328 dev->mmio + DB2K_REG_ACQ_CONTROL); in db2k_ai_insn_read()
335 writel(1000000, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_LOW); in db2k_ai_insn_read()
336 writew(0, dev->mmio + DB2K_REG_ACQ_PACER_CLOCK_DIV_HIGH); in db2k_ai_insn_read()
351 dev->mmio + DB2K_REG_ACQ_CONTROL); in db2k_ai_insn_read()
359 dev->mmio + DB2K_REG_ACQ_CONTROL); in db2k_ai_insn_read()
372 data[i] = readw(dev->mmio + DB2K_REG_ACQ_RESULTS_FIFO); in db2k_ai_insn_read()
374 dev->mmio + DB2K_REG_ACQ_CONTROL); in db2k_ai_insn_read()
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| D | s626.c | 110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
167 if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S)) in s626_debi_transfer()
181 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_read()
186 return readl(dev->mmio + S626_P_DEBIAD); in s626_debi_read()
196 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_write()
197 writel(wdata, dev->mmio + S626_P_DEBIAD); in s626_debi_write()
214 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
217 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace()
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| D | icp_multi.c | 94 status = readw(dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_eoc()
120 writew(adc_csr, dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
125 dev->mmio + ICP_MULTI_ADC_CSR); in icp_multi_ai_insn_read()
134 data[n] = (readw(dev->mmio + ICP_MULTI_AI) >> 4) & 0x0fff; in icp_multi_ai_insn_read()
147 status = readw(dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_ready()
166 writew(dac_csr, dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
177 writew(val, dev->mmio + ICP_MULTI_AO); in icp_multi_ao_insn_write()
181 dev->mmio + ICP_MULTI_DAC_CSR); in icp_multi_ao_insn_write()
194 data[1] = readw(dev->mmio + ICP_MULTI_DI); in icp_multi_di_insn_bits()
205 writew(s->state, dev->mmio + ICP_MULTI_DO); in icp_multi_do_insn_bits()
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| /drivers/ata/ |
| D | sata_sx4.c | 419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_dma_prep() local
428 mmio += PDC_CHIP0_OFS; in pdc20621_dma_prep()
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep()
478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; in pdc20621_nodata_prep() local
484 mmio += PDC_CHIP0_OFS; in pdc20621_nodata_prep()
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep()
529 void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; in __pdc20621_push_hdma() local
532 mmio += PDC_CHIP0_OFS; in __pdc20621_push_hdma()
534 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in __pdc20621_push_hdma()
535 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */ in __pdc20621_push_hdma()
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| D | ahci_imx.c | 117 static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) in imx_phy_crbit_assert() argument
124 crval = readl(mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
129 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_crbit_assert()
133 srval = readl(mmio + IMX_P0PHYSR); in imx_phy_crbit_assert()
142 static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) in imx_phy_reg_addressing() argument
148 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_addressing()
151 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); in imx_phy_reg_addressing()
156 ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); in imx_phy_reg_addressing()
163 static int imx_phy_reg_write(u16 val, void __iomem *mmio) in imx_phy_reg_write() argument
169 writel(crval, mmio + IMX_P0PHYCR); in imx_phy_reg_write()
[all …]
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| D | sata_nv.c | 599 void __iomem *mmio = pp->ctl_block; in nv_adma_register_mode() local
606 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
609 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
616 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_register_mode()
617 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); in nv_adma_register_mode()
620 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
623 status = readw(mmio + NV_ADMA_STAT); in nv_adma_register_mode()
637 void __iomem *mmio = pp->ctl_block; in nv_adma_mode() local
646 tmp = readw(mmio + NV_ADMA_CTL); in nv_adma_mode()
647 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL); in nv_adma_mode()
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| /drivers/gpu/drm/i915/gvt/ |
| D | mmio_context.c | 206 struct engine_mmio *mmio; in restore_context_mmio_for_inhibit() local
223 for (mmio = gvt->engine_mmio_list.mmio; in restore_context_mmio_for_inhibit()
224 i915_mmio_reg_valid(mmio->reg); mmio++) { in restore_context_mmio_for_inhibit()
225 if (mmio->id != ring_id || !mmio->in_context) in restore_context_mmio_for_inhibit()
228 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
229 *cs++ = vgpu_vreg_t(vgpu, mmio->reg) | (mmio->mask << 16); in restore_context_mmio_for_inhibit()
479 struct engine_mmio *mmio; in switch_mmio() local
485 for (mmio = engine->i915->gvt->engine_mmio_list.mmio; in switch_mmio()
486 i915_mmio_reg_valid(mmio->reg); mmio++) { in switch_mmio()
487 if (mmio->id != engine->id) in switch_mmio()
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| /drivers/phy/qualcomm/ |
| D | phy-qcom-ipq806x-sata.c | 19 void __iomem *mmio; member
59 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
61 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
63 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
68 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM0); in qcom_ipq806x_sata_phy_init()
70 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
77 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM1); in qcom_ipq806x_sata_phy_init()
79 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
82 writel_relaxed(reg, phy->mmio + SATA_PHY_P0_PARAM2); in qcom_ipq806x_sata_phy_init()
85 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
[all …]
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| /drivers/ntb/hw/amd/ |
| D | ntb_hw_amd.c | 125 void __iomem *mmio, *peer_mmio; in amd_ntb_mw_set_trans() local
142 mmio = ndev->self_mmio; in amd_ntb_mw_set_trans()
166 write64(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
189 writel(base_addr, mmio + limit_reg); in amd_ntb_mw_set_trans()
346 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_enable() local
350 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_enable()
362 void __iomem *mmio = ndev->self_mmio; in amd_ntb_link_disable() local
366 writel(ndev->int_mask, mmio + AMD_INTMASK_OFFSET); in amd_ntb_link_disable()
423 void __iomem *mmio = ndev->self_mmio; in amd_ntb_db_read() local
425 return (u64)readw(mmio + AMD_DBSTAT_OFFSET); in amd_ntb_db_read()
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| /drivers/ntb/hw/intel/ |
| D | ntb_hw_gen3.c | 147 void __iomem *mmio; in gen3_setup_b2b_mw() local
151 mmio = ndev->self_mmio; in gen3_setup_b2b_mw()
155 iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
156 bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET); in gen3_setup_b2b_mw()
160 iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
161 bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET); in gen3_setup_b2b_mw()
165 iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET); in gen3_setup_b2b_mw()
166 iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET); in gen3_setup_b2b_mw()
259 void __iomem *mmio; in ndev_ntb3_debugfs_read() local
266 mmio = ndev->self_mmio; in ndev_ntb3_debugfs_read()
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| D | ntb_hw_gen1.c | 203 void __iomem *mmio) in ndev_db_read() argument
208 return ndev->reg->db_ioread(mmio); in ndev_db_read()
212 void __iomem *mmio) in ndev_db_write() argument
220 ndev->reg->db_iowrite(db_bits, mmio); in ndev_db_write()
226 void __iomem *mmio) in ndev_db_set_mask() argument
239 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_set_mask()
247 void __iomem *mmio) in ndev_db_clear_mask() argument
260 ndev->reg->db_iowrite(ndev->db_mask, mmio); in ndev_db_clear_mask()
297 void __iomem *mmio) in ndev_spad_read() argument
305 return ioread32(mmio + (idx << 2)); in ndev_spad_read()
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| /drivers/net/wireless/mediatek/mt76/ |
| D | mmio.c | 13 val = readl(dev->mmio.regs + offset); in mt76_mmio_rr()
22 writel(val, dev->mmio.regs + offset); in mt76_mmio_wr()
35 __iowrite32_copy(dev->mmio.regs + offset, data, DIV_ROUND_UP(len, 4)); in mt76_mmio_write_copy()
41 __ioread32_copy(data, dev->mmio.regs + offset, DIV_ROUND_UP(len, 4)); in mt76_mmio_read_copy()
73 spin_lock_irqsave(&dev->mmio.irq_lock, flags); in mt76_set_irq_mask()
74 dev->mmio.irqmask &= ~clear; in mt76_set_irq_mask()
75 dev->mmio.irqmask |= set; in mt76_set_irq_mask()
77 if (mtk_wed_device_active(&dev->mmio.wed)) in mt76_set_irq_mask()
78 mtk_wed_device_irq_set_mask(&dev->mmio.wed, in mt76_set_irq_mask()
79 dev->mmio.irqmask); in mt76_set_irq_mask()
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| /drivers/mtd/nand/raw/ |
| D | cs553x_nand.c | 94 void __iomem *mmio; member
108 writeb(ctl, cs553x->mmio + MM_NAND_CTL); in cs553x_write_ctrl_byte()
109 writeb(data, cs553x->mmio + MM_NAND_IO); in cs553x_write_ctrl_byte()
110 return readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status, in cs553x_write_ctrl_byte()
118 writeb(0, cs553x->mmio + MM_NAND_CTL); in cs553x_data_in()
120 memcpy_fromio(buf, cs553x->mmio, 0x800); in cs553x_data_in()
124 memcpy_fromio(buf, cs553x->mmio, len); in cs553x_data_in()
130 writeb(0, cs553x->mmio + MM_NAND_CTL); in cs553x_data_out()
132 memcpy_toio(cs553x->mmio, buf, 0x800); in cs553x_data_out()
136 memcpy_toio(cs553x->mmio, buf, len); in cs553x_data_out()
[all …]
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| /drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 121 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); in hibmc_plane_atomic_update()
128 priv->mmio + HIBMC_CRT_FB_WIDTH); in hibmc_plane_atomic_update()
131 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
135 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
165 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
171 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
183 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_enable()
205 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_disable()
259 val = readl(priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
261 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
[all …]
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| /drivers/ssb/ |
| D | scan.c | 177 lo = readw(bus->mmio + offset); in scan_read32()
178 hi = readw(bus->mmio + offset + 2); in scan_read32()
184 return readl(bus->mmio + offset); in scan_read32()
207 iounmap(bus->mmio); in ssb_iounmap()
211 pci_iounmap(bus->host_pci, bus->mmio); in ssb_iounmap()
219 bus->mmio = NULL; in ssb_iounmap()
226 void __iomem *mmio = NULL; in ssb_ioremap() local
233 mmio = ioremap(baseaddr, SSB_CORE_SIZE); in ssb_ioremap()
237 mmio = pci_iomap(bus->host_pci, 0, ~0UL); in ssb_ioremap()
244 mmio = (void __iomem *)baseaddr; in ssb_ioremap()
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