| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_mpc.c | 352 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc1_init_mpcc() argument
354 mpcc->mpcc_id = mpcc_inst; in mpc1_init_mpcc()
460 int mpcc_inst, in mpc1_read_mpcc_state() argument
465 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id); in mpc1_read_mpcc_state()
466 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id); in mpc1_read_mpcc_state()
467 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id); in mpc1_read_mpcc_state()
468 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode, in mpc1_read_mpcc_state()
472 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle, in mpc1_read_mpcc_state()
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| D | dcn10_hw_sequencer.c | 1202 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_plane_atomic_disconnect()
1407 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn10_init_pipes()
1414 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn10_init_pipes()
3255 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) in get_hubp_by_inst() argument
3260 if (res_pool->hubps[i]->inst == mpcc_inst) in get_hubp_by_inst()
3273 int mpcc_inst; in dcn10_wait_for_mpcc_disconnect() local
3282 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) { in dcn10_wait_for_mpcc_disconnect()
3283 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { in dcn10_wait_for_mpcc_disconnect()
3284 struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
3288 res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); in dcn10_wait_for_mpcc_disconnect()
[all …]
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| D | dcn10_mpc.h | 198 int mpcc_inst,
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| D | dcn10_resource.c | 1112 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn10_acquire_free_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_mpc.c | 62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc201_init_mpcc() argument
64 mpcc->mpcc_id = mpcc_inst; in mpc201_init_mpcc()
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| D | dcn201_hwseq.c | 312 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn201_init_hw()
320 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_init_hw()
407 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn201_plane_atomic_disconnect()
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| D | dcn201_resource.c | 1018 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn201_acquire_free_pipe_for_layer()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hwseq.c | 231 ASSERT(wb_info->mpcc_inst >= 0); in dcn30_set_writeback()
232 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
238 wb_info->dwb_pipe_inst, wb_info->mpcc_inst); in dcn30_set_writeback()
253 wb_info->mpcc_inst); in dcn30_update_writeback()
332 wb_info->mpcc_inst); in dcn30_enable_writeback()
392 wb_info.mpcc_inst = -1; in dcn30_program_all_writeback_pipes_in_tree()
400 wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dcn30_program_all_writeback_pipes_in_tree()
405 if (wb_info.mpcc_inst == -1) { in dcn30_program_all_writeback_pipes_in_tree()
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| D | dcn30_mpc.c | 1038 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc3_init_mpcc() argument
1040 mpcc->mpcc_id = mpcc_inst; in mpc3_init_mpcc()
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| D | dcn30_mpc.h | 1089 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
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| D | dcn30_resource.c | 1539 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dmub_psr.c | 343 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst; in dmub_psr_copy_settings()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | mpc.h | 204 int mpcc_inst,
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_mpc.c | 511 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) in mpc2_init_mpcc() argument
513 mpcc->mpcc_id = mpcc_inst; in mpc2_init_mpcc()
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| D | dcn20_resource.c | 1479 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; in dcn20_split_stream_for_odm()
1564 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in dcn20_split_stream_for_mpc()
2172 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; in dcn20_acquire_free_pipe_for_layer()
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| D | dcn20_hwseq.c | 2882 pipe_ctx->plane_res.mpcc_inst = dpp->inst; in dcn20_fpga_init_hw()
2892 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true; in dcn20_fpga_init_hw()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 324 uint8_t mpcc_inst; member
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc_stream.h | 94 int mpcc_inst; member
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| D | dc.h | 1425 int mpcc_inst);
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 1821 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_split_pipe()
2345 pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst; in acquire_first_free_pipe()
2658 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst; in acquire_resource_from_hw_enabled_state()
2663 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s); in acquire_resource_from_hw_enabled_state()
2666 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id = in acquire_resource_from_hw_enabled_state()
2670 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot = in acquire_resource_from_hw_enabled_state()
4282 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dc_resource_acquire_secondary_pipe_for_mpc_odm()
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| D | dc.c | 3487 int mpcc_inst; in wait_for_outstanding_hw_updates() local
3503 mpcc_inst = hubp->inst; in wait_for_outstanding_hw_updates()
3506 if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) { in wait_for_outstanding_hw_updates()
3507 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst); in wait_for_outstanding_hw_updates()
3508 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false; in wait_for_outstanding_hw_updates()
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| /drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_resource.c | 2667 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2699 free_pipe->plane_res.mpcc_inst = in dcn32_acquire_free_pipe_as_secondary_dpp_pipe()
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| /drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 2174 uint8_t mpcc_inst; member
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| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calcs.c | 541 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; in split_stream_across_pipes()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 1593 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn32_split_stream_for_mpc_or_odm()
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