| /drivers/media/pci/solo6x10/ |
| D | solo6x10-regs.h | 34 #define SOLO_DMA_CTRL_REFRESH_CYCLE(n) ((n)<<8) argument
36 #define SOLO_DMA_CTRL_SDRAM_SIZE(n) ((n)<<6) argument
41 #define SOLO_DMA_CTRL_LATENCY(n) ((n)<<0) argument
49 #define SOLO_VCLK_SELECT(n) ((n)<<20) argument
50 #define SOLO_VCLK_VIN1415_DELAY(n) ((n)<<14) argument
51 #define SOLO_VCLK_VIN1213_DELAY(n) ((n)<<12) argument
52 #define SOLO_VCLK_VIN1011_DELAY(n) ((n)<<10) argument
53 #define SOLO_VCLK_VIN0809_DELAY(n) ((n)<<8) argument
54 #define SOLO_VCLK_VIN0607_DELAY(n) ((n)<<6) argument
55 #define SOLO_VCLK_VIN0405_DELAY(n) ((n)<<4) argument
[all …]
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| /drivers/media/common/siano/ |
| D | smsdvb-debugfs.c | 37 int n = 0; in smsdvb_print_dvb_stats() local
48 n += sysfs_emit_at(buf, n, "is_rf_locked = %d\n", p->is_rf_locked); in smsdvb_print_dvb_stats()
49 n += sysfs_emit_at(buf, n, "is_demod_locked = %d\n", p->is_demod_locked); in smsdvb_print_dvb_stats()
50 n += sysfs_emit_at(buf, n, "is_external_lna_on = %d\n", p->is_external_lna_on); in smsdvb_print_dvb_stats()
51 n += sysfs_emit_at(buf, n, "SNR = %d\n", p->SNR); in smsdvb_print_dvb_stats()
52 n += sysfs_emit_at(buf, n, "ber = %d\n", p->ber); in smsdvb_print_dvb_stats()
53 n += sysfs_emit_at(buf, n, "FIB_CRC = %d\n", p->FIB_CRC); in smsdvb_print_dvb_stats()
54 n += sysfs_emit_at(buf, n, "ts_per = %d\n", p->ts_per); in smsdvb_print_dvb_stats()
55 n += sysfs_emit_at(buf, n, "MFER = %d\n", p->MFER); in smsdvb_print_dvb_stats()
56 n += sysfs_emit_at(buf, n, "RSSI = %d\n", p->RSSI); in smsdvb_print_dvb_stats()
[all …]
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| /drivers/media/platform/nxp/imx8-isi/ |
| D | imx8-isi-regs.h | 17 #define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25) argument
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16) argument
24 #define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6) argument
26 #define CHNL_CTRL_SRC_TYPE(n) ((n) << 4) argument
30 #define CHNL_CTRL_SRC_INPUT(n) ((n) << 0) argument
35 #define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24) argument
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16) argument
89 #define CHNL_IMG_CTRL_DEINT(n) ((n) << 12) argument
97 #define CHNL_IMG_CTRL_DEC_X(n) ((n) << 10) argument
99 #define CHNL_IMG_CTRL_DEC_Y(n) ((n) << 8) argument
[all …]
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| /drivers/media/cec/core/ |
| D | cec-notifier.c | 54 struct cec_notifier *n; in cec_notifier_get_conn() local
57 list_for_each_entry(n, &cec_notifiers, head) { in cec_notifier_get_conn()
58 if (n->hdmi_dev == hdmi_dev && in cec_notifier_get_conn()
60 (n->port_name && !strcmp(n->port_name, port_name)))) { in cec_notifier_get_conn()
61 kref_get(&n->kref); in cec_notifier_get_conn()
63 return n; in cec_notifier_get_conn()
66 n = kzalloc(sizeof(*n), GFP_KERNEL); in cec_notifier_get_conn()
67 if (!n) in cec_notifier_get_conn()
69 n->hdmi_dev = hdmi_dev; in cec_notifier_get_conn()
71 n->port_name = kstrdup(port_name, GFP_KERNEL); in cec_notifier_get_conn()
[all …]
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| /drivers/gpu/drm/rockchip/ |
| D | inno_hdmi.h | 48 #define v_VIDEO_INPUT_FORMAT(n) (n << 1) argument
61 #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6) argument
62 #define v_VIDEO_INPUT_BITS(n) (n << 4) argument
63 #define v_VIDEO_INPUT_CSP(n) (n << 0) argument
73 #define v_VIDEO_AUTO_CSC(n) (n << 7) argument
75 #define v_VIDEO_C0_C2_SWAP(n) (n << 0) argument
88 #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4) argument
101 #define v_AVMUTE_CLEAR(n) (n << 7) argument
102 #define v_AVMUTE_ENABLE(n) (n << 6) argument
103 #define v_AUDIO_MUTE(n) (n << 1) argument
[all …]
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| /drivers/gpu/drm/exynos/ |
| D | regs-decon5433.h | 12 #define DECON_WINCONx(n) (0x0020 + ((n) * 4)) argument
13 #define DECON_VIDOSDxH(n) (0x0080 + ((n) * 4)) argument
15 #define DECON_VIDOSDxA(n) (0x00B0 + ((n) * 0x20)) argument
16 #define DECON_VIDOSDxB(n) (0x00B4 + ((n) * 0x20)) argument
17 #define DECON_VIDOSDxC(n) (0x00B8 + ((n) * 0x20)) argument
18 #define DECON_VIDOSDxD(n) (0x00BC + ((n) * 0x20)) argument
19 #define DECON_VIDOSDxE(n) (0x00C0 + ((n) * 0x20)) argument
20 #define DECON_VIDW0xADD0B0(n) (0x0150 + ((n) * 0x10)) argument
21 #define DECON_VIDW0xADD0B1(n) (0x0154 + ((n) * 0x10)) argument
22 #define DECON_VIDW0xADD0B2(n) (0x0158 + ((n) * 0x10)) argument
[all …]
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| /drivers/usb/gadget/udc/ |
| D | fusb300_udc.h | 21 #define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30) argument
22 #define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30) argument
23 #define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30) argument
24 #define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30) argument
25 #define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30) argument
54 #define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10) argument
55 #define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10) argument
56 #define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10) argument
57 #define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10) argument
60 #define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10) argument
[all …]
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| /drivers/net/ethernet/intel/igc/ |
| D | igc_dump.c | 47 int n = 0; in igc_regdump() local
53 for (n = 0; n < 4; n++) in igc_regdump()
54 regs[n] = rd32(IGC_RDLEN(n)); in igc_regdump()
57 for (n = 0; n < 4; n++) in igc_regdump()
58 regs[n] = rd32(IGC_RDH(n)); in igc_regdump()
61 for (n = 0; n < 4; n++) in igc_regdump()
62 regs[n] = rd32(IGC_RDT(n)); in igc_regdump()
65 for (n = 0; n < 4; n++) in igc_regdump()
66 regs[n] = rd32(IGC_RXDCTL(n)); in igc_regdump()
69 for (n = 0; n < 4; n++) in igc_regdump()
[all …]
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| /drivers/clk/at91/ |
| D | sam9x60.c | 76 char *n; member
85 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
86 { .n = "uhpck", .p = "usbck", .id = 6 },
87 { .n = "pck0", .p = "prog0", .id = 8 },
88 { .n = "pck1", .p = "prog1", .id = 9 },
89 { .n = "qspick", .p = "masterck_div", .id = 19 },
93 char *n; member
97 { .n = "pioA_clk", .id = 2, },
98 { .n = "pioB_clk", .id = 3, },
99 { .n = "pioC_clk", .id = 4, },
[all …]
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| D | sama5d4.c | 40 char *n; member
49 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
50 { .n = "lcdck", .p = "masterck_div", .id = 3 },
51 { .n = "smdck", .p = "smdclk", .id = 4 },
52 { .n = "uhpck", .p = "usbck", .id = 6 },
53 { .n = "udpck", .p = "usbck", .id = 7 },
54 { .n = "pck0", .p = "prog0", .id = 8 },
55 { .n = "pck1", .p = "prog1", .id = 9 },
56 { .n = "pck2", .p = "prog2", .id = 10 },
60 char *n; member
[all …]
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| D | at91sam9260.c | 11 char *n; member
17 char *n; member
76 { .n = "uhpck", .p = "usbck", .id = 6 },
77 { .n = "udpck", .p = "usbck", .id = 7 },
78 { .n = "pck0", .p = "prog0", .id = 8 },
79 { .n = "pck1", .p = "prog1", .id = 9 },
83 { .n = "pioA_clk", .id = 2 },
84 { .n = "pioB_clk", .id = 3 },
85 { .n = "pioC_clk", .id = 4 },
86 { .n = "adc_clk", .id = 5 },
[all …]
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| D | sama5d2.c | 41 char *n; member
50 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
51 { .n = "lcdck", .p = "masterck_div", .id = 3 },
52 { .n = "uhpck", .p = "usbck", .id = 6 },
53 { .n = "udpck", .p = "usbck", .id = 7 },
54 { .n = "pck0", .p = "prog0", .id = 8 },
55 { .n = "pck1", .p = "prog1", .id = 9 },
56 { .n = "pck2", .p = "prog2", .id = 10 },
57 { .n = "iscck", .p = "masterck_div", .id = 18 },
61 char *n; member
[all …]
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| D | sama5d3.c | 41 char *n; member
50 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
51 { .n = "lcdck", .p = "masterck_div", .id = 3 },
52 { .n = "smdck", .p = "smdclk", .id = 4 },
53 { .n = "uhpck", .p = "usbck", .id = 6 },
54 { .n = "udpck", .p = "usbck", .id = 7 },
55 { .n = "pck0", .p = "prog0", .id = 8 },
56 { .n = "pck1", .p = "prog1", .id = 9 },
57 { .n = "pck2", .p = "prog2", .id = 10 },
61 char *n; member
[all …]
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| D | sama7g5.c | 159 const char *n; member
171 .n = "cpupll_fracck",
184 .n = "cpupll_divpmcck",
202 .n = "syspll_fracck",
216 .n = "syspll_divpmcck",
232 .n = "ddrpll_fracck",
245 .n = "ddrpll_divpmcck",
257 .n = "imgpll_fracck",
266 .n = "imgpll_divpmcck",
278 .n = "baudpll_fracck",
[all …]
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| /drivers/phy/allwinner/ |
| D | phy-sun6i-mipi-dphy.c | 21 #define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4) argument
36 #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24) argument
37 #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16) argument
38 #define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff) argument
41 #define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24) argument
42 #define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16) argument
43 #define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8) argument
44 #define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff) argument
47 #define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff) argument
52 #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8) argument
[all …]
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| /drivers/usb/dwc3/ |
| D | core.h | 133 #define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) argument
134 #define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) argument
136 #define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) argument
138 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) argument
140 #define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) argument
141 #define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) argument
143 #define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) argument
144 #define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) argument
145 #define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) argument
146 #define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) argument
[all …]
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| /drivers/media/platform/renesas/vsp1/ |
| D | vsp1_regs.h | 17 #define VI6_CMD(n) (0x0000 + (n) * 4) argument
28 #define VI6_SRESET_SRTS(n) BIT(n) argument
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28) argument
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8) argument
34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) argument
39 #define VI6_WPF_IRQ_STA(n) (0x004c + (n) * 12) argument
44 #define VI6_DISP_IRQ_ENB(n) (0x0078 + (n) * 60) argument
47 #define VI6_DISP_IRQ_ENB_LNEE(n) BIT(n) argument
49 #define VI6_DISP_IRQ_STA(n) (0x007c + (n) * 60) argument
52 #define VI6_DISP_IRQ_STA_LNE(n) BIT(n) argument
[all …]
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| /drivers/gpu/drm/renesas/rcar-du/ |
| D | rcar_du_regs.h | 72 #define DSSR_DFB(n) (1 << ((n)+15)) argument
78 #define DSSR_ADC(n) (1 << ((n)-1)) argument
86 #define DSRCR_ADCL(n) (1 << ((n)-1)) argument
95 #define DIER_ADCE(n) (1 << ((n)-1)) argument
104 #define DPPR_DPE(n) (1 << ((n)*4-1)) argument
105 #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) argument
106 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) argument
154 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) argument
155 #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) argument
156 #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) argument
[all …]
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | dispc.h | 37 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
38 DISPC_BA0_OFFSET(n))
39 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
40 DISPC_BA1_OFFSET(n))
41 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
42 DISPC_BA0_UV_OFFSET(n))
43 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
44 DISPC_BA1_UV_OFFSET(n))
45 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
46 DISPC_POS_OFFSET(n))
[all …]
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | dispc.h | 34 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \ argument
35 DISPC_BA0_OFFSET(n))
36 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \ argument
37 DISPC_BA1_OFFSET(n))
38 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \ argument
39 DISPC_BA0_UV_OFFSET(n))
40 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \ argument
41 DISPC_BA1_UV_OFFSET(n))
42 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \ argument
43 DISPC_POS_OFFSET(n))
[all …]
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| /drivers/vhost/ |
| D | test.c | 43 static void handle_vq(struct vhost_test *n) in handle_vq() argument
45 struct vhost_virtqueue *vq = &n->vqs[VHOST_TEST_VQ]; in handle_vq()
58 vhost_disable_notify(&n->dev, vq); in handle_vq()
70 if (unlikely(vhost_enable_notify(&n->dev, vq))) { in handle_vq()
71 vhost_disable_notify(&n->dev, vq); in handle_vq()
87 vhost_add_used_and_signal(&n->dev, vq, head, 0); in handle_vq()
100 struct vhost_test *n = container_of(vq->dev, struct vhost_test, dev); in handle_vq_kick() local
102 handle_vq(n); in handle_vq_kick()
107 struct vhost_test *n = kmalloc(sizeof *n, GFP_KERNEL); in vhost_test_open() local
111 if (!n) in vhost_test_open()
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| /drivers/crypto/inside-secure/ |
| D | safexcel.h | 40 #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3) argument
41 #define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3) argument
147 #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n))) argument
148 #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n))) argument
149 #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n))) argument
150 #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n))) argument
151 #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n))) argument
152 #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n))) argument
153 #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n))) argument
167 #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) argument
[all …]
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| /drivers/staging/wlan-ng/ |
| D | p80211mgmt.h | 179 #define WLAN_GET_MGMT_CAP_INFO_ESS(n) ((n) & BIT(0)) argument
180 #define WLAN_GET_MGMT_CAP_INFO_IBSS(n) (((n) & BIT(1)) >> 1) argument
181 #define WLAN_GET_MGMT_CAP_INFO_CFPOLLABLE(n) (((n) & BIT(2)) >> 2) argument
182 #define WLAN_GET_MGMT_CAP_INFO_CFPOLLREQ(n) (((n) & BIT(3)) >> 3) argument
183 #define WLAN_GET_MGMT_CAP_INFO_PRIVACY(n) (((n) & BIT(4)) >> 4) argument
185 #define WLAN_GET_MGMT_CAP_INFO_SHORT(n) (((n) & BIT(5)) >> 5) argument
186 #define WLAN_GET_MGMT_CAP_INFO_PBCC(n) (((n) & BIT(6)) >> 6) argument
187 #define WLAN_GET_MGMT_CAP_INFO_AGILITY(n) (((n) & BIT(7)) >> 7) argument
189 #define WLAN_SET_MGMT_CAP_INFO_ESS(n) (n) argument
190 #define WLAN_SET_MGMT_CAP_INFO_IBSS(n) ((n) << 1) argument
[all …]
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| /drivers/gpu/drm/mxsfb/ |
| D | lcdif_regs.h | 150 #define DISP_SIZE_DELTA_Y(n) (((n) & 0xffff) << 16) argument
152 #define DISP_SIZE_DELTA_X(n) ((n) & 0xffff) argument
155 #define HSYN_PARA_BP_H(n) (((n) & 0xffff) << 16) argument
157 #define HSYN_PARA_FP_H(n) ((n) & 0xffff) argument
160 #define VSYN_PARA_BP_V(n) (((n) & 0xffff) << 16) argument
162 #define VSYN_PARA_FP_V(n) ((n) & 0xffff) argument
165 #define VSYN_HSYN_WIDTH_PW_V(n) (((n) & 0xffff) << 16) argument
167 #define VSYN_HSYN_WIDTH_PW_H(n) ((n) & 0xffff) argument
188 #define CTRLDESCL0_1_HEIGHT(n) (((n) & 0xffff) << 16) argument
190 #define CTRLDESCL0_1_WIDTH(n) ((n) & 0xffff) argument
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| /drivers/gpu/drm/panel/ |
| D | panel-sitronix-st7789v.c | 23 #define ST7789V_RAMCTRL_EPF(n) (((n) & 3) << 4) argument
27 #define ST7789V_RGBCTRL_RCM(n) (((n) & 3) << 5) argument
32 #define ST7789V_RGBCTRL_VBP(n) ((n) & 0x7f) argument
33 #define ST7789V_RGBCTRL_HBP(n) ((n) & 0x1f) argument
36 #define ST7789V_PORCTRL_IDLE_BP(n) (((n) & 0xf) << 4) argument
37 #define ST7789V_PORCTRL_IDLE_FP(n) ((n) & 0xf) argument
38 #define ST7789V_PORCTRL_PARTIAL_BP(n) (((n) & 0xf) << 4) argument
39 #define ST7789V_PORCTRL_PARTIAL_FP(n) ((n) & 0xf) argument
42 #define ST7789V_GCTRL_VGHS(n) (((n) & 7) << 4) argument
43 #define ST7789V_GCTRL_VGLS(n) ((n) & 7) argument
[all …]
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