| /drivers/gpu/drm/i915/gem/ |
| D | i915_gem_context.c | 392 unsigned num_engines; member
415 if (idx >= set->num_engines) { in set_proto_ctx_engines_balance()
417 idx, set->num_engines); in set_proto_ctx_engines_balance()
421 idx = array_index_nospec(idx, set->num_engines); in set_proto_ctx_engines_balance()
506 if (idx >= set->num_engines) { in set_proto_ctx_engines_bond()
509 idx, set->num_engines); in set_proto_ctx_engines_bond()
513 idx = array_index_nospec(idx, set->num_engines); in set_proto_ctx_engines_bond()
607 if (slot >= set->num_engines) { in set_proto_ctx_engines_parallel_submit()
609 slot, set->num_engines); in set_proto_ctx_engines_parallel_submit()
756 set.num_engines = (args->size - sizeof(*user)) / sizeof(*user->engines); in set_proto_ctx_engines()
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| D | i915_gem_context_types.h | 52 unsigned int num_engines; member
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| D | i915_gem_context.h | 214 else if (likely(idx < e->num_engines && e->engines[idx])) in i915_gem_context_get_engine()
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| /drivers/gpu/drm/i915/gt/uc/ |
| D | selftest_guc_multi_lrc.c | 13 static void logical_sort(struct intel_engine_cs **engines, int num_engines) in logical_sort() argument
18 for (i = 0; i < num_engines; ++i) in logical_sort()
27 sizeof(struct intel_engine_cs *) * num_engines); in logical_sort()
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| /drivers/crypto/intel/qat/qat_common/ |
| D | adf_hw_arbiter.c | 41 for_each_set_bit(i, &ae_mask, hw_data->num_engines) in adf_init_arb()
98 for (i = 0; i < hw_data->num_engines; i++) in adf_exit_arb()
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| D | adf_heartbeat.c | 59 const size_t max_aes = accel_dev->hw_device->num_engines; in validate_hb_ctrs_cnt()
87 const size_t max_aes = accel_dev->hw_device->num_engines; in adf_heartbeat_check_ctrs()
170 const size_t max_aes = hw_device->num_engines; in adf_hb_get_status()
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| D | adf_accel_devices.h | 237 u8 num_engines; member
266 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
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| D | adf_gen2_hw_data.c | 35 for_each_set_bit(i, &ae_mask, hw_data->num_engines) { in adf_gen2_enable_error_correction()
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_ring_submission.c | 695 const int num_engines = in mi_set_context() local
696 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0; in mi_set_context()
703 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); in mi_set_context()
720 if (num_engines) { in mi_set_context()
723 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
773 if (num_engines) { in mi_set_context()
777 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
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| D | intel_engine.h | 294 unsigned int num_engines, in intel_engine_create_parallel() argument
298 return engines[0]->cops->create_parallel(engines, num_engines, width); in intel_engine_create_parallel()
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| D | intel_gt_types.h | 266 u8 num_engines; member
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_dmm_tiler.c | 283 for (i = 0; i < dmm->num_engines; i++) { in omap_dmm_irq_handler()
754 REFILL_BUFFER_SIZE * omap_dmm->num_engines, in omap_dmm_remove()
836 omap_dmm->num_engines = (hwinfo >> 24) & 0x1F; in omap_dmm_probe()
841 atomic_set(&omap_dmm->engine_counter, omap_dmm->num_engines); in omap_dmm_probe()
877 REFILL_BUFFER_SIZE * omap_dmm->num_engines, in omap_dmm_probe()
886 omap_dmm->engines = kcalloc(omap_dmm->num_engines, in omap_dmm_probe()
893 for (i = 0; i < omap_dmm->num_engines; i++) { in omap_dmm_probe()
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| D | omap_dmm_priv.h | 168 int num_engines; member
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| /drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_context.c | 318 count = engines->num_engines; in live_parallel_switch()
1369 unsigned long idx, ndwords, dw, num_engines; in igt_ctx_readonly() local
1409 num_engines = 0; in igt_ctx_readonly()
1412 num_engines++; in igt_ctx_readonly()
1461 ndwords, num_engines); in igt_ctx_readonly()
1775 unsigned long num_engines, count; in igt_vm_isolation() local
1841 num_engines = 0; in igt_vm_isolation()
1883 num_engines++; in igt_vm_isolation()
1886 count, num_engines); in igt_vm_isolation()
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| D | mock_context.c | 136 engines->num_engines = 1; in live_context_for_engine()
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| /drivers/infiniband/hw/hfi1/ |
| D | sdma.c | 1253 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines) in sdma_clean() argument
1272 for (i = 0; dd->per_sdma && i < num_engines; ++i) { in sdma_clean()
1329 size_t num_engines = chip_sdma_engines(dd); in sdma_init() local
1341 num_engines = mod_num_sdma; in sdma_init()
1349 chip_sdma_mem_size(dd) / (num_engines * SDMA_BLOCK_SIZE); in sdma_init()
1357 num_engines, descq_cnt); in sdma_init()
1360 dd->per_sdma = kcalloc_node(num_engines, sizeof(*dd->per_sdma), in sdma_init()
1377 for (this_idx = 0; this_idx < num_engines; ++this_idx) { in sdma_init()
1443 dd->sdma_heads_size = L1_CACHE_BYTES * num_engines; in sdma_init()
1464 for (this_idx = 0; this_idx < num_engines; ++this_idx) { in sdma_init()
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| /drivers/crypto/intel/qat/qat_c62xvf/ |
| D | adf_c62xvf_hw_data.c | 69 hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES; in adf_init_hw_data_c62xiov()
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| /drivers/crypto/intel/qat/qat_c3xxxvf/ |
| D | adf_c3xxxvf_hw_data.c | 69 hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES; in adf_init_hw_data_c3xxxiov()
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| /drivers/crypto/intel/qat/qat_dh895xccvf/ |
| D | adf_dh895xccvf_hw_data.c | 69 hw_data->num_engines = ADF_DH895XCCIOV_MAX_ACCELENGINES; in adf_init_hw_data_dh895xcciov()
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| /drivers/gpu/drm/i915/ |
| D | i915_perf_types.h | 426 u32 num_engines; member
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| D | i915_query.c | 152 if (query.num_engines || query.rsvd[0] || query.rsvd[1] || in query_engine_info()
168 query.num_engines++; in query_engine_info()
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| /drivers/crypto/intel/qat/qat_c3xxx/ |
| D | adf_c3xxx_hw_data.c | 122 hw_data->num_engines = ADF_C3XXX_MAX_ACCELENGINES; in adf_init_hw_data_c3xxx()
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| /drivers/crypto/intel/qat/qat_c62x/ |
| D | adf_c62x_hw_data.c | 124 hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES; in adf_init_hw_data_c62x()
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| /drivers/accel/habanalabs/common/ |
| D | command_submission.c | 2486 u32 num_engines, enum hl_engine_command command) in cs_ioctl_engines() argument
2505 if (!num_engines || num_engines > max_num_of_engines) { in cs_ioctl_engines()
2506 dev_err(hdev->dev, "Number of engines %d is invalid\n", num_engines); in cs_ioctl_engines()
2511 engines = kmalloc_array(num_engines, sizeof(u32), GFP_KERNEL); in cs_ioctl_engines()
2515 if (copy_from_user(engines, engines_arr, num_engines * sizeof(u32))) { in cs_ioctl_engines()
2521 rc = hdev->asic_funcs->set_engines(hdev, engines, num_engines, command); in cs_ioctl_engines()
2600 args->in.num_engines, args->in.engine_command); in hl_cs_ioctl()
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| /drivers/crypto/intel/qat/qat_dh895xcc/ |
| D | adf_dh895xcc_hw_data.c | 218 hw_data->num_engines = ADF_DH895XCC_MAX_ACCELENGINES; in adf_init_hw_data_dh895xcc()
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