| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | mcs_reg.h | 15 u64 offset; \
17 offset = 0x408ull; \
19 offset = 0xa28ull; \
20 offset += (a) * 0x8ull; \
21 offset; })
25 u64 offset; \
27 offset = 0x808ull; \
29 offset = 0xa68ull; \
30 offset += (a) * 0x8ull; \
31 offset; })
[all …]
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| /drivers/net/ethernet/microchip/vcap/ |
| D | vcap_model_kunit.c | 20 .offset = 0,
25 .offset = 2,
30 .offset = 3,
35 .offset = 10,
40 .offset = 13,
45 .offset = 16,
50 .offset = 19,
55 .offset = 20,
60 .offset = 32,
65 .offset = 35,
[all …]
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| /drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_vcap_ag_api.c | 20 .offset = 0,
25 .offset = 1,
30 .offset = 2,
35 .offset = 4,
40 .offset = 16,
45 .offset = 18,
50 .offset = 83,
55 .offset = 84,
60 .offset = 85,
65 .offset = 88,
[all …]
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| /drivers/net/ethernet/microchip/lan966x/ |
| D | lan966x_vcap_ag_api.c | 12 .offset = 0,
17 .offset = 1,
22 .offset = 3,
27 .offset = 12,
32 .offset = 13,
37 .offset = 14,
42 .offset = 15,
47 .offset = 16,
52 .offset = 17,
57 .offset = 18,
[all …]
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| D | lan966x_ethtool.c | 12 { .name = "rx_octets", .offset = 0x00, },
13 { .name = "rx_unicast", .offset = 0x01, },
14 { .name = "rx_multicast", .offset = 0x02 },
15 { .name = "rx_broadcast", .offset = 0x03 },
16 { .name = "rx_short", .offset = 0x04 },
17 { .name = "rx_frag", .offset = 0x05 },
18 { .name = "rx_jabber", .offset = 0x06 },
19 { .name = "rx_crc", .offset = 0x07 },
20 { .name = "rx_symbol_err", .offset = 0x08 },
21 { .name = "rx_sz_64", .offset = 0x09 },
[all …]
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| /drivers/crypto/cavium/nitrox/ |
| D | nitrox_hal.c | 44 u64 offset; in nitrox_config_emu_unit() local
58 offset = EMU_WD_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
59 nitrox_write_csr(ndev, offset, emu_wd_int.value); in nitrox_config_emu_unit()
60 offset = EMU_GE_INT_ENA_W1SX(i); in nitrox_config_emu_unit()
61 nitrox_write_csr(ndev, offset, emu_ge_int.value); in nitrox_config_emu_unit()
70 u64 offset; in reset_pkt_input_ring() local
73 offset = NPS_PKT_IN_INSTR_CTLX(ring); in reset_pkt_input_ring()
74 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
76 nitrox_write_csr(ndev, offset, pkt_in_ctl.value); in reset_pkt_input_ring()
81 pkt_in_ctl.value = nitrox_read_csr(ndev, offset); in reset_pkt_input_ring()
[all …]
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| /drivers/gpio/ |
| D | gpio-eic-sprd.c | 139 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, in sprd_eic_update() argument
144 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_update()
152 tmp |= BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
154 tmp &= ~BIT(SPRD_EIC_BIT(offset)); in sprd_eic_update()
160 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_eic_read() argument
164 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); in sprd_eic_read()
166 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); in sprd_eic_read()
169 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) in sprd_eic_request() argument
171 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); in sprd_eic_request()
175 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) in sprd_eic_free() argument
[all …]
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| D | gpio-cs5535.c | 83 static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset, in __cs5535_gpio_set() argument
86 if (offset < 16) in __cs5535_gpio_set()
88 outl(1 << offset, chip->base + reg); in __cs5535_gpio_set()
91 errata_outl(chip, 1 << (offset - 16), reg); in __cs5535_gpio_set()
94 void cs5535_gpio_set(unsigned offset, unsigned int reg) in cs5535_gpio_set() argument
100 __cs5535_gpio_set(chip, offset, reg); in cs5535_gpio_set()
105 static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset, in __cs5535_gpio_clear() argument
108 if (offset < 16) in __cs5535_gpio_clear()
110 outl(1 << (offset + 16), chip->base + reg); in __cs5535_gpio_clear()
113 errata_outl(chip, 1 << offset, reg); in __cs5535_gpio_clear()
[all …]
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| D | gpio-aspeed.c | 253 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) in to_bank() argument
255 unsigned int bank = GPIO_BANK(offset); in to_bank()
267 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument
272 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
280 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument
282 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio()
283 const struct aspeed_gpio_bank *bank = to_bank(offset); in have_gpio()
284 unsigned int group = GPIO_OFFSET(offset) / 8; in have_gpio()
287 (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
290 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument
[all …]
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| D | gpio-sprd.c | 48 static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset, in sprd_gpio_update() argument
53 offset / SPRD_GPIO_BANK_NR); in sprd_gpio_update()
61 tmp |= BIT(SPRD_GPIO_BIT(offset)); in sprd_gpio_update()
63 tmp &= ~BIT(SPRD_GPIO_BIT(offset)); in sprd_gpio_update()
69 static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg) in sprd_gpio_read() argument
73 offset / SPRD_GPIO_BANK_NR); in sprd_gpio_read()
75 return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset))); in sprd_gpio_read()
78 static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset) in sprd_gpio_request() argument
80 sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1); in sprd_gpio_request()
84 static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset) in sprd_gpio_free() argument
[all …]
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| /drivers/net/wireless/ath/ath10k/ |
| D | qmi_wlfw_v01.c | 17 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01,
26 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01,
35 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01,
44 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01,
53 .offset = offsetof(struct wlfw_ce_tgt_pipe_cfg_s_v01,
66 .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01,
75 .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01,
84 .offset = offsetof(struct wlfw_ce_svc_pipe_cfg_s_v01,
97 .offset = offsetof(struct wlfw_shadow_reg_cfg_s_v01,
106 .offset = offsetof(struct wlfw_shadow_reg_cfg_s_v01,
[all …]
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| /drivers/thunderbolt/ |
| D | cap.c | 21 u32 value, offset; in tb_port_enable_tmu() local
29 offset = 0x26; in tb_port_enable_tmu()
31 offset = 0x2a; in tb_port_enable_tmu()
35 ret = tb_sw_read(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_port_enable_tmu()
44 return tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1); in tb_port_enable_tmu()
72 int tb_port_next_cap(struct tb_port *port, unsigned int offset) in tb_port_next_cap() argument
77 if (!offset) in tb_port_next_cap()
80 ret = tb_port_read(port, &header, TB_CFG_PORT, offset, 1); in tb_port_next_cap()
89 int offset = 0; in __tb_port_find_cap() local
95 offset = tb_port_next_cap(port, offset); in __tb_port_find_cap()
[all …]
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| /drivers/net/dsa/sja1105/ |
| D | sja1105_ethtool.c | 83 int offset; member
94 .offset = 0,
101 .offset = 0x0,
108 .offset = 0x0,
115 .offset = 0x0,
123 .offset = 0x1,
130 .offset = 0x1,
137 .offset = 0x1,
144 .offset = 0x1,
151 .offset = 0x1,
[all …]
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| /drivers/misc/ocxl/ |
| D | mmio.c | 7 int ocxl_global_mmio_read32(struct ocxl_afu *afu, size_t offset, in ocxl_global_mmio_read32() argument
10 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_read32()
20 *val = readl_be((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read32()
24 *val = readl((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read32()
32 int ocxl_global_mmio_read64(struct ocxl_afu *afu, size_t offset, in ocxl_global_mmio_read64() argument
35 if (offset > afu->config.global_mmio_size - 8) in ocxl_global_mmio_read64()
45 *val = readq_be((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read64()
49 *val = readq((char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_read64()
57 int ocxl_global_mmio_write32(struct ocxl_afu *afu, size_t offset, in ocxl_global_mmio_write32() argument
60 if (offset > afu->config.global_mmio_size - 4) in ocxl_global_mmio_write32()
[all …]
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| /drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| D | init.c | 43 init->offset, init_exec(init) ? \
365 return bit_I.offset; in init_table()
377 init_table_(struct nvbios_init *init, u16 offset, const char *name) in init_table_() argument
382 if (len >= offset + 2) { in init_table_()
383 data = nvbios_rd16(bios, data + offset); in init_table_()
461 init_xlat_(struct nvbios_init *init, u8 index, u8 offset) in init_xlat_() argument
468 return nvbios_rd08(bios, data + offset); in init_xlat_()
586 u8 opcode = nvbios_rd08(bios, init->offset); in init_reserved()
600 cont(" 0x%02x", nvbios_rd08(bios, init->offset + i)); in init_reserved()
602 init->offset += length; in init_reserved()
[all …]
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| /drivers/staging/media/atomisp/pci/ |
| D | ia_css_isp_configs.c | 27 unsigned int offset = 0; in ia_css_configure_iterator() local
39 offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; in ia_css_configure_iterator()
42 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_iterator()
50 unsigned int offset = 0; in ia_css_configure_copy_output() local
62 offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; in ia_css_configure_copy_output()
65 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_copy_output()
75 unsigned int offset = 0; in ia_css_configure_crop() local
87 offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; in ia_css_configure_crop()
90 &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], in ia_css_configure_crop()
98 unsigned int offset = 0; in ia_css_configure_fpn() local
[all …]
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| /drivers/net/ipa/ |
| D | ipa_qmi_msg.c | 20 .offset = offsetof(struct ipa_indication_register_req,
30 .offset = offsetof(struct ipa_indication_register_req,
40 .offset = offsetof(struct ipa_indication_register_req,
50 .offset = offsetof(struct ipa_indication_register_req,
60 .offset = offsetof(struct ipa_indication_register_req,
70 .offset = offsetof(struct ipa_indication_register_req,
80 .offset = offsetof(struct ipa_indication_register_req,
90 .offset = offsetof(struct ipa_indication_register_req,
100 .offset = offsetof(struct ipa_indication_register_req,
110 .offset = offsetof(struct ipa_indication_register_req,
[all …]
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| /drivers/pinctrl/ |
| D | pinctrl-da9062.c | 31 #define DA9062_TYPE(offset) (4 * (offset % 2)) argument
32 #define DA9062_PIN_SHIFT(offset) (4 * (offset % 2)) argument
46 unsigned int offset) in da9062_pctl_get_pin_mode() argument
51 ret = regmap_read(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), &val); in da9062_pctl_get_pin_mode()
55 val >>= DA9062_PIN_SHIFT(offset); in da9062_pctl_get_pin_mode()
62 unsigned int offset, unsigned int mode_req) in da9062_pctl_set_pin_mode() argument
70 mode <<= DA9062_PIN_SHIFT(offset); in da9062_pctl_set_pin_mode()
71 mask = DA9062AA_GPIO0_PIN_MASK << DA9062_PIN_SHIFT(offset); in da9062_pctl_set_pin_mode()
73 ret = regmap_update_bits(regmap, DA9062AA_GPIO_0_1 + (offset >> 1), in da9062_pctl_set_pin_mode()
76 pctl->pin_config[offset] = mode_req; in da9062_pctl_set_pin_mode()
[all …]
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| /drivers/gpu/drm/i915/display/ |
| D | dvo_ns2501.c | 195 u8 offset; member
301 [0] = { .offset = 0x0a, .value = 0x81, },
303 [1] = { .offset = 0x12, .value = 0x02, },
304 [2] = { .offset = 0x18, .value = 0x07, },
305 [3] = { .offset = 0x19, .value = 0x00, },
306 [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */
308 [5] = { .offset = 0x1e, .value = 0x02, },
309 [6] = { .offset = 0x1f, .value = 0x40, },
310 [7] = { .offset = 0x20, .value = 0x00, },
311 [8] = { .offset = 0x21, .value = 0x00, },
[all …]
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| /drivers/hwtracing/coresight/ |
| D | coresight-etm4x-cfg.c | 15 if (offset == cval) { \
47 struct cscfg_regval_csdev *reg_csdev, u32 offset) in etm4_cfg_map_reg_offset() argument
53 if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || in etm4_cfg_map_reg_offset()
54 ((offset >= TRCSEQRSTEVR) && (offset <= TRCEXTINSELR)) || in etm4_cfg_map_reg_offset()
55 ((offset >= TRCCIDCCTLR0) && (offset <= TRCVMIDCCTLR1))) { in etm4_cfg_map_reg_offset()
76 } else if ((offset & GENMASK(11, 4)) == TRCSEQEVRn(0)) { in etm4_cfg_map_reg_offset()
78 idx = (offset & GENMASK(3, 0)) / 4; in etm4_cfg_map_reg_offset()
83 } else if ((offset >= TRCSSCCRn(0)) && (offset <= TRCSSPCICRn(7))) { in etm4_cfg_map_reg_offset()
85 idx = (offset & GENMASK(4, 0)) / 4; in etm4_cfg_map_reg_offset()
86 off_mask = (offset & GENMASK(11, 5)); in etm4_cfg_map_reg_offset()
[all …]
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| /drivers/net/wireless/ath/ath6kl/ |
| D | bmi.c | 118 u32 offset; in ath6kl_bmi_read() local
143 offset = 0; in ath6kl_bmi_read()
144 memcpy(&(ar->bmi.cmd_buf[offset]), &cid, sizeof(cid)); in ath6kl_bmi_read()
145 offset += sizeof(cid); in ath6kl_bmi_read()
146 memcpy(&(ar->bmi.cmd_buf[offset]), &addr, sizeof(addr)); in ath6kl_bmi_read()
147 offset += sizeof(addr); in ath6kl_bmi_read()
148 memcpy(&(ar->bmi.cmd_buf[offset]), &rx_len, sizeof(rx_len)); in ath6kl_bmi_read()
149 offset += sizeof(len); in ath6kl_bmi_read()
151 ret = ath6kl_hif_bmi_write(ar, ar->bmi.cmd_buf, offset); in ath6kl_bmi_read()
174 u32 offset; in ath6kl_bmi_write() local
[all …]
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| /drivers/net/ethernet/qlogic/qed/ |
| D | qed_debug.c | 1129 u32 offset = 0; in qed_dump_str_param() local
1132 offset += qed_dump_str(char_buf + offset, dump, param_name); in qed_dump_str_param()
1136 *(char_buf + offset) = 1; in qed_dump_str_param()
1137 offset++; in qed_dump_str_param()
1140 offset += qed_dump_str(char_buf + offset, dump, param_val); in qed_dump_str_param()
1143 offset += qed_dump_align(char_buf + offset, dump, offset); in qed_dump_str_param()
1145 return BYTES_TO_DWORDS(offset); in qed_dump_str_param()
1155 u32 offset = 0; in qed_dump_num_param() local
1158 offset += qed_dump_str(char_buf + offset, dump, param_name); in qed_dump_num_param()
1162 *(char_buf + offset) = 0; in qed_dump_num_param()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | trace.h | 11 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
12 TP_ARGS(dev, offset, value),
15 __field(unsigned int, offset)
20 __entry->offset = offset;
23 TP_printk("%s %04x %08x", dev_name(__entry->dev), __entry->offset,
28 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
29 TP_ARGS(dev, offset, value));
31 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
32 TP_ARGS(dev, offset, value));
35 TP_PROTO(struct device *dev, unsigned int offset, u32 value),
[all …]
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| /drivers/pinctrl/spear/ |
| D | pinctrl-plgpio.c | 73 int (*o2p)(int offset); /* offset_to_pin */
84 u32 offset = PIN_OFFSET(pin); in is_plgpio_set() local
90 return !!(val & (1 << offset)); in is_plgpio_set()
95 u32 offset = PIN_OFFSET(pin); in plgpio_reg_set() local
99 mask = 1 << offset; in plgpio_reg_set()
105 u32 offset = PIN_OFFSET(pin); in plgpio_reg_reset() local
109 mask = 1 << offset; in plgpio_reg_reset()
115 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset) in plgpio_direction_input() argument
122 offset = plgpio->p2o(offset); in plgpio_direction_input()
123 if (offset == -1) in plgpio_direction_input()
[all …]
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| /drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_dcn30.c | 91 union dmub_addr offset; in dmub_dcn30_backdoor_load() local
100 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
102 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
103 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
109 dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
111 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); in dmub_dcn30_backdoor_load()
112 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); in dmub_dcn30_backdoor_load()
129 union dmub_addr offset; in dmub_dcn30_setup_windows() local
133 offset = cw2->offset; in dmub_dcn30_setup_windows()
136 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part); in dmub_dcn30_setup_windows()
[all …]
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