• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4  *
5  *
6  *          Name:  mpi2_cnfg.h
7  *         Title:  MPI Configuration messages and pages
8  * Creation Date:  November 10, 2006
9  *
10  *    mpi2_cnfg.h Version:  02.00.47
11  *
12  * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13  *       prefix are for use only on MPI v2.5 products, and must not be used
14  *       with MPI v2.0 products. Unless otherwise noted, names beginning with
15  *       MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16  *
17  * Version History
18  * ---------------
19  *
20  * Date      Version   Description
21  * --------  --------  ------------------------------------------------------
22  * 04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
23  * 06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
24  *                     Added Manufacturing Page 11.
25  *                     Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
26  *                     define.
27  * 06-26-07  02.00.02  Adding generic structure for product-specific
28  *                     Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
29  *                     Rework of BIOS Page 2 configuration page.
30  *                     Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
31  *                     forms.
32  *                     Added configuration pages IOC Page 8 and Driver
33  *                     Persistent Mapping Page 0.
34  * 08-31-07  02.00.03  Modified configuration pages dealing with Integrated
35  *                     RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
36  *                     RAID Physical Disk Pages 0 and 1, RAID Configuration
37  *                     Page 0).
38  *                     Added new value for AccessStatus field of SAS Device
39  *                     Page 0 (_SATA_NEEDS_INITIALIZATION).
40  * 10-31-07  02.00.04  Added missing SEPDevHandle field to
41  *                     MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
42  * 12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
43  *                     NVDATA.
44  *                     Modified IOC Page 7 to use masks and added field for
45  *                     SASBroadcastPrimitiveMasks.
46  *                     Added MPI2_CONFIG_PAGE_BIOS_4.
47  *                     Added MPI2_CONFIG_PAGE_LOG_0.
48  * 02-29-08  02.00.06  Modified various names to make them 32-character unique.
49  *                     Added SAS Device IDs.
50  *                     Updated Integrated RAID configuration pages including
51  *                     Manufacturing Page 4, IOC Page 6, and RAID Configuration
52  *                     Page 0.
53  * 05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
54  *                     Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
55  *                     Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
56  *                     Added missing MaxNumRoutedSasAddresses field to
57  *                     MPI2_CONFIG_PAGE_EXPANDER_0.
58  *                     Added SAS Port Page 0.
59  *                     Modified structure layout for
60  *                     MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
61  * 06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
62  *                     MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
63  * 10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
64  *                     to 0x000000FF.
65  *                     Added two new values for the Physical Disk Coercion Size
66  *                     bits in the Flags field of Manufacturing Page 4.
67  *                     Added product-specific Manufacturing pages 16 to 31.
68  *                     Modified Flags bits for controlling write cache on SATA
69  *                     drives in IO Unit Page 1.
70  *                     Added new bit to AdditionalControlFlags of SAS IO Unit
71  *                     Page 1 to control Invalid Topology Correction.
72  *                     Added additional defines for RAID Volume Page 0
73  *                     VolumeStatusFlags field.
74  *                     Modified meaning of RAID Volume Page 0 VolumeSettings
75  *                     define for auto-configure of hot-swap drives.
76  *                     Added SupportedPhysDisks field to RAID Volume Page 1 and
77  *                     added related defines.
78  *                     Added PhysDiskAttributes field (and related defines) to
79  *                     RAID Physical Disk Page 0.
80  *                     Added MPI2_SAS_PHYINFO_PHY_VACANT define.
81  *                     Added three new DiscoveryStatus bits for SAS IO Unit
82  *                     Page 0 and SAS Expander Page 0.
83  *                     Removed multiplexing information from SAS IO Unit pages.
84  *                     Added BootDeviceWaitTime field to SAS IO Unit Page 4.
85  *                     Removed Zone Address Resolved bit from PhyInfo and from
86  *                     Expander Page 0 Flags field.
87  *                     Added two new AccessStatus values to SAS Device Page 0
88  *                     for indicating routing problems. Added 3 reserved words
89  *                     to this page.
90  * 01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
91  *                     Inserted missing reserved field into structure for IOC
92  *                     Page 6.
93  *                     Added more pending task bits to RAID Volume Page 0
94  *                     VolumeStatusFlags defines.
95  *                     Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
96  *                     Added a new DiscoveryStatus bit for SAS IO Unit Page 0
97  *                     and SAS Expander Page 0 to flag a downstream initiator
98  *                     when in simplified routing mode.
99  *                     Removed SATA Init Failure defines for DiscoveryStatus
100  *                     fields of SAS IO Unit Page 0 and SAS Expander Page 0.
101  *                     Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
102  *                     Added PortGroups, DmaGroup, and ControlGroup fields to
103  *                     SAS Device Page 0.
104  * 05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
105  *                     Unit Page 6.
106  *                     Added expander reduced functionality data to SAS
107  *                     Expander Page 0.
108  *                     Added SAS PHY Page 2 and SAS PHY Page 3.
109  * 07-30-09  02.00.12  Added IO Unit Page 7.
110  *                     Added new device ids.
111  *                     Added SAS IO Unit Page 5.
112  *                     Added partial and slumber power management capable flags
113  *                     to SAS Device Page 0 Flags field.
114  *                     Added PhyInfo defines for power condition.
115  *                     Added Ethernet configuration pages.
116  * 10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
117  *                     Added SAS PHY Page 4 structure and defines.
118  * 02-10-10  02.00.14  Modified the comments for the configuration page
119  *                     structures that contain an array of data. The host
120  *                     should use the "count" field in the page data (e.g. the
121  *                     NumPhys field) to determine the number of valid elements
122  *                     in the array.
123  *                     Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
124  *                     Added PowerManagementCapabilities to IO Unit Page 7.
125  *                     Added PortWidthModGroup field to
126  *                     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
127  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
128  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
129  *                     Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
130  * 05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
131  *                     define.
132  *                     Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
133  *                     Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
134  * 08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
135  *                     defines.
136  * 11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
137  *                     MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
138  *                     the Pinout field.
139  *                     Added BoardTemperature and BoardTemperatureUnits fields
140  *                     to MPI2_CONFIG_PAGE_IO_UNIT_7.
141  *                     Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
142  *                     and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
143  * 02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
144  *                     Added IO Unit Page 8, IO Unit Page 9,
145  *                     and IO Unit Page 10.
146  *                     Added SASNotifyPrimitiveMasks field to
147  *                     MPI2_CONFIG_PAGE_IOC_7.
148  * 03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
149  * 05-25-11  02.00.20  Cleaned up a few comments.
150  * 08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
151  *                     for PCIe link as obsolete.
152  *                     Added SpinupFlags field containing a Disable Spin-up bit
153  *                     to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
154  *                     Unit Page 4.
155  * 11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
156  *                     Added UEFIVersion field to BIOS Page 1 and defined new
157  *                     BiosOptions bits.
158  *                     Incorporating additions for MPI v2.5.
159  * 11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
160  *                     Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
161  * 12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
162  *                     obsolete for MPI v2.5 and later.
163  *                     Added some defines for 12G SAS speeds.
164  * 04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
165  *                     Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
166  *                     match the specification.
167  * 08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
168  *			future use.
169  * 12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
170  *		       MPI2_CONFIG_PAGE_MAN_7.
171  *		       Added EnclosureLevel and ConnectorName fields to
172  *		       MPI2_CONFIG_PAGE_SAS_DEV_0.
173  *		       Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
174  *		       MPI2_CONFIG_PAGE_SAS_DEV_0.
175  *		       Added EnclosureLevel field to
176  *		       MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
177  *		       Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
178  *		       MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
179  * 01-08-14  02.00.28  Added more defines for the BiosOptions field of
180  *		       MPI2_CONFIG_PAGE_BIOS_1.
181  * 06-13-14  02.00.29  Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
182  *                     more defines for the BiosOptions field.
183  * 11-18-14  02.00.30  Updated copyright information.
184  *                     Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
185  *                     Added AdapterOrderAux fields to BIOS Page 3.
186  * 03-16-15  02.00.31  Updated for MPI v2.6.
187  *                     Added Flags field to IO Unit Page 7.
188  *                     Added new SAS Phy Event codes
189  * 05-25-15  02.00.33  Added more defines for the BiosOptions field of
190  *                     MPI2_CONFIG_PAGE_BIOS_1.
191  * 08-25-15  02.00.34  Bumped Header Version.
192  * 12-18-15  02.00.35  Added SATADeviceWaitTime to SAS IO Unit Page 4.
193  * 01-21-16  02.00.36  Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
194  *                     Added Link field to PCIe Link Pages
195  *                     Added EnclosureLevel and ConnectorName to PCIe
196  *                     Device Page 0.
197  *                     Added define for PCIE IoUnit page 1 max rate shift.
198  *                     Added comment for reserved ExtPageTypes.
199  *                     Added SAS 4 22.5 gbs speed support.
200  *                     Added PCIe 4 16.0 GT/sec speec support.
201  *                     Removed AHCI support.
202  *                     Removed SOP support.
203  *                     Added NegotiatedLinkRate and NegotiatedPortWidth to
204  *                     PCIe device page 0.
205  * 04-10-16  02.00.37  Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
206  * 07-01-16  02.00.38  Added Manufacturing page 7 Connector types.
207  *                     Changed declaration of ConnectorName in PCIe DevicePage0
208  *                     to match SAS DevicePage 0.
209  *                     Added SATADeviceWaitTime to IO Unit Page 11.
210  *                     Added MPI26_MFGPAGE_DEVID_SAS4008
211  *                     Added x16 PCIe width to IO Unit Page 7
212  *                     Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
213  *                     phy data.
214  *                     Added InitStatus to PCIe IO Unit Page 1 header.
215  * 09-01-16  02.00.39  Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
216  *                     Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
217  *                     MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
218  * 02-02-17  02.00.40  Added MPI2_MANPAGE7_SLOT_UNKNOWN.
219  *                     Added ChassisSlot field to SAS Enclosure Page 0.
220  *                     Added ChassisSlot Valid bit (bit 5) to the Flags field
221  *                     in SAS Enclosure Page 0.
222  * 06-13-17  02.00.41  Added MPI26_MFGPAGE_DEVID_SAS3816 and
223  *                     MPI26_MFGPAGE_DEVID_SAS3916 defines.
224  *                     Removed MPI26_MFGPAGE_DEVID_SAS4008 define.
225  *                     Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define.
226  *                     Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to
227  *                     PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN.
228  *                     Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to
229  *                     MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK.
230  * 09-29-17  02.00.42  Added ControllerResetTO field to PCIe Device Page 2.
231  *                     Added NOIOB field to PCIe Device Page 2.
232  *                     Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to
233  *                     the Capabilities field of PCIe Device Page 2.
234  * 07-22-18  02.00.43  Added defines for SAS3916 and SAS3816.
235  *                     Added WRiteCache defines to IO Unit Page 1.
236  *                     Added MaxEnclosureLevel to BIOS Page 1.
237  *                     Added OEMRD to SAS Enclosure Page 1.
238  *                     Added DMDReportPCIe to PCIe IO Unit Page 1.
239  *                     Added Flags field and flags for Retimers to
240  *                     PCIe Switch Page 1.
241  * 08-02-18  02.00.44  Added Slotx2, Slotx4 to ManPage 7.
242  * 08-15-18  02.00.45  Added ProductSpecific field at end of IOC Page 1
243  * 08-28-18  02.00.46  Added NVMs Write Cache flag to IOUnitPage1
244  *                     Added DMDReport Delay Time defines to
245  *                     PCIeIOUnitPage1
246  * --------------------------------------------------------------------------
247  * 08-02-18  02.00.44  Added Slotx2, Slotx4 to ManPage 7.
248  * 08-15-18  02.00.45  Added ProductSpecific field at end of IOC Page 1
249  * 08-28-18  02.00.46  Added NVMs Write Cache flag to IOUnitPage1
250  *                     Added DMDReport Delay Time defines to PCIeIOUnitPage1
251  * 12-17-18  02.00.47  Swap locations of Slotx2 and Slotx4 in ManPage 7.
252  * 08-01-19  02.00.49  Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID
253  *                     Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT
254  */
255 
256 #ifndef MPI2_CNFG_H
257 #define MPI2_CNFG_H
258 
259 /*****************************************************************************
260 *  Configuration Page Header and defines
261 *****************************************************************************/
262 
263 /*Config Page Header */
264 typedef struct _MPI2_CONFIG_PAGE_HEADER {
265 	U8                 PageVersion;                /*0x00 */
266 	U8                 PageLength;                 /*0x01 */
267 	U8                 PageNumber;                 /*0x02 */
268 	U8                 PageType;                   /*0x03 */
269 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
270 	Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
271 
272 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
273 	MPI2_CONFIG_PAGE_HEADER  Struct;
274 	U8                       Bytes[4];
275 	U16                      Word16[2];
276 	U32                      Word32;
277 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
278 	Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
279 
280 /*Extended Config Page Header */
281 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
282 	U8                  PageVersion;                /*0x00 */
283 	U8                  Reserved1;                  /*0x01 */
284 	U8                  PageNumber;                 /*0x02 */
285 	U8                  PageType;                   /*0x03 */
286 	U16                 ExtPageLength;              /*0x04 */
287 	U8                  ExtPageType;                /*0x06 */
288 	U8                  Reserved2;                  /*0x07 */
289 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
290 	*PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
291 	Mpi2ConfigExtendedPageHeader_t,
292 	*pMpi2ConfigExtendedPageHeader_t;
293 
294 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
295 	MPI2_CONFIG_PAGE_HEADER          Struct;
296 	MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
297 	U8                               Bytes[8];
298 	U16                              Word16[4];
299 	U32                              Word32[2];
300 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
301 	*PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
302 	Mpi2ConfigPageExtendedHeaderUnion,
303 	*pMpi2ConfigPageExtendedHeaderUnion;
304 
305 
306 /*PageType field values */
307 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
308 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
309 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
310 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
311 
312 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
313 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
314 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
315 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
316 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
317 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
318 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
319 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
320 
321 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
322 
323 
324 /*ExtPageType field values */
325 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
326 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
327 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
328 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
329 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
330 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
331 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
332 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
333 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
334 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
335 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
336 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT        (0x1B)
337 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH         (0x1C)
338 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE         (0x1D)
339 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK           (0x1E)
340 
341 
342 /*****************************************************************************
343 *  PageAddress defines
344 *****************************************************************************/
345 
346 /*RAID Volume PageAddress format */
347 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
348 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
349 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
350 
351 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
352 
353 
354 /*RAID Physical Disk PageAddress format */
355 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
356 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
357 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
358 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
359 
360 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
361 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
362 
363 
364 /*SAS Expander PageAddress format */
365 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
366 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
367 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
368 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
369 
370 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
371 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
372 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
373 
374 
375 /*SAS Device PageAddress format */
376 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
377 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
378 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
379 
380 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
381 
382 
383 /*SAS PHY PageAddress format */
384 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
385 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
386 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
387 
388 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
389 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
390 
391 
392 /*SAS Port PageAddress format */
393 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
394 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
395 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
396 
397 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
398 
399 
400 /*SAS Enclosure PageAddress format */
401 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
402 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
403 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
404 
405 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
406 
407 /*Enclosure PageAddress format */
408 #define MPI26_ENCLOS_PGAD_FORM_MASK                 (0xF0000000)
409 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
410 #define MPI26_ENCLOS_PGAD_FORM_HANDLE               (0x10000000)
411 
412 #define MPI26_ENCLOS_PGAD_HANDLE_MASK               (0x0000FFFF)
413 
414 /*RAID Configuration PageAddress format */
415 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
416 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
417 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
418 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
419 
420 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
421 
422 
423 /*Driver Persistent Mapping PageAddress format */
424 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
425 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
426 
427 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
428 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
429 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
430 
431 
432 /*Ethernet PageAddress format */
433 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
434 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
435 
436 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
437 
438 
439 /*PCIe Switch PageAddress format */
440 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK            (0xF0000000)
441 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL   (0x00000000)
442 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM    (0x10000000)
443 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL     (0x20000000)
444 
445 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK          (0x0000FFFF)
446 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK         (0x00FF0000)
447 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT        (16)
448 
449 
450 /*PCIe Device PageAddress format */
451 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK            (0xF0000000)
452 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
453 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE          (0x20000000)
454 
455 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK          (0x0000FFFF)
456 
457 /*PCIe Link PageAddress format */
458 #define MPI26_PCIE_LINK_PGAD_FORM_MASK            (0xF0000000)
459 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK   (0x00000000)
460 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM        (0x10000000)
461 
462 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK       (0x000000FF)
463 
464 
465 
466 /****************************************************************************
467 *  Configuration messages
468 ****************************************************************************/
469 
470 /*Configuration Request Message */
471 typedef struct _MPI2_CONFIG_REQUEST {
472 	U8                      Action;                     /*0x00 */
473 	U8                      SGLFlags;                   /*0x01 */
474 	U8                      ChainOffset;                /*0x02 */
475 	U8                      Function;                   /*0x03 */
476 	U16                     ExtPageLength;              /*0x04 */
477 	U8                      ExtPageType;                /*0x06 */
478 	U8                      MsgFlags;                   /*0x07 */
479 	U8                      VP_ID;                      /*0x08 */
480 	U8                      VF_ID;                      /*0x09 */
481 	U16                     Reserved1;                  /*0x0A */
482 	U8                      Reserved2;                  /*0x0C */
483 	U8                      ProxyVF_ID;                 /*0x0D */
484 	U16                     Reserved4;                  /*0x0E */
485 	U32                     Reserved3;                  /*0x10 */
486 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
487 	U32                     PageAddress;                /*0x18 */
488 	MPI2_SGE_IO_UNION       PageBufferSGE;              /*0x1C */
489 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
490 	Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
491 
492 /*values for the Action field */
493 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
494 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
495 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
496 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
497 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
498 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
499 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
500 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
501 
502 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
503 
504 
505 /*Config Reply Message */
506 typedef struct _MPI2_CONFIG_REPLY {
507 	U8                      Action;                     /*0x00 */
508 	U8                      SGLFlags;                   /*0x01 */
509 	U8                      MsgLength;                  /*0x02 */
510 	U8                      Function;                   /*0x03 */
511 	U16                     ExtPageLength;              /*0x04 */
512 	U8                      ExtPageType;                /*0x06 */
513 	U8                      MsgFlags;                   /*0x07 */
514 	U8                      VP_ID;                      /*0x08 */
515 	U8                      VF_ID;                      /*0x09 */
516 	U16                     Reserved1;                  /*0x0A */
517 	U16                     Reserved2;                  /*0x0C */
518 	U16                     IOCStatus;                  /*0x0E */
519 	U32                     IOCLogInfo;                 /*0x10 */
520 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x14 */
521 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
522 	Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
523 
524 
525 
526 /*****************************************************************************
527 *
528 *              C o n f i g u r a t i o n    P a g e s
529 *
530 *****************************************************************************/
531 
532 /****************************************************************************
533 *  Manufacturing Config pages
534 ****************************************************************************/
535 
536 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
537 #define MPI2_MFGPAGE_VENDORID_ATTO                  (0x117C)
538 
539 /*MPI v2.0 SAS products */
540 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
541 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
542 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
543 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
544 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
545 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
546 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
547 
548 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
549 
550 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
551 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
552 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
553 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
554 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
555 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
556 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
557 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
558 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
559 #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP            (0x02B0)
560 #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1          (0x02B1)
561 
562 /*MPI v2.5 SAS products */
563 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
564 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
565 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
566 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
567 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
568 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
569 
570 /* MPI v2.6 SAS Products */
571 #define MPI26_MFGPAGE_DEVID_SAS3216                 (0x00C9)
572 #define MPI26_MFGPAGE_DEVID_SAS3224                 (0x00C4)
573 #define MPI26_MFGPAGE_DEVID_SAS3316_1               (0x00C5)
574 #define MPI26_MFGPAGE_DEVID_SAS3316_2               (0x00C6)
575 #define MPI26_MFGPAGE_DEVID_SAS3316_3               (0x00C7)
576 #define MPI26_MFGPAGE_DEVID_SAS3316_4               (0x00C8)
577 #define MPI26_MFGPAGE_DEVID_SAS3324_1               (0x00C0)
578 #define MPI26_MFGPAGE_DEVID_SAS3324_2               (0x00C1)
579 #define MPI26_MFGPAGE_DEVID_SAS3324_3               (0x00C2)
580 #define MPI26_MFGPAGE_DEVID_SAS3324_4               (0x00C3)
581 
582 #define MPI26_MFGPAGE_DEVID_SAS3516                 (0x00AA)
583 #define MPI26_MFGPAGE_DEVID_SAS3516_1               (0x00AB)
584 #define MPI26_MFGPAGE_DEVID_SAS3416                 (0x00AC)
585 #define MPI26_MFGPAGE_DEVID_SAS3508                 (0x00AD)
586 #define MPI26_MFGPAGE_DEVID_SAS3508_1               (0x00AE)
587 #define MPI26_MFGPAGE_DEVID_SAS3408                 (0x00AF)
588 #define MPI26_MFGPAGE_DEVID_SAS3716                 (0x00D0)
589 #define MPI26_MFGPAGE_DEVID_SAS3616                 (0x00D1)
590 #define MPI26_MFGPAGE_DEVID_SAS3708                 (0x00D2)
591 
592 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3916           (0x0003)
593 #define MPI26_MFGPAGE_DEVID_INVALID0_3916           (0x00E0)
594 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3916            (0x00E1)
595 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3916           (0x00E2)
596 #define MPI26_MFGPAGE_DEVID_INVALID1_3916           (0x00E3)
597 
598 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3816           (0x0003)
599 #define MPI26_MFGPAGE_DEVID_INVALID0_3816           (0x00E4)
600 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3816            (0x00E5)
601 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3816           (0x00E6)
602 #define MPI26_MFGPAGE_DEVID_INVALID1_3816           (0x00E7)
603 
604 
605 /*Manufacturing Page 0 */
606 
607 typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
608 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
609 	U8                      ChipName[16];               /*0x04 */
610 	U8                      ChipRevision[8];            /*0x14 */
611 	U8                      BoardName[16];              /*0x1C */
612 	U8                      BoardAssembly[16];          /*0x2C */
613 	U8                      BoardTracerNumber[16];      /*0x3C */
614 } MPI2_CONFIG_PAGE_MAN_0,
615 	*PTR_MPI2_CONFIG_PAGE_MAN_0,
616 	Mpi2ManufacturingPage0_t,
617 	*pMpi2ManufacturingPage0_t;
618 
619 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
620 
621 
622 /*Manufacturing Page 1 */
623 
624 typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
625 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
626 	U8                      VPD[256];                   /*0x04 */
627 } MPI2_CONFIG_PAGE_MAN_1,
628 	*PTR_MPI2_CONFIG_PAGE_MAN_1,
629 	Mpi2ManufacturingPage1_t,
630 	*pMpi2ManufacturingPage1_t;
631 
632 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
633 
634 
635 typedef struct _MPI2_CHIP_REVISION_ID {
636 	U16 DeviceID;                                       /*0x00 */
637 	U8  PCIRevisionID;                                  /*0x02 */
638 	U8  Reserved;                                       /*0x03 */
639 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
640 	Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
641 
642 
643 /*Manufacturing Page 2 */
644 
645 /*
646  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
647  *one and check Header.PageLength at runtime.
648  */
649 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
650 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
651 #endif
652 
653 typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
654 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
655 	MPI2_CHIP_REVISION_ID   ChipId;                     /*0x04 */
656 	U32
657 		HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
658 } MPI2_CONFIG_PAGE_MAN_2,
659 	*PTR_MPI2_CONFIG_PAGE_MAN_2,
660 	Mpi2ManufacturingPage2_t,
661 	*pMpi2ManufacturingPage2_t;
662 
663 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
664 
665 
666 /*Manufacturing Page 3 */
667 
668 /*
669  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
670  *one and check Header.PageLength at runtime.
671  */
672 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
673 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
674 #endif
675 
676 typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
677 	MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
678 	MPI2_CHIP_REVISION_ID               ChipId;         /*0x04 */
679 	U32
680 		Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
681 } MPI2_CONFIG_PAGE_MAN_3,
682 	*PTR_MPI2_CONFIG_PAGE_MAN_3,
683 	Mpi2ManufacturingPage3_t,
684 	*pMpi2ManufacturingPage3_t;
685 
686 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
687 
688 
689 /*Manufacturing Page 4 */
690 
691 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
692 	U8                          PowerSaveFlags;                 /*0x00 */
693 	U8                          InternalOperationsSleepTime;    /*0x01 */
694 	U8                          InternalOperationsRunTime;      /*0x02 */
695 	U8                          HostIdleTime;                   /*0x03 */
696 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
697 	*PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
698 	Mpi2ManPage4PwrSaveSettings_t,
699 	*pMpi2ManPage4PwrSaveSettings_t;
700 
701 /*defines for the PowerSaveFlags field */
702 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
703 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
704 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
705 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
706 
707 typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
708 	MPI2_CONFIG_PAGE_HEADER             Header;                 /*0x00 */
709 	U32                                 Reserved1;              /*0x04 */
710 	U32                                 Flags;                  /*0x08 */
711 	U8                                  InquirySize;            /*0x0C */
712 	U8                                  Reserved2;              /*0x0D */
713 	U16                                 Reserved3;              /*0x0E */
714 	U8                                  InquiryData[56];        /*0x10 */
715 	U32                                 RAID0VolumeSettings;    /*0x48 */
716 	U32                                 RAID1EVolumeSettings;   /*0x4C */
717 	U32                                 RAID1VolumeSettings;    /*0x50 */
718 	U32                                 RAID10VolumeSettings;   /*0x54 */
719 	U32                                 Reserved4;              /*0x58 */
720 	U32                                 Reserved5;              /*0x5C */
721 	MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /*0x60 */
722 	U8                                  MaxOCEDisks;            /*0x64 */
723 	U8                                  ResyncRate;             /*0x65 */
724 	U16                                 DataScrubDuration;      /*0x66 */
725 	U8                                  MaxHotSpares;           /*0x68 */
726 	U8                                  MaxPhysDisksPerVol;     /*0x69 */
727 	U8                                  MaxPhysDisks;           /*0x6A */
728 	U8                                  MaxVolumes;             /*0x6B */
729 } MPI2_CONFIG_PAGE_MAN_4,
730 	*PTR_MPI2_CONFIG_PAGE_MAN_4,
731 	Mpi2ManufacturingPage4_t,
732 	*pMpi2ManufacturingPage4_t;
733 
734 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
735 
736 /*Manufacturing Page 4 Flags field */
737 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
738 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
739 
740 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
741 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
742 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
743 
744 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
745 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
746 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
747 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
748 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
749 
750 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
751 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
752 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
753 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
754 
755 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
756 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
757 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
758 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
759 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
760 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
761 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
762 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
763 
764 
765 /*Manufacturing Page 5 */
766 
767 /*
768  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
769  *one and check the value returned for NumPhys at runtime.
770  */
771 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
772 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
773 #endif
774 
775 typedef struct _MPI2_MANUFACTURING5_ENTRY {
776 	U64                                 WWID;           /*0x00 */
777 	U64                                 DeviceName;     /*0x08 */
778 } MPI2_MANUFACTURING5_ENTRY,
779 	*PTR_MPI2_MANUFACTURING5_ENTRY,
780 	Mpi2Manufacturing5Entry_t,
781 	*pMpi2Manufacturing5Entry_t;
782 
783 typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
784 	MPI2_CONFIG_PAGE_HEADER             Header;         /*0x00 */
785 	U8                                  NumPhys;        /*0x04 */
786 	U8                                  Reserved1;      /*0x05 */
787 	U16                                 Reserved2;      /*0x06 */
788 	U32                                 Reserved3;      /*0x08 */
789 	U32                                 Reserved4;      /*0x0C */
790 	MPI2_MANUFACTURING5_ENTRY
791 		Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
792 } MPI2_CONFIG_PAGE_MAN_5,
793 	*PTR_MPI2_CONFIG_PAGE_MAN_5,
794 	Mpi2ManufacturingPage5_t,
795 	*pMpi2ManufacturingPage5_t;
796 
797 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
798 
799 
800 /*Manufacturing Page 6 */
801 
802 typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
803 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
804 	U32                             ProductSpecificInfo;/*0x04 */
805 } MPI2_CONFIG_PAGE_MAN_6,
806 	*PTR_MPI2_CONFIG_PAGE_MAN_6,
807 	Mpi2ManufacturingPage6_t,
808 	*pMpi2ManufacturingPage6_t;
809 
810 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
811 
812 
813 /*Manufacturing Page 7 */
814 
815 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
816 	U32                         Pinout;                 /*0x00 */
817 	U8                          Connector[16];          /*0x04 */
818 	U8                          Location;               /*0x14 */
819 	U8                          ReceptacleID;           /*0x15 */
820 	U16                         Slot;                   /*0x16 */
821 	U16                         Slotx2;                 /*0x18 */
822 	U16                         Slotx4;                 /*0x1A */
823 } MPI2_MANPAGE7_CONNECTOR_INFO,
824 	*PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
825 	Mpi2ManPage7ConnectorInfo_t,
826 	*pMpi2ManPage7ConnectorInfo_t;
827 
828 /*defines for the Pinout field */
829 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
830 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
831 
832 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
833 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
834 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
835 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
836 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
837 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
838 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
839 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
840 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
841 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
842 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
843 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
844 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
845 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
846 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
847 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A                 (0x0E)
848 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i               (0x0F)
849 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i                (0x10)
850 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i                (0x11)
851 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i                (0x12)
852 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i                (0x13)
853 
854 /*defines for the Location field */
855 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
856 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
857 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
858 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
859 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
860 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
861 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
862 
863 /*defines for the Slot field */
864 #define MPI2_MANPAGE7_SLOT_UNKNOWN                      (0xFFFF)
865 
866 /*
867  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
868  *one and check the value returned for NumPhys at runtime.
869  */
870 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
871 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
872 #endif
873 
874 typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
875 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
876 	U32                             Reserved1;          /*0x04 */
877 	U32                             Reserved2;          /*0x08 */
878 	U32                             Flags;              /*0x0C */
879 	U8                              EnclosureName[16];  /*0x10 */
880 	U8                              NumPhys;            /*0x20 */
881 	U8                              Reserved3;          /*0x21 */
882 	U16                             Reserved4;          /*0x22 */
883 	MPI2_MANPAGE7_CONNECTOR_INFO
884 	ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
885 } MPI2_CONFIG_PAGE_MAN_7,
886 	*PTR_MPI2_CONFIG_PAGE_MAN_7,
887 	Mpi2ManufacturingPage7_t,
888 	*pMpi2ManufacturingPage7_t;
889 
890 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
891 
892 /*defines for the Flags field */
893 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
894 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
895 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
896 
897 #define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT        (0x00000020)
898 #define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID       (0x00000010)
899 
900 /*
901  *Generic structure to use for product-specific manufacturing pages
902  *(currently Manufacturing Page 8 through Manufacturing Page 31).
903  */
904 
905 typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
906 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
907 	U32                             ProductSpecificInfo;/*0x04 */
908 } MPI2_CONFIG_PAGE_MAN_PS,
909 	*PTR_MPI2_CONFIG_PAGE_MAN_PS,
910 	Mpi2ManufacturingPagePS_t,
911 	*pMpi2ManufacturingPagePS_t;
912 
913 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
914 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
915 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
916 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
917 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
918 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
919 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
920 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
921 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
922 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
923 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
924 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
925 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
926 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
927 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
928 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
929 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
930 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
931 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
932 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
933 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
934 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
935 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
936 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
937 
938 
939 /****************************************************************************
940 *  IO Unit Config Pages
941 ****************************************************************************/
942 
943 /*IO Unit Page 0 */
944 
945 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
946 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
947 	U64                     UniqueValue;                /*0x04 */
948 	MPI2_VERSION_UNION      NvdataVersionDefault;       /*0x08 */
949 	MPI2_VERSION_UNION      NvdataVersionPersistent;    /*0x0A */
950 } MPI2_CONFIG_PAGE_IO_UNIT_0,
951 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
952 	Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
953 
954 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
955 
956 
957 /*IO Unit Page 1 */
958 
959 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
960 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
961 	U32                     Flags;                      /*0x04 */
962 } MPI2_CONFIG_PAGE_IO_UNIT_1,
963 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
964 	Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
965 
966 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
967 
968 /* IO Unit Page 1 Flags defines */
969 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK             (0x00030000)
970 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT            (16)
971 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE        (0x00000000)
972 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE           (0x00010000)
973 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE          (0x00020000)
974 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
975 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
976 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
977 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
978 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
979 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
980 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
981 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
982 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
983 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
984 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
985 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
986 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
987 
988 
989 /*IO Unit Page 3 */
990 
991 /*
992  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
993  *one and check the value returned for GPIOCount at runtime.
994  */
995 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
996 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (36)
997 #endif
998 
999 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
1000 	MPI2_CONFIG_PAGE_HEADER Header;			 /*0x00 */
1001 	U8                      GPIOCount;		 /*0x04 */
1002 	U8                      Reserved1;		 /*0x05 */
1003 	U16                     Reserved2;		 /*0x06 */
1004 	U16
1005 		GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
1006 } MPI2_CONFIG_PAGE_IO_UNIT_3,
1007 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
1008 	Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
1009 
1010 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
1011 
1012 /*defines for IO Unit Page 3 GPIOVal field */
1013 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
1014 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
1015 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
1016 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
1017 
1018 
1019 /*IO Unit Page 5 */
1020 
1021 /*
1022  *Upper layer code (drivers, utilities, etc.) should leave this define set to
1023  *one and check the value returned for NumDmaEngines at runtime.
1024  */
1025 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
1026 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
1027 #endif
1028 
1029 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
1030 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1031 	U64
1032 		RaidAcceleratorBufferBaseAddress;           /*0x04 */
1033 	U64
1034 		RaidAcceleratorBufferSize;                  /*0x0C */
1035 	U64
1036 		RaidAcceleratorControlBaseAddress;          /*0x14 */
1037 	U8                      RAControlSize;              /*0x1C */
1038 	U8                      NumDmaEngines;              /*0x1D */
1039 	U8                      RAMinControlSize;           /*0x1E */
1040 	U8                      RAMaxControlSize;           /*0x1F */
1041 	U32                     Reserved1;                  /*0x20 */
1042 	U32                     Reserved2;                  /*0x24 */
1043 	U32                     Reserved3;                  /*0x28 */
1044 	U32
1045 	DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
1046 } MPI2_CONFIG_PAGE_IO_UNIT_5,
1047 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
1048 	Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
1049 
1050 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
1051 
1052 /*defines for IO Unit Page 5 DmaEngineCapabilities field */
1053 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
1054 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
1055 
1056 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
1057 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
1058 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
1059 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
1060 
1061 
1062 /*IO Unit Page 6 */
1063 
1064 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
1065 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1066 	U16                     Flags;                  /*0x04 */
1067 	U8                      RAHostControlSize;      /*0x06 */
1068 	U8                      Reserved0;              /*0x07 */
1069 	U64
1070 		RaidAcceleratorHostControlBaseAddress;  /*0x08 */
1071 	U32                     Reserved1;              /*0x10 */
1072 	U32                     Reserved2;              /*0x14 */
1073 	U32                     Reserved3;              /*0x18 */
1074 } MPI2_CONFIG_PAGE_IO_UNIT_6,
1075 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
1076 	Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
1077 
1078 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
1079 
1080 /*defines for IO Unit Page 6 Flags field */
1081 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
1082 
1083 
1084 /*IO Unit Page 7 */
1085 
1086 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
1087 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1088 	U8                      CurrentPowerMode;       /*0x04 */
1089 	U8                      PreviousPowerMode;      /*0x05 */
1090 	U8                      PCIeWidth;              /*0x06 */
1091 	U8                      PCIeSpeed;              /*0x07 */
1092 	U32                     ProcessorState;         /*0x08 */
1093 	U32
1094 		PowerManagementCapabilities;            /*0x0C */
1095 	U16                     IOCTemperature;         /*0x10 */
1096 	U8
1097 		IOCTemperatureUnits;                    /*0x12 */
1098 	U8                      IOCSpeed;               /*0x13 */
1099 	U16                     BoardTemperature;       /*0x14 */
1100 	U8
1101 		BoardTemperatureUnits;                  /*0x16 */
1102 	U8                      Reserved3;              /*0x17 */
1103 	U32			BoardPowerRequirement;	/*0x18 */
1104 	U32			PCISlotPowerAllocation;	/*0x1C */
1105 /* reserved prior to MPI v2.6 */
1106 	U8		Flags;			/* 0x20 */
1107 	U8		Reserved6;			/* 0x21 */
1108 	U16		Reserved7;			/* 0x22 */
1109 	U32		Reserved8;			/* 0x24 */
1110 } MPI2_CONFIG_PAGE_IO_UNIT_7,
1111 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
1112 	Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
1113 
1114 #define MPI2_IOUNITPAGE7_PAGEVERSION			(0x05)
1115 
1116 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
1117 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
1118 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
1119 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
1120 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
1121 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
1122 
1123 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
1124 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
1125 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
1126 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
1127 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
1128 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
1129 
1130 
1131 /*defines for IO Unit Page 7 PCIeWidth field */
1132 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
1133 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
1134 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
1135 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
1136 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16             (0x10)
1137 
1138 /*defines for IO Unit Page 7 PCIeSpeed field */
1139 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
1140 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
1141 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
1142 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS       (0x03)
1143 
1144 /*defines for IO Unit Page 7 ProcessorState field */
1145 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
1146 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
1147 
1148 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
1149 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
1150 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
1151 
1152 /*defines for IO Unit Page 7 PowerManagementCapabilities field */
1153 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
1154 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
1155 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
1156 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
1157 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
1158 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
1159 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
1160 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
1161 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
1162 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
1163 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
1164 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
1165 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
1166 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
1167 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
1168 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008)
1169 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004)
1170 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002)
1171 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001)
1172 
1173 /*obsolete names for the PowerManagementCapabilities bits (above) */
1174 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
1175 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
1176 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
1177 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /*obsolete */
1178 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /*obsolete */
1179 
1180 
1181 /*defines for IO Unit Page 7 IOCTemperatureUnits field */
1182 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
1183 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
1184 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
1185 
1186 /*defines for IO Unit Page 7 IOCSpeed field */
1187 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
1188 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
1189 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
1190 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
1191 
1192 /*defines for IO Unit Page 7 BoardTemperatureUnits field */
1193 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
1194 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
1195 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
1196 
1197 /* defines for IO Unit Page 7 Flags field */
1198 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC       (0x01)
1199 
1200 /*IO Unit Page 8 */
1201 
1202 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
1203 
1204 typedef struct _MPI2_IOUNIT8_SENSOR {
1205 	U16                     Flags;                  /*0x00 */
1206 	U16                     Reserved1;              /*0x02 */
1207 	U16
1208 		Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1209 	U32                     Reserved2;              /*0x0C */
1210 	U32                     Reserved3;              /*0x10 */
1211 	U32                     Reserved4;              /*0x14 */
1212 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1213 	Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1214 
1215 /*defines for IO Unit Page 8 Sensor Flags field */
1216 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
1217 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
1218 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
1219 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
1220 
1221 /*
1222  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1223  *one and check the value returned for NumSensors at runtime.
1224  */
1225 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1226 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
1227 #endif
1228 
1229 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1230 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1231 	U32                     Reserved1;              /*0x04 */
1232 	U32                     Reserved2;              /*0x08 */
1233 	U8                      NumSensors;             /*0x0C */
1234 	U8                      PollingInterval;        /*0x0D */
1235 	U16                     Reserved3;              /*0x0E */
1236 	MPI2_IOUNIT8_SENSOR
1237 		Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1238 } MPI2_CONFIG_PAGE_IO_UNIT_8,
1239 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1240 	Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1241 
1242 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
1243 
1244 
1245 /*IO Unit Page 9 */
1246 
1247 typedef struct _MPI2_IOUNIT9_SENSOR {
1248 	U16                     CurrentTemperature;     /*0x00 */
1249 	U16                     Reserved1;              /*0x02 */
1250 	U8                      Flags;                  /*0x04 */
1251 	U8                      Reserved2;              /*0x05 */
1252 	U16                     Reserved3;              /*0x06 */
1253 	U32                     Reserved4;              /*0x08 */
1254 	U32                     Reserved5;              /*0x0C */
1255 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1256 	Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1257 
1258 /*defines for IO Unit Page 9 Sensor Flags field */
1259 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
1260 
1261 /*
1262  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1263  *one and check the value returned for NumSensors at runtime.
1264  */
1265 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1266 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
1267 #endif
1268 
1269 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1270 	MPI2_CONFIG_PAGE_HEADER Header;                 /*0x00 */
1271 	U32                     Reserved1;              /*0x04 */
1272 	U32                     Reserved2;              /*0x08 */
1273 	U8                      NumSensors;             /*0x0C */
1274 	U8                      Reserved4;              /*0x0D */
1275 	U16                     Reserved3;              /*0x0E */
1276 	MPI2_IOUNIT9_SENSOR
1277 		Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1278 } MPI2_CONFIG_PAGE_IO_UNIT_9,
1279 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1280 	Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1281 
1282 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
1283 
1284 
1285 /*IO Unit Page 10 */
1286 
1287 typedef struct _MPI2_IOUNIT10_FUNCTION {
1288 	U8                      CreditPercent;      /*0x00 */
1289 	U8                      Reserved1;          /*0x01 */
1290 	U16                     Reserved2;          /*0x02 */
1291 } MPI2_IOUNIT10_FUNCTION,
1292 	*PTR_MPI2_IOUNIT10_FUNCTION,
1293 	Mpi2IOUnit10Function_t,
1294 	*pMpi2IOUnit10Function_t;
1295 
1296 /*
1297  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1298  *one and check the value returned for NumFunctions at runtime.
1299  */
1300 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1301 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
1302 #endif
1303 
1304 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1305 	MPI2_CONFIG_PAGE_HEADER Header;                      /*0x00 */
1306 	U8                      NumFunctions;                /*0x04 */
1307 	U8                      Reserved1;                   /*0x05 */
1308 	U16                     Reserved2;                   /*0x06 */
1309 	U32                     Reserved3;                   /*0x08 */
1310 	U32                     Reserved4;                   /*0x0C */
1311 	MPI2_IOUNIT10_FUNCTION
1312 		Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1313 } MPI2_CONFIG_PAGE_IO_UNIT_10,
1314 	*PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1315 	Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1316 
1317 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
1318 
1319 
1320 /* IO Unit Page 11 (for MPI v2.6 and later) */
1321 
1322 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP {
1323 	U8          MaxTargetSpinup;            /* 0x00 */
1324 	U8          SpinupDelay;                /* 0x01 */
1325 	U8          SpinupFlags;                /* 0x02 */
1326 	U8          Reserved1;                  /* 0x03 */
1327 } MPI26_IOUNIT11_SPINUP_GROUP,
1328 	*PTR_MPI26_IOUNIT11_SPINUP_GROUP,
1329 	Mpi26IOUnit11SpinupGroup_t,
1330 	*pMpi26IOUnit11SpinupGroup_t;
1331 
1332 /* defines for IO Unit Page 11 SpinupFlags */
1333 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG          (0x01)
1334 
1335 
1336 /*
1337  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1338  * four and check the value returned for NumPhys at runtime.
1339  */
1340 #ifndef MPI26_IOUNITPAGE11_PHY_MAX
1341 #define MPI26_IOUNITPAGE11_PHY_MAX        (4)
1342 #endif
1343 
1344 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 {
1345 	MPI2_CONFIG_PAGE_HEADER       Header;			       /*0x00 */
1346 	U32                           Reserved1;                      /*0x04 */
1347 	MPI26_IOUNIT11_SPINUP_GROUP   SpinupGroupParameters[4];       /*0x08 */
1348 	U32                           Reserved2;                      /*0x18 */
1349 	U32                           Reserved3;                      /*0x1C */
1350 	U32                           Reserved4;                      /*0x20 */
1351 	U8                            BootDeviceWaitTime;             /*0x24 */
1352 	U8                            Reserved5;                      /*0x25 */
1353 	U16                           Reserved6;                      /*0x26 */
1354 	U8                            NumPhys;                        /*0x28 */
1355 	U8                            PEInitialSpinupDelay;           /*0x29 */
1356 	U8                            PEReplyDelay;                   /*0x2A */
1357 	U8                            Flags;                          /*0x2B */
1358 	U8			      PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */
1359 } MPI26_CONFIG_PAGE_IO_UNIT_11,
1360 	*PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
1361 	Mpi26IOUnitPage11_t,
1362 	*pMpi26IOUnitPage11_t;
1363 
1364 #define MPI26_IOUNITPAGE11_PAGEVERSION                  (0x00)
1365 
1366 /* defines for Flags field */
1367 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE        (0x01)
1368 
1369 /* defines for PHY field */
1370 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK        (0x03)
1371 
1372 
1373 
1374 
1375 
1376 
1377 /****************************************************************************
1378 *  IOC Config Pages
1379 ****************************************************************************/
1380 
1381 /*IOC Page 0 */
1382 
1383 typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1384 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1385 	U32                     Reserved1;                  /*0x04 */
1386 	U32                     Reserved2;                  /*0x08 */
1387 	U16                     VendorID;                   /*0x0C */
1388 	U16                     DeviceID;                   /*0x0E */
1389 	U8                      RevisionID;                 /*0x10 */
1390 	U8                      Reserved3;                  /*0x11 */
1391 	U16                     Reserved4;                  /*0x12 */
1392 	U32                     ClassCode;                  /*0x14 */
1393 	U16                     SubsystemVendorID;          /*0x18 */
1394 	U16                     SubsystemID;                /*0x1A */
1395 } MPI2_CONFIG_PAGE_IOC_0,
1396 	*PTR_MPI2_CONFIG_PAGE_IOC_0,
1397 	Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1398 
1399 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
1400 
1401 
1402 /*IOC Page 1 */
1403 
1404 typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1405 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1406 	U32                     Flags;                      /*0x04 */
1407 	U32                     CoalescingTimeout;          /*0x08 */
1408 	U8                      CoalescingDepth;            /*0x0C */
1409 	U8                      PCISlotNum;                 /*0x0D */
1410 	U8                      PCIBusNum;                  /*0x0E */
1411 	U8                      PCIDomainSegment;           /*0x0F */
1412 	U32                     Reserved1;                  /*0x10 */
1413 	U32                     ProductSpecific;            /* 0x14 */
1414 } MPI2_CONFIG_PAGE_IOC_1,
1415 	*PTR_MPI2_CONFIG_PAGE_IOC_1,
1416 	Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1417 
1418 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
1419 
1420 /*defines for IOC Page 1 Flags field */
1421 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
1422 
1423 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
1424 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
1425 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
1426 
1427 /*IOC Page 6 */
1428 
1429 typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1430 	MPI2_CONFIG_PAGE_HEADER Header;         /*0x00 */
1431 	U32
1432 		CapabilitiesFlags;              /*0x04 */
1433 	U8                      MaxDrivesRAID0; /*0x08 */
1434 	U8                      MaxDrivesRAID1; /*0x09 */
1435 	U8
1436 		 MaxDrivesRAID1E;                /*0x0A */
1437 	U8
1438 		 MaxDrivesRAID10;		/*0x0B */
1439 	U8                      MinDrivesRAID0; /*0x0C */
1440 	U8                      MinDrivesRAID1; /*0x0D */
1441 	U8
1442 		 MinDrivesRAID1E;                /*0x0E */
1443 	U8
1444 		 MinDrivesRAID10;                /*0x0F */
1445 	U32                     Reserved1;      /*0x10 */
1446 	U8
1447 		 MaxGlobalHotSpares;             /*0x14 */
1448 	U8                      MaxPhysDisks;   /*0x15 */
1449 	U8                      MaxVolumes;     /*0x16 */
1450 	U8                      MaxConfigs;     /*0x17 */
1451 	U8                      MaxOCEDisks;    /*0x18 */
1452 	U8                      Reserved2;      /*0x19 */
1453 	U16                     Reserved3;      /*0x1A */
1454 	U32
1455 		SupportedStripeSizeMapRAID0;    /*0x1C */
1456 	U32
1457 		SupportedStripeSizeMapRAID1E;   /*0x20 */
1458 	U32
1459 		SupportedStripeSizeMapRAID10;   /*0x24 */
1460 	U32                     Reserved4;      /*0x28 */
1461 	U32                     Reserved5;      /*0x2C */
1462 	U16
1463 		DefaultMetadataSize;            /*0x30 */
1464 	U16                     Reserved6;      /*0x32 */
1465 	U16
1466 		MaxBadBlockTableEntries;        /*0x34 */
1467 	U16                     Reserved7;      /*0x36 */
1468 	U32
1469 		IRNvsramVersion;                /*0x38 */
1470 } MPI2_CONFIG_PAGE_IOC_6,
1471 	*PTR_MPI2_CONFIG_PAGE_IOC_6,
1472 	Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1473 
1474 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
1475 
1476 /*defines for IOC Page 6 CapabilitiesFlags */
1477 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
1478 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
1479 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
1480 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
1481 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
1482 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
1483 
1484 
1485 /*IOC Page 7 */
1486 
1487 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
1488 
1489 typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1490 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1491 	U32                     Reserved1;                  /*0x04 */
1492 	U32
1493 		EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1494 	U16                     SASBroadcastPrimitiveMasks; /*0x18 */
1495 	U16                     SASNotifyPrimitiveMasks;    /*0x1A */
1496 	U32                     Reserved3;                  /*0x1C */
1497 } MPI2_CONFIG_PAGE_IOC_7,
1498 	*PTR_MPI2_CONFIG_PAGE_IOC_7,
1499 	Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1500 
1501 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
1502 
1503 
1504 /*IOC Page 8 */
1505 
1506 typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1507 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1508 	U8                      NumDevsPerEnclosure;        /*0x04 */
1509 	U8                      Reserved1;                  /*0x05 */
1510 	U16                     Reserved2;                  /*0x06 */
1511 	U16                     MaxPersistentEntries;       /*0x08 */
1512 	U16                     MaxNumPhysicalMappedIDs;    /*0x0A */
1513 	U16                     Flags;                      /*0x0C */
1514 	U16                     Reserved3;                  /*0x0E */
1515 	U16                     IRVolumeMappingFlags;       /*0x10 */
1516 	U16                     Reserved4;                  /*0x12 */
1517 	U32                     Reserved5;                  /*0x14 */
1518 } MPI2_CONFIG_PAGE_IOC_8,
1519 	*PTR_MPI2_CONFIG_PAGE_IOC_8,
1520 	Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1521 
1522 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
1523 
1524 /*defines for IOC Page 8 Flags field */
1525 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
1526 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
1527 
1528 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
1529 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
1530 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
1531 
1532 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
1533 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
1534 
1535 /*defines for IOC Page 8 IRVolumeMappingFlags */
1536 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
1537 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
1538 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
1539 
1540 
1541 /****************************************************************************
1542 *  BIOS Config Pages
1543 ****************************************************************************/
1544 
1545 /*BIOS Page 1 */
1546 
1547 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1548 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1549 	U32                     BiosOptions;                /*0x04 */
1550 	U32                     IOCSettings;                /*0x08 */
1551 	U8                      SSUTimeout;                 /*0x0C */
1552 	U8                      MaxEnclosureLevel;          /*0x0D */
1553 	U16                     Reserved2;                  /*0x0E */
1554 	U32                     DeviceSettings;             /*0x10 */
1555 	U16                     NumberOfDevices;            /*0x14 */
1556 	U16                     UEFIVersion;                /*0x16 */
1557 	U16                     IOTimeoutBlockDevicesNonRM; /*0x18 */
1558 	U16                     IOTimeoutSequential;        /*0x1A */
1559 	U16                     IOTimeoutOther;             /*0x1C */
1560 	U16                     IOTimeoutBlockDevicesRM;    /*0x1E */
1561 } MPI2_CONFIG_PAGE_BIOS_1,
1562 	*PTR_MPI2_CONFIG_PAGE_BIOS_1,
1563 	Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1564 
1565 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x07)
1566 
1567 /*values for BIOS Page 1 BiosOptions field */
1568 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE    (0x00008000)
1569 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG                  (0x00004000)
1570 
1571 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
1572 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL                        (0x00000000)
1573 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE                   (0x00000800)
1574 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID                        (0x00001000)
1575 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS                        (0x00001800)
1576 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY                        (0x00002000)
1577 
1578 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS		(0x00000400)
1579 
1580 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD	(0x00000300)
1581 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD	(0x00000000)
1582 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD	(0x00000100)
1583 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD	(0x00000200)
1584 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD	(0x00000300)
1585 
1586 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                  (0x000000F0)
1587 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                   (0x00000000)
1588 
1589 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION   (0x00000006)
1590 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII              (0x00000000)
1591 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII             (0x00000002)
1592 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII       (0x00000004)
1593 
1594 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                 (0x00000001)
1595 
1596 /*values for BIOS Page 1 IOCSettings field */
1597 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
1598 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
1599 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
1600 
1601 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
1602 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
1603 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
1604 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
1605 
1606 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
1607 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
1608 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
1609 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
1610 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
1611 
1612 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
1613 
1614 /*values for BIOS Page 1 DeviceSettings field */
1615 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
1616 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
1617 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
1618 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
1619 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
1620 
1621 /*defines for BIOS Page 1 UEFIVersion field */
1622 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
1623 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
1624 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
1625 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
1626 
1627 
1628 
1629 /*BIOS Page 2 */
1630 
1631 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1632 	U32         Reserved1;                              /*0x00 */
1633 	U32         Reserved2;                              /*0x04 */
1634 	U32         Reserved3;                              /*0x08 */
1635 	U32         Reserved4;                              /*0x0C */
1636 	U32         Reserved5;                              /*0x10 */
1637 	U32         Reserved6;                              /*0x14 */
1638 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1639 	*PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1640 	Mpi2BootDeviceAdapterOrder_t,
1641 	*pMpi2BootDeviceAdapterOrder_t;
1642 
1643 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1644 	U64         SASAddress;                             /*0x00 */
1645 	U8          LUN[8];                                 /*0x08 */
1646 	U32         Reserved1;                              /*0x10 */
1647 	U32         Reserved2;                              /*0x14 */
1648 } MPI2_BOOT_DEVICE_SAS_WWID,
1649 	*PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1650 	Mpi2BootDeviceSasWwid_t,
1651 	*pMpi2BootDeviceSasWwid_t;
1652 
1653 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1654 	U64         EnclosureLogicalID;                     /*0x00 */
1655 	U32         Reserved1;                              /*0x08 */
1656 	U32         Reserved2;                              /*0x0C */
1657 	U16         SlotNumber;                             /*0x10 */
1658 	U16         Reserved3;                              /*0x12 */
1659 	U32         Reserved4;                              /*0x14 */
1660 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1661 	*PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1662 	Mpi2BootDeviceEnclosureSlot_t,
1663 	*pMpi2BootDeviceEnclosureSlot_t;
1664 
1665 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1666 	U64         DeviceName;                             /*0x00 */
1667 	U8          LUN[8];                                 /*0x08 */
1668 	U32         Reserved1;                              /*0x10 */
1669 	U32         Reserved2;                              /*0x14 */
1670 } MPI2_BOOT_DEVICE_DEVICE_NAME,
1671 	*PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1672 	Mpi2BootDeviceDeviceName_t,
1673 	*pMpi2BootDeviceDeviceName_t;
1674 
1675 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1676 	MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
1677 	MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
1678 	MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1679 	MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
1680 } MPI2_BIOSPAGE2_BOOT_DEVICE,
1681 	*PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1682 	Mpi2BiosPage2BootDevice_t,
1683 	*pMpi2BiosPage2BootDevice_t;
1684 
1685 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1686 	MPI2_CONFIG_PAGE_HEADER     Header;                 /*0x00 */
1687 	U32                         Reserved1;              /*0x04 */
1688 	U32                         Reserved2;              /*0x08 */
1689 	U32                         Reserved3;              /*0x0C */
1690 	U32                         Reserved4;              /*0x10 */
1691 	U32                         Reserved5;              /*0x14 */
1692 	U32                         Reserved6;              /*0x18 */
1693 	U8                          ReqBootDeviceForm;      /*0x1C */
1694 	U8                          Reserved7;              /*0x1D */
1695 	U16                         Reserved8;              /*0x1E */
1696 	MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /*0x20 */
1697 	U8                          ReqAltBootDeviceForm;   /*0x38 */
1698 	U8                          Reserved9;              /*0x39 */
1699 	U16                         Reserved10;             /*0x3A */
1700 	MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /*0x3C */
1701 	U8                          CurrentBootDeviceForm;  /*0x58 */
1702 	U8                          Reserved11;             /*0x59 */
1703 	U16                         Reserved12;             /*0x5A */
1704 	MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /*0x58 */
1705 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1706 	Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1707 
1708 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
1709 
1710 /*values for BIOS Page 2 BootDeviceForm fields */
1711 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
1712 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
1713 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
1714 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
1715 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
1716 
1717 
1718 /*BIOS Page 3 */
1719 
1720 #define MPI2_BIOSPAGE3_NUM_ADAPTER      (4)
1721 
1722 typedef struct _MPI2_ADAPTER_INFO {
1723 	U8      PciBusNumber;                        /*0x00 */
1724 	U8      PciDeviceAndFunctionNumber;          /*0x01 */
1725 	U16     AdapterFlags;                        /*0x02 */
1726 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1727 	Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1728 
1729 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
1730 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
1731 
1732 typedef struct _MPI2_ADAPTER_ORDER_AUX {
1733 	U64     WWID;					/* 0x00 */
1734 	U32     Reserved1;				/* 0x08 */
1735 	U32     Reserved2;				/* 0x0C */
1736 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX,
1737 	Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t;
1738 
1739 
1740 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1741 	MPI2_CONFIG_PAGE_HEADER Header;              /*0x00 */
1742 	U32                     GlobalFlags;         /*0x04 */
1743 	U32                     BiosVersion;         /*0x08 */
1744 	MPI2_ADAPTER_INFO       AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER];
1745 	U32                     Reserved1;           /*0x1C */
1746 	MPI2_ADAPTER_ORDER_AUX  AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER];
1747 } MPI2_CONFIG_PAGE_BIOS_3,
1748 	*PTR_MPI2_CONFIG_PAGE_BIOS_3,
1749 	Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1750 
1751 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x01)
1752 
1753 /*values for BIOS Page 3 GlobalFlags */
1754 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
1755 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
1756 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
1757 
1758 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
1759 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
1760 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
1761 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
1762 
1763 
1764 /*BIOS Page 4 */
1765 
1766 /*
1767  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1768  *one and check the value returned for NumPhys at runtime.
1769  */
1770 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1771 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
1772 #endif
1773 
1774 typedef struct _MPI2_BIOS4_ENTRY {
1775 	U64                     ReassignmentWWID;       /*0x00 */
1776 	U64                     ReassignmentDeviceName; /*0x08 */
1777 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1778 	Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1779 
1780 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1781 	MPI2_CONFIG_PAGE_HEADER Header;             /*0x00 */
1782 	U8                      NumPhys;            /*0x04 */
1783 	U8                      Reserved1;          /*0x05 */
1784 	U16                     Reserved2;          /*0x06 */
1785 	MPI2_BIOS4_ENTRY
1786 		Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /*0x08 */
1787 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1788 	Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1789 
1790 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
1791 
1792 
1793 /****************************************************************************
1794 *  RAID Volume Config Pages
1795 ****************************************************************************/
1796 
1797 /*RAID Volume Page 0 */
1798 
1799 typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1800 	U8                      RAIDSetNum;        /*0x00 */
1801 	U8                      PhysDiskMap;       /*0x01 */
1802 	U8                      PhysDiskNum;       /*0x02 */
1803 	U8                      Reserved;          /*0x03 */
1804 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1805 	Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1806 
1807 /*defines for the PhysDiskMap field */
1808 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
1809 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
1810 
1811 typedef struct _MPI2_RAIDVOL0_SETTINGS {
1812 	U16                     Settings;          /*0x00 */
1813 	U8                      HotSparePool;      /*0x01 */
1814 	U8                      Reserved;          /*0x02 */
1815 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1816 	Mpi2RaidVol0Settings_t,
1817 	*pMpi2RaidVol0Settings_t;
1818 
1819 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1820 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
1821 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
1822 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
1823 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
1824 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
1825 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
1826 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
1827 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
1828 
1829 /*RAID Volume Page 0 VolumeSettings defines */
1830 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
1831 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1832 
1833 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
1834 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
1835 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
1836 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
1837 
1838 /*
1839  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1840  *one and check the value returned for NumPhysDisks at runtime.
1841  */
1842 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1843 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
1844 #endif
1845 
1846 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1847 	MPI2_CONFIG_PAGE_HEADER Header;            /*0x00 */
1848 	U16                     DevHandle;         /*0x04 */
1849 	U8                      VolumeState;       /*0x06 */
1850 	U8                      VolumeType;        /*0x07 */
1851 	U32                     VolumeStatusFlags; /*0x08 */
1852 	MPI2_RAIDVOL0_SETTINGS  VolumeSettings;    /*0x0C */
1853 	U64                     MaxLBA;            /*0x10 */
1854 	U32                     StripeSize;        /*0x18 */
1855 	U16                     BlockSize;         /*0x1C */
1856 	U16                     Reserved1;         /*0x1E */
1857 	U8                      SupportedPhysDisks;/*0x20 */
1858 	U8                      ResyncRate;        /*0x21 */
1859 	U16                     DataScrubDuration; /*0x22 */
1860 	U8                      NumPhysDisks;      /*0x24 */
1861 	U8                      Reserved2;         /*0x25 */
1862 	U8                      Reserved3;         /*0x26 */
1863 	U8                      InactiveStatus;    /*0x27 */
1864 	MPI2_RAIDVOL0_PHYS_DISK
1865 	PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1866 } MPI2_CONFIG_PAGE_RAID_VOL_0,
1867 	*PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1868 	Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1869 
1870 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
1871 
1872 /*values for RAID VolumeState */
1873 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
1874 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
1875 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
1876 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
1877 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
1878 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
1879 
1880 /*values for RAID VolumeType */
1881 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
1882 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
1883 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
1884 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
1885 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
1886 
1887 /*values for RAID Volume Page 0 VolumeStatusFlags field */
1888 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
1889 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
1890 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
1891 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
1892 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
1893 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
1894 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
1895 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
1896 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
1897 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
1898 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
1899 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
1900 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
1901 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
1902 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
1903 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
1904 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
1905 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
1906 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
1907 
1908 /*values for RAID Volume Page 0 SupportedPhysDisks field */
1909 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
1910 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
1911 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
1912 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
1913 
1914 /*values for RAID Volume Page 0 InactiveStatus field */
1915 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
1916 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
1917 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
1918 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
1919 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
1920 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
1921 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
1922 
1923 
1924 /*RAID Volume Page 1 */
1925 
1926 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1927 	MPI2_CONFIG_PAGE_HEADER Header;                     /*0x00 */
1928 	U16                     DevHandle;                  /*0x04 */
1929 	U16                     Reserved0;                  /*0x06 */
1930 	U8                      GUID[24];                   /*0x08 */
1931 	U8                      Name[16];                   /*0x20 */
1932 	U64                     WWID;                       /*0x30 */
1933 	U32                     Reserved1;                  /*0x38 */
1934 	U32                     Reserved2;                  /*0x3C */
1935 } MPI2_CONFIG_PAGE_RAID_VOL_1,
1936 	*PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1937 	Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1938 
1939 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
1940 
1941 
1942 /****************************************************************************
1943 *  RAID Physical Disk Config Pages
1944 ****************************************************************************/
1945 
1946 /*RAID Physical Disk Page 0 */
1947 
1948 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1949 	U16                     Reserved1;                  /*0x00 */
1950 	U8                      HotSparePool;               /*0x02 */
1951 	U8                      Reserved2;                  /*0x03 */
1952 } MPI2_RAIDPHYSDISK0_SETTINGS,
1953 	*PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1954 	Mpi2RaidPhysDisk0Settings_t,
1955 	*pMpi2RaidPhysDisk0Settings_t;
1956 
1957 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1958 
1959 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1960 	U8                      VendorID[8];                /*0x00 */
1961 	U8                      ProductID[16];              /*0x08 */
1962 	U8                      ProductRevLevel[4];         /*0x18 */
1963 	U8                      SerialNum[32];              /*0x1C */
1964 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1965 	*PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1966 	Mpi2RaidPhysDisk0InquiryData_t,
1967 	*pMpi2RaidPhysDisk0InquiryData_t;
1968 
1969 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1970 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
1971 	U16                             DevHandle;          /*0x04 */
1972 	U8                              Reserved1;          /*0x06 */
1973 	U8                              PhysDiskNum;        /*0x07 */
1974 	MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;   /*0x08 */
1975 	U32                             Reserved2;          /*0x0C */
1976 	MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;        /*0x10 */
1977 	U32                             Reserved3;          /*0x4C */
1978 	U8                              PhysDiskState;      /*0x50 */
1979 	U8                              OfflineReason;      /*0x51 */
1980 	U8                              IncompatibleReason; /*0x52 */
1981 	U8                              PhysDiskAttributes; /*0x53 */
1982 	U32                             PhysDiskStatusFlags;/*0x54 */
1983 	U64                             DeviceMaxLBA;       /*0x58 */
1984 	U64                             HostMaxLBA;         /*0x60 */
1985 	U64                             CoercedMaxLBA;      /*0x68 */
1986 	U16                             BlockSize;          /*0x70 */
1987 	U16                             Reserved5;          /*0x72 */
1988 	U32                             Reserved6;          /*0x74 */
1989 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1990 	*PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1991 	Mpi2RaidPhysDiskPage0_t,
1992 	*pMpi2RaidPhysDiskPage0_t;
1993 
1994 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
1995 
1996 /*PhysDiskState defines */
1997 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
1998 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
1999 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
2000 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
2001 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
2002 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
2003 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
2004 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
2005 
2006 /*OfflineReason defines */
2007 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
2008 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
2009 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
2010 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
2011 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
2012 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
2013 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
2014 
2015 /*IncompatibleReason defines */
2016 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
2017 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
2018 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
2019 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
2020 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
2021 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
2022 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
2023 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
2024 
2025 /*PhysDiskAttributes defines */
2026 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
2027 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
2028 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
2029 
2030 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
2031 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
2032 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
2033 
2034 /*PhysDiskStatusFlags defines */
2035 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
2036 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
2037 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
2038 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
2039 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
2040 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
2041 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
2042 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
2043 
2044 
2045 /*RAID Physical Disk Page 1 */
2046 
2047 /*
2048  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2049  *one and check the value returned for NumPhysDiskPaths at runtime.
2050  */
2051 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
2052 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
2053 #endif
2054 
2055 typedef struct _MPI2_RAIDPHYSDISK1_PATH {
2056 	U16             DevHandle;          /*0x00 */
2057 	U16             Reserved1;          /*0x02 */
2058 	U64             WWID;               /*0x04 */
2059 	U64             OwnerWWID;          /*0x0C */
2060 	U8              OwnerIdentifier;    /*0x14 */
2061 	U8              Reserved2;          /*0x15 */
2062 	U16             Flags;              /*0x16 */
2063 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
2064 	Mpi2RaidPhysDisk1Path_t,
2065 	*pMpi2RaidPhysDisk1Path_t;
2066 
2067 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
2068 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
2069 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
2070 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
2071 
2072 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
2073 	MPI2_CONFIG_PAGE_HEADER         Header;             /*0x00 */
2074 	U8                              NumPhysDiskPaths;   /*0x04 */
2075 	U8                              PhysDiskNum;        /*0x05 */
2076 	U16                             Reserved1;          /*0x06 */
2077 	U32                             Reserved2;          /*0x08 */
2078 	MPI2_RAIDPHYSDISK1_PATH
2079 		PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
2080 } MPI2_CONFIG_PAGE_RD_PDISK_1,
2081 	*PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
2082 	Mpi2RaidPhysDiskPage1_t,
2083 	*pMpi2RaidPhysDiskPage1_t;
2084 
2085 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
2086 
2087 
2088 /****************************************************************************
2089 *  values for fields used by several types of SAS Config Pages
2090 ****************************************************************************/
2091 
2092 /*values for NegotiatedLinkRates fields */
2093 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
2094 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
2095 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
2096 /*link rates used for Negotiated Physical and Logical Link Rate */
2097 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
2098 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
2099 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
2100 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
2101 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
2102 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
2103 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
2104 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
2105 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
2106 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
2107 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
2108 #define MPI26_SAS_NEG_LINK_RATE_22_5                    (0x0C)
2109 
2110 
2111 /*values for AttachedPhyInfo fields */
2112 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
2113 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
2114 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
2115 
2116 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
2117 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
2118 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
2119 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
2120 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
2121 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
2122 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
2123 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
2124 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
2125 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
2126 
2127 
2128 /*values for PhyInfo fields */
2129 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
2130 
2131 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
2132 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
2133 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
2134 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
2135 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
2136 
2137 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
2138 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
2139 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
2140 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
2141 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
2142 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
2143 
2144 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
2145 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
2146 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
2147 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
2148 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
2149 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
2150 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
2151 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
2152 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
2153 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
2154 
2155 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
2156 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
2157 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
2158 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
2159 
2160 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
2161 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
2162 
2163 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
2164 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
2165 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
2166 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
2167 
2168 
2169 /*values for SAS ProgrammedLinkRate fields */
2170 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
2171 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
2172 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
2173 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
2174 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
2175 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
2176 #define MPI26_SAS_PRATE_MAX_RATE_22_5                   (0xC0)
2177 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
2178 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
2179 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
2180 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
2181 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
2182 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
2183 #define MPI26_SAS_PRATE_MIN_RATE_22_5                   (0x0C)
2184 
2185 
2186 /*values for SAS HwLinkRate fields */
2187 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
2188 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
2189 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
2190 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
2191 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
2192 #define MPI26_SAS_HWRATE_MAX_RATE_22_5                  (0xC0)
2193 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
2194 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
2195 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
2196 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
2197 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
2198 #define MPI26_SAS_HWRATE_MIN_RATE_22_5                  (0x0C)
2199 
2200 
2201 
2202 /****************************************************************************
2203 *  SAS IO Unit Config Pages
2204 ****************************************************************************/
2205 
2206 /*SAS IO Unit Page 0 */
2207 
2208 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
2209 	U8          Port;                   /*0x00 */
2210 	U8          PortFlags;              /*0x01 */
2211 	U8          PhyFlags;               /*0x02 */
2212 	U8          NegotiatedLinkRate;     /*0x03 */
2213 	U32         ControllerPhyDeviceInfo;/*0x04 */
2214 	U16         AttachedDevHandle;      /*0x08 */
2215 	U16         ControllerDevHandle;    /*0x0A */
2216 	U32         DiscoveryStatus;        /*0x0C */
2217 	U32         Reserved;               /*0x10 */
2218 } MPI2_SAS_IO_UNIT0_PHY_DATA,
2219 	*PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
2220 	Mpi2SasIOUnit0PhyData_t,
2221 	*pMpi2SasIOUnit0PhyData_t;
2222 
2223 /*
2224  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2225  *one and check the value returned for NumPhys at runtime.
2226  */
2227 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
2228 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
2229 #endif
2230 
2231 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
2232 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2233 	U32                                 Reserved1;/*0x08 */
2234 	U8                                  NumPhys;  /*0x0C */
2235 	U8                                  Reserved2;/*0x0D */
2236 	U16                                 Reserved3;/*0x0E */
2237 	MPI2_SAS_IO_UNIT0_PHY_DATA
2238 		PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];    /*0x10 */
2239 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
2240 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
2241 	Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
2242 
2243 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
2244 
2245 /*values for SAS IO Unit Page 0 PortFlags */
2246 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
2247 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
2248 
2249 /*values for SAS IO Unit Page 0 PhyFlags */
2250 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT       (0x40)
2251 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT       (0x20)
2252 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
2253 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
2254 
2255 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2256 
2257 /*see mpi2_sas.h for values for
2258  *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2259 
2260 /*values for SAS IO Unit Page 0 DiscoveryStatus */
2261 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
2262 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
2263 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
2264 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
2265 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
2266 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
2267 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
2268 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
2269 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
2270 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
2271 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
2272 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
2273 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
2274 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
2275 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
2276 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
2277 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
2278 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
2279 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
2280 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
2281 
2282 
2283 /*SAS IO Unit Page 1 */
2284 
2285 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
2286 	U8          Port;                       /*0x00 */
2287 	U8          PortFlags;                  /*0x01 */
2288 	U8          PhyFlags;                   /*0x02 */
2289 	U8          MaxMinLinkRate;             /*0x03 */
2290 	U32         ControllerPhyDeviceInfo;    /*0x04 */
2291 	U16         MaxTargetPortConnectTime;   /*0x08 */
2292 	U16         Reserved1;                  /*0x0A */
2293 } MPI2_SAS_IO_UNIT1_PHY_DATA,
2294 	*PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
2295 	Mpi2SasIOUnit1PhyData_t,
2296 	*pMpi2SasIOUnit1PhyData_t;
2297 
2298 /*
2299  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2300  *one and check the value returned for NumPhys at runtime.
2301  */
2302 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2303 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
2304 #endif
2305 
2306 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2307 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
2308 	U16
2309 		ControlFlags;                       /*0x08 */
2310 	U16
2311 		SASNarrowMaxQueueDepth;             /*0x0A */
2312 	U16
2313 		AdditionalControlFlags;             /*0x0C */
2314 	U16
2315 		SASWideMaxQueueDepth;               /*0x0E */
2316 	U8
2317 		NumPhys;                            /*0x10 */
2318 	U8
2319 		SATAMaxQDepth;                      /*0x11 */
2320 	U8
2321 		ReportDeviceMissingDelay;           /*0x12 */
2322 	U8
2323 		IODeviceMissingDelay;               /*0x13 */
2324 	MPI2_SAS_IO_UNIT1_PHY_DATA
2325 		PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /*0x14 */
2326 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
2327 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2328 	Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2329 
2330 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
2331 
2332 /*values for SAS IO Unit Page 1 ControlFlags */
2333 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
2334 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
2335 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000)
2336 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
2337 
2338 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
2339 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
2340 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
2341 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
2342 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
2343 
2344 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
2345 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
2346 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
2347 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
2348 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
2349 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
2350 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
2351 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001)
2352 
2353 /*values for SAS IO Unit Page 1 AdditionalControlFlags */
2354 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
2355 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
2356 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
2357 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
2358 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
2359 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
2360 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
2361 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
2362 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
2363 
2364 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2365 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
2366 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
2367 
2368 /*values for SAS IO Unit Page 1 PortFlags */
2369 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
2370 
2371 /*values for SAS IO Unit Page 1 PhyFlags */
2372 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
2373 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
2374 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
2375 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
2376 
2377 /*values for SAS IO Unit Page 1 MaxMinLinkRate */
2378 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
2379 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
2380 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
2381 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
2382 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
2383 #define MPI26_SASIOUNIT1_MAX_RATE_22_5                              (0xC0)
2384 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
2385 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
2386 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
2387 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
2388 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
2389 #define MPI26_SASIOUNIT1_MIN_RATE_22_5                              (0x0C)
2390 
2391 /*see mpi2_sas.h for values for
2392  *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2393 
2394 
2395 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
2396 
2397 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2398 	U8          MaxTargetSpinup;            /*0x00 */
2399 	U8          SpinupDelay;                /*0x01 */
2400 	U8          SpinupFlags;                /*0x02 */
2401 	U8          Reserved1;                  /*0x03 */
2402 } MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2403 	*PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2404 	Mpi2SasIOUnit4SpinupGroup_t,
2405 	*pMpi2SasIOUnit4SpinupGroup_t;
2406 /*defines for SAS IO Unit Page 4 SpinupFlags */
2407 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
2408 
2409 
2410 /*
2411  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2412  *one and check the value returned for NumPhys at runtime.
2413  */
2414 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2415 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
2416 #endif
2417 
2418 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2419 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;/*0x00 */
2420 	MPI2_SAS_IOUNIT4_SPINUP_GROUP
2421 		SpinupGroupParameters[4];       /*0x08 */
2422 	U32
2423 		Reserved1;                      /*0x18 */
2424 	U32
2425 		Reserved2;                      /*0x1C */
2426 	U32
2427 		Reserved3;                      /*0x20 */
2428 	U8
2429 		BootDeviceWaitTime;             /*0x24 */
2430 	U8
2431 		SATADeviceWaitTime;		/*0x25 */
2432 	U16
2433 		Reserved5;                      /*0x26 */
2434 	U8
2435 		NumPhys;                        /*0x28 */
2436 	U8
2437 		PEInitialSpinupDelay;           /*0x29 */
2438 	U8
2439 		PEReplyDelay;                   /*0x2A */
2440 	U8
2441 		Flags;                          /*0x2B */
2442 	U8
2443 		PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /*0x2C */
2444 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2445 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2446 	Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2447 
2448 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
2449 
2450 /*defines for Flags field */
2451 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
2452 
2453 /*defines for PHY field */
2454 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
2455 
2456 
2457 /*SAS IO Unit Page 5 */
2458 
2459 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2460 	U8          ControlFlags;               /*0x00 */
2461 	U8          PortWidthModGroup;          /*0x01 */
2462 	U16         InactivityTimerExponent;    /*0x02 */
2463 	U8          SATAPartialTimeout;         /*0x04 */
2464 	U8          Reserved2;                  /*0x05 */
2465 	U8          SATASlumberTimeout;         /*0x06 */
2466 	U8          Reserved3;                  /*0x07 */
2467 	U8          SASPartialTimeout;          /*0x08 */
2468 	U8          Reserved4;                  /*0x09 */
2469 	U8          SASSlumberTimeout;          /*0x0A */
2470 	U8          Reserved5;                  /*0x0B */
2471 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2472 	*PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2473 	Mpi2SasIOUnit5PhyPmSettings_t,
2474 	*pMpi2SasIOUnit5PhyPmSettings_t;
2475 
2476 /*defines for ControlFlags field */
2477 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
2478 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
2479 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
2480 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
2481 
2482 /*defines for PortWidthModeGroup field */
2483 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
2484 
2485 /*defines for InactivityTimerExponent field */
2486 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
2487 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
2488 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
2489 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
2490 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
2491 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
2492 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
2493 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
2494 
2495 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
2496 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
2497 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
2498 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
2499 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
2500 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
2501 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
2502 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
2503 
2504 /*
2505  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2506  *one and check the value returned for NumPhys at runtime.
2507  */
2508 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2509 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
2510 #endif
2511 
2512 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2513 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;   /*0x00 */
2514 	U8                                  NumPhys;  /*0x08 */
2515 	U8                                  Reserved1;/*0x09 */
2516 	U16                                 Reserved2;/*0x0A */
2517 	U32                                 Reserved3;/*0x0C */
2518 	MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2519 	SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2520 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2521 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2522 	Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2523 
2524 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
2525 
2526 
2527 /*SAS IO Unit Page 6 */
2528 
2529 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2530 	U8          CurrentStatus;              /*0x00 */
2531 	U8          CurrentModulation;          /*0x01 */
2532 	U8          CurrentUtilization;         /*0x02 */
2533 	U8          Reserved1;                  /*0x03 */
2534 	U32         Reserved2;                  /*0x04 */
2535 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2536 	*PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2537 	Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2538 	*pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2539 
2540 /*defines for CurrentStatus field */
2541 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
2542 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
2543 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
2544 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
2545 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
2546 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
2547 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
2548 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
2549 
2550 /*defines for CurrentModulation field */
2551 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
2552 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
2553 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
2554 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
2555 
2556 /*
2557  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2558  *one and check the value returned for NumGroups at runtime.
2559  */
2560 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2561 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
2562 #endif
2563 
2564 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2565 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /*0x00 */
2566 	U32                                 Reserved1;              /*0x08 */
2567 	U32                                 Reserved2;              /*0x0C */
2568 	U8                                  NumGroups;              /*0x10 */
2569 	U8                                  Reserved3;              /*0x11 */
2570 	U16                                 Reserved4;              /*0x12 */
2571 	MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2572 	PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2573 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2574 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2575 	Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2576 
2577 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
2578 
2579 
2580 /*SAS IO Unit Page 7 */
2581 
2582 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2583 	U8          Flags;                      /*0x00 */
2584 	U8          Reserved1;                  /*0x01 */
2585 	U16         Reserved2;                  /*0x02 */
2586 	U8          Threshold75Pct;             /*0x04 */
2587 	U8          Threshold50Pct;             /*0x05 */
2588 	U8          Threshold25Pct;             /*0x06 */
2589 	U8          Reserved3;                  /*0x07 */
2590 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2591 	*PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2592 	Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2593 	*pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2594 
2595 /*defines for Flags field */
2596 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
2597 
2598 
2599 /*
2600  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2601  *one and check the value returned for NumGroups at runtime.
2602  */
2603 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2604 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
2605 #endif
2606 
2607 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2608 	MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;             /*0x00 */
2609 	U8                               SamplingInterval;   /*0x08 */
2610 	U8                               WindowLength;       /*0x09 */
2611 	U16                              Reserved1;          /*0x0A */
2612 	U32                              Reserved2;          /*0x0C */
2613 	U32                              Reserved3;          /*0x10 */
2614 	U8                               NumGroups;          /*0x14 */
2615 	U8                               Reserved4;          /*0x15 */
2616 	U16                              Reserved5;          /*0x16 */
2617 	MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2618 	PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2619 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2620 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2621 	Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2622 
2623 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
2624 
2625 
2626 /*SAS IO Unit Page 8 */
2627 
2628 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2629 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2630 		Header;                         /*0x00 */
2631 	U32
2632 		Reserved1;                      /*0x08 */
2633 	U32
2634 		PowerManagementCapabilities;    /*0x0C */
2635 	U8
2636 		TxRxSleepStatus;                /*0x10 */
2637 	U8
2638 		Reserved2;                      /*0x11 */
2639 	U16
2640 		Reserved3;                      /*0x12 */
2641 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2642 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2643 	Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2644 
2645 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
2646 
2647 /*defines for PowerManagementCapabilities field */
2648 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
2649 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
2650 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
2651 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
2652 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
2653 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
2654 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
2655 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
2656 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
2657 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
2658 
2659 /*defines for TxRxSleepStatus field */
2660 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
2661 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
2662 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
2663 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
2664 
2665 
2666 
2667 /*SAS IO Unit Page 16 */
2668 
2669 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2670 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2671 		Header;                             /*0x00 */
2672 	U64
2673 		TimeStamp;                          /*0x08 */
2674 	U32
2675 		Reserved1;                          /*0x10 */
2676 	U32
2677 		Reserved2;                          /*0x14 */
2678 	U32
2679 		FastPathPendedRequests;             /*0x18 */
2680 	U32
2681 		FastPathUnPendedRequests;           /*0x1C */
2682 	U32
2683 		FastPathHostRequestStarts;          /*0x20 */
2684 	U32
2685 		FastPathFirmwareRequestStarts;      /*0x24 */
2686 	U32
2687 		FastPathHostCompletions;            /*0x28 */
2688 	U32
2689 		FastPathFirmwareCompletions;        /*0x2C */
2690 	U32
2691 		NonFastPathRequestStarts;           /*0x30 */
2692 	U32
2693 		NonFastPathHostCompletions;         /*0x30 */
2694 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2695 	*PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2696 	Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2697 
2698 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
2699 
2700 
2701 /****************************************************************************
2702 *  SAS Expander Config Pages
2703 ****************************************************************************/
2704 
2705 /*SAS Expander Page 0 */
2706 
2707 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2708 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2709 		Header;                     /*0x00 */
2710 	U8
2711 		PhysicalPort;               /*0x08 */
2712 	U8
2713 		ReportGenLength;            /*0x09 */
2714 	U16
2715 		EnclosureHandle;            /*0x0A */
2716 	U64
2717 		SASAddress;                 /*0x0C */
2718 	U32
2719 		DiscoveryStatus;            /*0x14 */
2720 	U16
2721 		DevHandle;                  /*0x18 */
2722 	U16
2723 		ParentDevHandle;            /*0x1A */
2724 	U16
2725 		ExpanderChangeCount;        /*0x1C */
2726 	U16
2727 		ExpanderRouteIndexes;       /*0x1E */
2728 	U8
2729 		NumPhys;                    /*0x20 */
2730 	U8
2731 		SASLevel;                   /*0x21 */
2732 	U16
2733 		Flags;                      /*0x22 */
2734 	U16
2735 		STPBusInactivityTimeLimit;  /*0x24 */
2736 	U16
2737 		STPMaxConnectTimeLimit;     /*0x26 */
2738 	U16
2739 		STP_SMP_NexusLossTime;      /*0x28 */
2740 	U16
2741 		MaxNumRoutedSasAddresses;   /*0x2A */
2742 	U64
2743 		ActiveZoneManagerSASAddress;/*0x2C */
2744 	U16
2745 		ZoneLockInactivityLimit;    /*0x34 */
2746 	U16
2747 		Reserved1;                  /*0x36 */
2748 	U8
2749 		TimeToReducedFunc;          /*0x38 */
2750 	U8
2751 		InitialTimeToReducedFunc;   /*0x39 */
2752 	U8
2753 		MaxReducedFuncTime;         /*0x3A */
2754 	U8
2755 		Reserved2;                  /*0x3B */
2756 } MPI2_CONFIG_PAGE_EXPANDER_0,
2757 	*PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2758 	Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2759 
2760 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
2761 
2762 /*values for SAS Expander Page 0 DiscoveryStatus field */
2763 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
2764 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
2765 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
2766 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
2767 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
2768 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2769 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
2770 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
2771 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
2772 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
2773 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
2774 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
2775 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
2776 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
2777 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
2778 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
2779 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
2780 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
2781 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
2782 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
2783 
2784 /*values for SAS Expander Page 0 Flags field */
2785 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
2786 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
2787 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
2788 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
2789 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
2790 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
2791 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
2792 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
2793 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
2794 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
2795 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
2796 
2797 
2798 /*SAS Expander Page 1 */
2799 
2800 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2801 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2802 		Header;                     /*0x00 */
2803 	U8
2804 		PhysicalPort;               /*0x08 */
2805 	U8
2806 		Reserved1;                  /*0x09 */
2807 	U16
2808 		Reserved2;                  /*0x0A */
2809 	U8
2810 		NumPhys;                    /*0x0C */
2811 	U8
2812 		Phy;                        /*0x0D */
2813 	U16
2814 		NumTableEntriesProgrammed;  /*0x0E */
2815 	U8
2816 		ProgrammedLinkRate;         /*0x10 */
2817 	U8
2818 		HwLinkRate;                 /*0x11 */
2819 	U16
2820 		AttachedDevHandle;          /*0x12 */
2821 	U32
2822 		PhyInfo;                    /*0x14 */
2823 	U32
2824 		AttachedDeviceInfo;         /*0x18 */
2825 	U16
2826 		ExpanderDevHandle;          /*0x1C */
2827 	U8
2828 		ChangeCount;                /*0x1E */
2829 	U8
2830 		NegotiatedLinkRate;         /*0x1F */
2831 	U8
2832 		PhyIdentifier;              /*0x20 */
2833 	U8
2834 		AttachedPhyIdentifier;      /*0x21 */
2835 	U8
2836 		Reserved3;                  /*0x22 */
2837 	U8
2838 		DiscoveryInfo;              /*0x23 */
2839 	U32
2840 		AttachedPhyInfo;            /*0x24 */
2841 	U8
2842 		ZoneGroup;                  /*0x28 */
2843 	U8
2844 		SelfConfigStatus;           /*0x29 */
2845 	U16
2846 		Reserved4;                  /*0x2A */
2847 } MPI2_CONFIG_PAGE_EXPANDER_1,
2848 	*PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2849 	Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2850 
2851 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
2852 
2853 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2854 
2855 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2856 
2857 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2858 
2859 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2860  *used for the AttachedDeviceInfo field */
2861 
2862 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2863 
2864 /*values for SAS Expander Page 1 DiscoveryInfo field */
2865 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
2866 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
2867 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
2868 
2869 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2870 
2871 
2872 /****************************************************************************
2873 *  SAS Device Config Pages
2874 ****************************************************************************/
2875 
2876 /*SAS Device Page 0 */
2877 
2878 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2879 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2880 		Header;                 /*0x00 */
2881 	U16
2882 		Slot;                   /*0x08 */
2883 	U16
2884 		EnclosureHandle;        /*0x0A */
2885 	U64
2886 		SASAddress;             /*0x0C */
2887 	U16
2888 		ParentDevHandle;        /*0x14 */
2889 	U8
2890 		PhyNum;                 /*0x16 */
2891 	U8
2892 		AccessStatus;           /*0x17 */
2893 	U16
2894 		DevHandle;              /*0x18 */
2895 	U8
2896 		AttachedPhyIdentifier;  /*0x1A */
2897 	U8
2898 		ZoneGroup;              /*0x1B */
2899 	U32
2900 		DeviceInfo;             /*0x1C */
2901 	U16
2902 		Flags;                  /*0x20 */
2903 	U8
2904 		PhysicalPort;           /*0x22 */
2905 	U8
2906 		MaxPortConnections;     /*0x23 */
2907 	U64
2908 		DeviceName;             /*0x24 */
2909 	U8
2910 		PortGroups;             /*0x2C */
2911 	U8
2912 		DmaGroup;               /*0x2D */
2913 	U8
2914 		ControlGroup;           /*0x2E */
2915 	U8
2916 		EnclosureLevel;		/*0x2F */
2917 	U32
2918 		ConnectorName[4];	/*0x30 */
2919 	U32
2920 		Reserved3;              /*0x34 */
2921 } MPI2_CONFIG_PAGE_SAS_DEV_0,
2922 	*PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2923 	Mpi2SasDevicePage0_t,
2924 	*pMpi2SasDevicePage0_t;
2925 
2926 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
2927 
2928 /*values for SAS Device Page 0 AccessStatus field */
2929 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
2930 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
2931 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
2932 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
2933 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
2934 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
2935 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
2936 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
2937 /*specific values for SATA Init failures */
2938 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
2939 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
2940 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
2941 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
2942 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
2943 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
2944 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
2945 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
2946 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
2947 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
2948 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
2949 
2950 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2951 
2952 /*values for SAS Device Page 0 Flags field */
2953 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
2954 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
2955 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
2956 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
2957 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
2958 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
2959 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
2960 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
2961 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
2962 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
2963 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
2964 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
2965 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
2966 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE              (0x0004)
2967 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
2968 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
2969 
2970 
2971 /*SAS Device Page 1 */
2972 
2973 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2974 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
2975 		Header;                 /*0x00 */
2976 	U32
2977 		Reserved1;              /*0x08 */
2978 	U64
2979 		SASAddress;             /*0x0C */
2980 	U32
2981 		Reserved2;              /*0x14 */
2982 	U16
2983 		DevHandle;              /*0x18 */
2984 	U16
2985 		Reserved3;              /*0x1A */
2986 	U8
2987 		InitialRegDeviceFIS[20];/*0x1C */
2988 } MPI2_CONFIG_PAGE_SAS_DEV_1,
2989 	*PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2990 	Mpi2SasDevicePage1_t,
2991 	*pMpi2SasDevicePage1_t;
2992 
2993 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
2994 
2995 
2996 /****************************************************************************
2997 *  SAS PHY Config Pages
2998 ****************************************************************************/
2999 
3000 /*SAS PHY Page 0 */
3001 
3002 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
3003 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3004 		Header;                 /*0x00 */
3005 	U16
3006 		OwnerDevHandle;         /*0x08 */
3007 	U16
3008 		Reserved1;              /*0x0A */
3009 	U16
3010 		AttachedDevHandle;      /*0x0C */
3011 	U8
3012 		AttachedPhyIdentifier;  /*0x0E */
3013 	U8
3014 		Reserved2;              /*0x0F */
3015 	U32
3016 		AttachedPhyInfo;        /*0x10 */
3017 	U8
3018 		ProgrammedLinkRate;     /*0x14 */
3019 	U8
3020 		HwLinkRate;             /*0x15 */
3021 	U8
3022 		ChangeCount;            /*0x16 */
3023 	U8
3024 		Flags;                  /*0x17 */
3025 	U32
3026 		PhyInfo;                /*0x18 */
3027 	U8
3028 		NegotiatedLinkRate;     /*0x1C */
3029 	U8
3030 		Reserved3;              /*0x1D */
3031 	U16
3032 		Reserved4;              /*0x1E */
3033 } MPI2_CONFIG_PAGE_SAS_PHY_0,
3034 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
3035 	Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
3036 
3037 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
3038 
3039 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
3040 
3041 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
3042 
3043 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
3044 
3045 /*values for SAS PHY Page 0 Flags field */
3046 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
3047 
3048 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
3049 
3050 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3051 
3052 
3053 /*SAS PHY Page 1 */
3054 
3055 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
3056 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3057 		Header;                     /*0x00 */
3058 	U32
3059 		Reserved1;                  /*0x08 */
3060 	U32
3061 		InvalidDwordCount;          /*0x0C */
3062 	U32
3063 		RunningDisparityErrorCount; /*0x10 */
3064 	U32
3065 		LossDwordSynchCount;        /*0x14 */
3066 	U32
3067 		PhyResetProblemCount;       /*0x18 */
3068 } MPI2_CONFIG_PAGE_SAS_PHY_1,
3069 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
3070 	Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
3071 
3072 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
3073 
3074 
3075 /*SAS PHY Page 2 */
3076 
3077 typedef struct _MPI2_SASPHY2_PHY_EVENT {
3078 	U8          PhyEventCode;       /*0x00 */
3079 	U8          Reserved1;          /*0x01 */
3080 	U16         Reserved2;          /*0x02 */
3081 	U32         PhyEventInfo;       /*0x04 */
3082 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
3083 	Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
3084 
3085 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
3086 
3087 
3088 /*
3089  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3090  *one and check the value returned for NumPhyEvents at runtime.
3091  */
3092 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
3093 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
3094 #endif
3095 
3096 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
3097 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3098 		Header;                     /*0x00 */
3099 	U32
3100 		Reserved1;                  /*0x08 */
3101 	U8
3102 		NumPhyEvents;               /*0x0C */
3103 	U8
3104 		Reserved2;                  /*0x0D */
3105 	U16
3106 		Reserved3;                  /*0x0E */
3107 	MPI2_SASPHY2_PHY_EVENT
3108 		PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
3109 } MPI2_CONFIG_PAGE_SAS_PHY_2,
3110 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
3111 	Mpi2SasPhyPage2_t,
3112 	*pMpi2SasPhyPage2_t;
3113 
3114 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
3115 
3116 
3117 /*SAS PHY Page 3 */
3118 
3119 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
3120 	U8          PhyEventCode;       /*0x00 */
3121 	U8          Reserved1;          /*0x01 */
3122 	U16         Reserved2;          /*0x02 */
3123 	U8          CounterType;        /*0x04 */
3124 	U8          ThresholdWindow;    /*0x05 */
3125 	U8          TimeUnits;          /*0x06 */
3126 	U8          Reserved3;          /*0x07 */
3127 	U32         EventThreshold;     /*0x08 */
3128 	U16         ThresholdFlags;     /*0x0C */
3129 	U16         Reserved4;          /*0x0E */
3130 } MPI2_SASPHY3_PHY_EVENT_CONFIG,
3131 	*PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
3132 	Mpi2SasPhy3PhyEventConfig_t,
3133 	*pMpi2SasPhy3PhyEventConfig_t;
3134 
3135 /*values for PhyEventCode field */
3136 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
3137 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
3138 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
3139 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
3140 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
3141 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
3142 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
3143 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
3144 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
3145 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
3146 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
3147 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
3148 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
3149 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
3150 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
3151 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
3152 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
3153 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
3154 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
3155 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
3156 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
3157 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
3158 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
3159 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
3160 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
3161 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
3162 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
3163 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
3164 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
3165 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
3166 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
3167 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
3168 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
3169 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
3170 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
3171 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
3172 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
3173 
3174 /*Following codes are product specific and in MPI v2.6 and later */
3175 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME		    (0xD3)
3176 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xD4)
3177 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME	            (0xD5)
3178 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT	    (0xD6)
3179 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START	            (0xD7)
3180 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT	    (0xD8)
3181 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN	    (0xD9)
3182 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE	    (0xDA)
3183 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE	    (0xDB)
3184 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE	    (0xDC)
3185 
3186 
3187 /*values for the CounterType field */
3188 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
3189 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
3190 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
3191 
3192 /*values for the TimeUnits field */
3193 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
3194 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
3195 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
3196 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
3197 
3198 /*values for the ThresholdFlags field */
3199 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
3200 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
3201 
3202 /*
3203  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3204  *one and check the value returned for NumPhyEvents at runtime.
3205  */
3206 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
3207 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
3208 #endif
3209 
3210 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
3211 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3212 		Header;                     /*0x00 */
3213 	U32
3214 		Reserved1;                  /*0x08 */
3215 	U8
3216 		NumPhyEvents;               /*0x0C */
3217 	U8
3218 		Reserved2;                  /*0x0D */
3219 	U16
3220 		Reserved3;                  /*0x0E */
3221 	MPI2_SASPHY3_PHY_EVENT_CONFIG
3222 		PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
3223 } MPI2_CONFIG_PAGE_SAS_PHY_3,
3224 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
3225 	Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
3226 
3227 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
3228 
3229 
3230 /*SAS PHY Page 4 */
3231 
3232 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
3233 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3234 		Header;                     /*0x00 */
3235 	U16
3236 		Reserved1;                  /*0x08 */
3237 	U8
3238 		Reserved2;                  /*0x0A */
3239 	U8
3240 		Flags;                      /*0x0B */
3241 	U8
3242 		InitialFrame[28];           /*0x0C */
3243 } MPI2_CONFIG_PAGE_SAS_PHY_4,
3244 	*PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
3245 	Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
3246 
3247 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
3248 
3249 /*values for the Flags field */
3250 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
3251 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
3252 
3253 
3254 
3255 
3256 /****************************************************************************
3257 *  SAS Port Config Pages
3258 ****************************************************************************/
3259 
3260 /*SAS Port Page 0 */
3261 
3262 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
3263 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3264 		Header;                     /*0x00 */
3265 	U8
3266 		PortNumber;                 /*0x08 */
3267 	U8
3268 		PhysicalPort;               /*0x09 */
3269 	U8
3270 		PortWidth;                  /*0x0A */
3271 	U8
3272 		PhysicalPortWidth;          /*0x0B */
3273 	U8
3274 		ZoneGroup;                  /*0x0C */
3275 	U8
3276 		Reserved1;                  /*0x0D */
3277 	U16
3278 		Reserved2;                  /*0x0E */
3279 	U64
3280 		SASAddress;                 /*0x10 */
3281 	U32
3282 		DeviceInfo;                 /*0x18 */
3283 	U32
3284 		Reserved3;                  /*0x1C */
3285 	U32
3286 		Reserved4;                  /*0x20 */
3287 } MPI2_CONFIG_PAGE_SAS_PORT_0,
3288 	*PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
3289 	Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
3290 
3291 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
3292 
3293 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
3294 
3295 
3296 /****************************************************************************
3297 *  SAS Enclosure Config Pages
3298 ****************************************************************************/
3299 
3300 /*SAS Enclosure Page 0 */
3301 
3302 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3303 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3304 	U32	Reserved1;			/*0x08 */
3305 	U64	EnclosureLogicalID;		/*0x0C */
3306 	U16	Flags;				/*0x14 */
3307 	U16	EnclosureHandle;		/*0x16 */
3308 	U16	NumSlots;			/*0x18 */
3309 	U16	StartSlot;			/*0x1A */
3310 	U8	ChassisSlot;			/*0x1C */
3311 	U8	EnclosureLevel;			/*0x1D */
3312 	U16	SEPDevHandle;			/*0x1E */
3313 	U8	OEMRD;				/*0x20 */
3314 	U8	Reserved1a;			/*0x21 */
3315 	U16	Reserved2;			/*0x22 */
3316 	U32	Reserved3;			/*0x24 */
3317 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3318 	*PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3319 	Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
3320 	MPI26_CONFIG_PAGE_ENCLOSURE_0,
3321 	*PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
3322 	Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t;
3323 
3324 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
3325 
3326 /*values for SAS Enclosure Page 0 Flags field */
3327 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID          (0x0080)
3328 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING     (0x0040)
3329 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID    (0x0020)
3330 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
3331 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
3332 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
3333 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
3334 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
3335 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
3336 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
3337 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
3338 
3339 #define MPI26_ENCLOSURE0_PAGEVERSION        (0x04)
3340 
3341 /*Values for Enclosure Page 0 Flags field */
3342 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID              (0x0080)
3343 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING         (0x0040)
3344 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID       (0x0020)
3345 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID         (0x0010)
3346 #define MPI26_ENCLS0_FLAGS_MNG_MASK                 (0x000F)
3347 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN              (0x0000)
3348 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES              (0x0001)
3349 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO            (0x0002)
3350 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO            (0x0003)
3351 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE        (0x0004)
3352 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO             (0x0005)
3353 
3354 /****************************************************************************
3355 *  Log Config Page
3356 ****************************************************************************/
3357 
3358 /*Log Page 0 */
3359 
3360 /*
3361  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3362  *one and check the value returned for NumLogEntries at runtime.
3363  */
3364 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3365 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
3366 #endif
3367 
3368 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
3369 
3370 typedef struct _MPI2_LOG_0_ENTRY {
3371 	U64         TimeStamp;                      /*0x00 */
3372 	U32         Reserved1;                      /*0x08 */
3373 	U16         LogSequence;                    /*0x0C */
3374 	U16         LogEntryQualifier;              /*0x0E */
3375 	U8          VP_ID;                          /*0x10 */
3376 	U8          VF_ID;                          /*0x11 */
3377 	U16         Reserved2;                      /*0x12 */
3378 	U8
3379 		LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3380 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3381 	Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3382 
3383 /*values for Log Page 0 LogEntry LogEntryQualifier field */
3384 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
3385 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
3386 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
3387 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
3388 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
3389 
3390 typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3391 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;       /*0x00 */
3392 	U32                                 Reserved1;    /*0x08 */
3393 	U32                                 Reserved2;    /*0x0C */
3394 	U16                                 NumLogEntries;/*0x10 */
3395 	U16                                 Reserved3;    /*0x12 */
3396 	MPI2_LOG_0_ENTRY
3397 		LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3398 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3399 	Mpi2LogPage0_t, *pMpi2LogPage0_t;
3400 
3401 #define MPI2_LOG_0_PAGEVERSION              (0x02)
3402 
3403 
3404 /****************************************************************************
3405 *  RAID Config Page
3406 ****************************************************************************/
3407 
3408 /*RAID Page 0 */
3409 
3410 /*
3411  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3412  *one and check the value returned for NumElements at runtime.
3413  */
3414 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3415 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
3416 #endif
3417 
3418 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3419 	U16                     ElementFlags;             /*0x00 */
3420 	U16                     VolDevHandle;             /*0x02 */
3421 	U8                      HotSparePool;             /*0x04 */
3422 	U8                      PhysDiskNum;              /*0x05 */
3423 	U16                     PhysDiskDevHandle;        /*0x06 */
3424 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3425 	*PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3426 	Mpi2RaidConfig0ConfigElement_t,
3427 	*pMpi2RaidConfig0ConfigElement_t;
3428 
3429 /*values for the ElementFlags field */
3430 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
3431 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
3432 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
3433 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
3434 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
3435 
3436 
3437 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3438 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;         /*0x00 */
3439 	U8                                  NumHotSpares;   /*0x08 */
3440 	U8                                  NumPhysDisks;   /*0x09 */
3441 	U8                                  NumVolumes;     /*0x0A */
3442 	U8                                  ConfigNum;      /*0x0B */
3443 	U32                                 Flags;          /*0x0C */
3444 	U8                                  ConfigGUID[24]; /*0x10 */
3445 	U32                                 Reserved1;      /*0x28 */
3446 	U8                                  NumElements;    /*0x2C */
3447 	U8                                  Reserved2;      /*0x2D */
3448 	U16                                 Reserved3;      /*0x2E */
3449 	MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3450 		ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3451 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3452 	*PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3453 	Mpi2RaidConfigurationPage0_t,
3454 	*pMpi2RaidConfigurationPage0_t;
3455 
3456 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
3457 
3458 /*values for RAID Configuration Page 0 Flags field */
3459 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
3460 
3461 
3462 /****************************************************************************
3463 *  Driver Persistent Mapping Config Pages
3464 ****************************************************************************/
3465 
3466 /*Driver Persistent Mapping Page 0 */
3467 
3468 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3469 	U64	PhysicalIdentifier;         /*0x00 */
3470 	U16	MappingInformation;         /*0x08 */
3471 	U16	DeviceIndex;                /*0x0A */
3472 	U32	PhysicalBitsMapping;        /*0x0C */
3473 	U32	Reserved1;                  /*0x10 */
3474 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3475 	*PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3476 	Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3477 
3478 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3479 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header; /*0x00 */
3480 	MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;  /*0x08 */
3481 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3482 	*PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3483 	Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3484 
3485 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
3486 
3487 /*values for Driver Persistent Mapping Page 0 MappingInformation field */
3488 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
3489 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
3490 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
3491 
3492 
3493 /****************************************************************************
3494 *  Ethernet Config Pages
3495 ****************************************************************************/
3496 
3497 /*Ethernet Page 0 */
3498 
3499 /*IP address (union of IPv4 and IPv6) */
3500 typedef union _MPI2_ETHERNET_IP_ADDR {
3501 	U32     IPv4Addr;
3502 	U32     IPv6Addr[4];
3503 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3504 	Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3505 
3506 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
3507 
3508 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3509 	MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;          /*0x00 */
3510 	U8                                  NumInterfaces;   /*0x08 */
3511 	U8                                  Reserved0;       /*0x09 */
3512 	U16                                 Reserved1;       /*0x0A */
3513 	U32                                 Status;          /*0x0C */
3514 	U8                                  MediaState;      /*0x10 */
3515 	U8                                  Reserved2;       /*0x11 */
3516 	U16                                 Reserved3;       /*0x12 */
3517 	U8                                  MacAddress[6];   /*0x14 */
3518 	U8                                  Reserved4;       /*0x1A */
3519 	U8                                  Reserved5;       /*0x1B */
3520 	MPI2_ETHERNET_IP_ADDR               IpAddress;       /*0x1C */
3521 	MPI2_ETHERNET_IP_ADDR               SubnetMask;      /*0x2C */
3522 	MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;/*0x3C */
3523 	MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;   /*0x4C */
3524 	MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;   /*0x5C */
3525 	MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;   /*0x6C */
3526 	U8
3527 		HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3528 } MPI2_CONFIG_PAGE_ETHERNET_0,
3529 	*PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3530 	Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3531 
3532 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
3533 
3534 /*values for Ethernet Page 0 Status field */
3535 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
3536 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
3537 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
3538 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
3539 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
3540 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
3541 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
3542 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
3543 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
3544 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
3545 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
3546 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
3547 
3548 /*values for Ethernet Page 0 MediaState field */
3549 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
3550 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
3551 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
3552 
3553 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
3554 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
3555 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
3556 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
3557 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
3558 
3559 
3560 /*Ethernet Page 1 */
3561 
3562 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3563 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3564 		Header;                 /*0x00 */
3565 	U32
3566 		Reserved0;              /*0x08 */
3567 	U32
3568 		Flags;                  /*0x0C */
3569 	U8
3570 		MediaState;             /*0x10 */
3571 	U8
3572 		Reserved1;              /*0x11 */
3573 	U16
3574 		Reserved2;              /*0x12 */
3575 	U8
3576 		MacAddress[6];          /*0x14 */
3577 	U8
3578 		Reserved3;              /*0x1A */
3579 	U8
3580 		Reserved4;              /*0x1B */
3581 	MPI2_ETHERNET_IP_ADDR
3582 		StaticIpAddress;        /*0x1C */
3583 	MPI2_ETHERNET_IP_ADDR
3584 		StaticSubnetMask;       /*0x2C */
3585 	MPI2_ETHERNET_IP_ADDR
3586 		StaticGatewayIpAddress; /*0x3C */
3587 	MPI2_ETHERNET_IP_ADDR
3588 		StaticDNS1IpAddress;    /*0x4C */
3589 	MPI2_ETHERNET_IP_ADDR
3590 		StaticDNS2IpAddress;    /*0x5C */
3591 	U32
3592 		Reserved5;              /*0x6C */
3593 	U32
3594 		Reserved6;              /*0x70 */
3595 	U32
3596 		Reserved7;              /*0x74 */
3597 	U32
3598 		Reserved8;              /*0x78 */
3599 	U8
3600 		HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3601 } MPI2_CONFIG_PAGE_ETHERNET_1,
3602 	*PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3603 	Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3604 
3605 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
3606 
3607 /*values for Ethernet Page 1 Flags field */
3608 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
3609 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
3610 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
3611 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
3612 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
3613 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
3614 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
3615 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
3616 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
3617 
3618 /*values for Ethernet Page 1 MediaState field */
3619 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
3620 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
3621 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
3622 
3623 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
3624 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
3625 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
3626 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
3627 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
3628 
3629 
3630 /****************************************************************************
3631 *  Extended Manufacturing Config Pages
3632 ****************************************************************************/
3633 
3634 /*
3635  *Generic structure to use for product-specific extended manufacturing pages
3636  *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3637  *Page 60).
3638  */
3639 
3640 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3641 	MPI2_CONFIG_EXTENDED_PAGE_HEADER
3642 		Header;                 /*0x00 */
3643 	U32
3644 		ProductSpecificInfo;    /*0x08 */
3645 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3646 	*PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3647 	Mpi2ExtManufacturingPagePS_t,
3648 	*pMpi2ExtManufacturingPagePS_t;
3649 
3650 /*PageVersion should be provided by product-specific code */
3651 
3652 
3653 
3654 /****************************************************************************
3655 *  values for fields used by several types of PCIe Config Pages
3656 ****************************************************************************/
3657 
3658 /*values for NegotiatedLinkRates fields */
3659 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL          (0x0F)
3660 /*link rates used for Negotiated Physical Link Rate */
3661 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN                (0x00)
3662 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED           (0x01)
3663 #define MPI26_PCIE_NEG_LINK_RATE_2_5                    (0x02)
3664 #define MPI26_PCIE_NEG_LINK_RATE_5_0                    (0x03)
3665 #define MPI26_PCIE_NEG_LINK_RATE_8_0                    (0x04)
3666 #define MPI26_PCIE_NEG_LINK_RATE_16_0                   (0x05)
3667 
3668 
3669 /****************************************************************************
3670 *  PCIe IO Unit Config Pages (MPI v2.6 and later)
3671 ****************************************************************************/
3672 
3673 /*PCIe IO Unit Page 0 */
3674 
3675 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA {
3676 	U8	Link;                   /*0x00 */
3677 	U8	LinkFlags;              /*0x01 */
3678 	U8	PhyFlags;               /*0x02 */
3679 	U8	NegotiatedLinkRate;     /*0x03 */
3680 	U32	ControllerPhyDeviceInfo;/*0x04 */
3681 	U16	AttachedDevHandle;      /*0x08 */
3682 	U16	ControllerDevHandle;    /*0x0A */
3683 	U32	EnumerationStatus;      /*0x0C */
3684 	U32	Reserved1;              /*0x10 */
3685 } MPI26_PCIE_IO_UNIT0_PHY_DATA,
3686 	*PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
3687 	Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t;
3688 
3689 /*
3690  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3691  *one and check the value returned for NumPhys at runtime.
3692  */
3693 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX
3694 #define MPI26_PCIE_IOUNIT0_PHY_MAX      (1)
3695 #endif
3696 
3697 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 {
3698 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header; /*0x00 */
3699 	U32	Reserved1;                              /*0x08 */
3700 	U8	NumPhys;                                /*0x0C */
3701 	U8	InitStatus;                             /*0x0D */
3702 	U16	Reserved3;                              /*0x0E */
3703 	MPI26_PCIE_IO_UNIT0_PHY_DATA
3704 		PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX];    /*0x10 */
3705 } MPI26_CONFIG_PAGE_PIOUNIT_0,
3706 	*PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
3707 	Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t;
3708 
3709 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION                   (0x00)
3710 
3711 /*values for PCIe IO Unit Page 0 LinkFlags */
3712 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
3713 
3714 /*values for PCIe IO Unit Page 0 PhyFlags */
3715 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED             (0x08)
3716 
3717 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3718 
3719 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3720  *values
3721  */
3722 
3723 /*values for PCIe IO Unit Page 0 EnumerationStatus */
3724 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED          (0x40000000)
3725 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED           (0x20000000)
3726 
3727 
3728 /*PCIe IO Unit Page 1 */
3729 
3730 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA {
3731 	U8	Link;                       /*0x00 */
3732 	U8	LinkFlags;                  /*0x01 */
3733 	U8	PhyFlags;                   /*0x02 */
3734 	U8	MaxMinLinkRate;             /*0x03 */
3735 	U32	ControllerPhyDeviceInfo;    /*0x04 */
3736 	U32	Reserved1;                  /*0x08 */
3737 } MPI26_PCIE_IO_UNIT1_PHY_DATA,
3738 	*PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
3739 	Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
3740 
3741 /*values for LinkFlags */
3742 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK     (0x00)
3743 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN                 (0x01)
3744 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN                 (0x02)
3745 
3746 /*
3747  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3748  *one and check the value returned for NumPhys at runtime.
3749  */
3750 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX
3751 #define MPI26_PCIE_IOUNIT1_PHY_MAX      (1)
3752 #endif
3753 
3754 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3755 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3756 	U16	ControlFlags;                       /*0x08 */
3757 	U16	Reserved;                           /*0x0A */
3758 	U16	AdditionalControlFlags;             /*0x0C */
3759 	U16	NVMeMaxQueueDepth;                  /*0x0E */
3760 	U8	NumPhys;                            /*0x10 */
3761 	U8	DMDReportPCIe;                      /*0x11 */
3762 	U16	Reserved2;                          /*0x12 */
3763 	MPI26_PCIE_IO_UNIT1_PHY_DATA
3764 		PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */
3765 } MPI26_CONFIG_PAGE_PIOUNIT_1,
3766 	*PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
3767 	Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t;
3768 
3769 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION   (0x00)
3770 
3771 /*values for PCIe IO Unit Page 1 PhyFlags */
3772 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                      (0x08)
3773 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY                    (0x01)
3774 
3775 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */
3776 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK                             (0xF0)
3777 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT                            (4)
3778 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5                              (0x20)
3779 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0                              (0x30)
3780 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0                              (0x40)
3781 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0                             (0x50)
3782 
3783 /*values for PCIe IO Unit Page 1 DMDReportPCIe */
3784 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK                          (0x80)
3785 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC                         (0x00)
3786 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC                        (0x80)
3787 #define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK                    (0x7F)
3788 
3789 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3790  *values
3791  */
3792 
3793 
3794 /****************************************************************************
3795 *  PCIe Switch Config Pages (MPI v2.6 and later)
3796 ****************************************************************************/
3797 
3798 /*PCIe Switch Page 0 */
3799 
3800 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 {
3801 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3802 	U8	PhysicalPort;               /*0x08 */
3803 	U8	Reserved1;                  /*0x09 */
3804 	U16	Reserved2;                  /*0x0A */
3805 	U16	DevHandle;                  /*0x0C */
3806 	U16	ParentDevHandle;            /*0x0E */
3807 	U8	NumPorts;                   /*0x10 */
3808 	U8	PCIeLevel;                  /*0x11 */
3809 	U16	Reserved3;                  /*0x12 */
3810 	U32	Reserved4;                  /*0x14 */
3811 	U32	Reserved5;                  /*0x18 */
3812 	U32	Reserved6;                  /*0x1C */
3813 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
3814 	Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t;
3815 
3816 #define MPI26_PCIESWITCH0_PAGEVERSION       (0x00)
3817 
3818 
3819 /*PCIe Switch Page 1 */
3820 
3821 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 {
3822 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3823 	U8	PhysicalPort;               /*0x08 */
3824 	U8	Reserved1;                  /*0x09 */
3825 	U16	Reserved2;                  /*0x0A */
3826 	U8	NumPorts;                   /*0x0C */
3827 	U8	PortNum;                    /*0x0D */
3828 	U16	AttachedDevHandle;          /*0x0E */
3829 	U16	SwitchDevHandle;            /*0x10 */
3830 	U8	NegotiatedPortWidth;        /*0x12 */
3831 	U8	NegotiatedLinkRate;         /*0x13 */
3832 	U32	Reserved4;                  /*0x14 */
3833 	U32	Reserved5;                  /*0x18 */
3834 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
3835 	Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t;
3836 
3837 #define MPI26_PCIESWITCH1_PAGEVERSION       (0x00)
3838 
3839 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3840 
3841 /* defines for the Flags field */
3842 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE         (0x0002)
3843 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE           (0x0001)
3844 
3845 /****************************************************************************
3846 *  PCIe Device Config Pages (MPI v2.6 and later)
3847 ****************************************************************************/
3848 
3849 /*PCIe Device Page 0 */
3850 
3851 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 {
3852 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3853 	U16	Slot;                   /*0x08 */
3854 	U16	EnclosureHandle;        /*0x0A */
3855 	U64	WWID;                   /*0x0C */
3856 	U16	ParentDevHandle;        /*0x14 */
3857 	U8	PortNum;                /*0x16 */
3858 	U8	AccessStatus;           /*0x17 */
3859 	U16	DevHandle;              /*0x18 */
3860 	U8	PhysicalPort;           /*0x1A */
3861 	U8	Reserved1;              /*0x1B */
3862 	U32	DeviceInfo;             /*0x1C */
3863 	U32	Flags;                  /*0x20 */
3864 	U8	SupportedLinkRates;     /*0x24 */
3865 	U8	MaxPortWidth;           /*0x25 */
3866 	U8	NegotiatedPortWidth;    /*0x26 */
3867 	U8	NegotiatedLinkRate;     /*0x27 */
3868 	U8	EnclosureLevel;         /*0x28 */
3869 	U8	Reserved2;              /*0x29 */
3870 	U16	Reserved3;              /*0x2A */
3871 	U8	ConnectorName[4];       /*0x2C */
3872 	U32	Reserved4;              /*0x30 */
3873 	U32	Reserved5;              /*0x34 */
3874 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
3875 	Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t;
3876 
3877 #define MPI26_PCIEDEVICE0_PAGEVERSION       (0x01)
3878 
3879 /*values for PCIe Device Page 0 AccessStatus field */
3880 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS                    (0x00)
3881 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION         (0x04)
3882 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED            (0x02)
3883 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED               (0x07)
3884 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED   (0x08)
3885 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE           (0x09)
3886 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED                (0x0A)
3887 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN                      (0x10)
3888 
3889 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT           (0x30)
3890 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED      (0x31)
3891 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED         (0x32)
3892 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED          (0x33)
3893 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED        (0x34)
3894 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED         (0x35)
3895 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
3896 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT            (0x37)
3897 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS          (0x38)
3898 
3899 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX                (0x3F)
3900 
3901 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo
3902  *field
3903  */
3904 
3905 /*values for PCIe Device Page 0 Flags field*/
3906 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE             (0x00020000)
3907 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE               (0x00010000)
3908 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE            (0x00008000)
3909 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH              (0x00004000)
3910 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE              (0x00002000)
3911 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION      (0x00000400)
3912 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION            (0x00000200)
3913 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE             (0x00000100)
3914 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED        (0x00000080)
3915 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED            (0x00000040)
3916 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED              (0x00000020)
3917 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED              (0x00000010)
3918 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID               (0x00000002)
3919 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT                 (0x00000001)
3920 
3921 /* values for PCIe Device Page 0 SupportedLinkRates field */
3922 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED             (0x08)
3923 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED              (0x04)
3924 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED              (0x02)
3925 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED              (0x01)
3926 
3927 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3928 
3929 
3930 /*PCIe Device Page 2 */
3931 
3932 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 {
3933 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3934 	U16	DevHandle;		/*0x08 */
3935 	U8	ControllerResetTO;		/* 0x0A */
3936 	U8	Reserved1;		/* 0x0B */
3937 	U32	MaximumDataTransferSize;	/*0x0C */
3938 	U32	Capabilities;		/*0x10 */
3939 	U16	NOIOB;		/* 0x14 */
3940 	U16     ShutdownLatency;        /* 0x16 */
3941 	U16     VendorID;               /* 0x18 */
3942 	U16     DeviceID;               /* 0x1A */
3943 	U16     SubsystemVendorID;      /* 0x1C */
3944 	U16     SubsystemID;            /* 0x1E */
3945 	U8      RevisionID;             /* 0x20 */
3946 	U8      Reserved21[3];          /* 0x21 */
3947 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
3948 	Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t;
3949 
3950 #define MPI26_PCIEDEVICE2_PAGEVERSION       (0x01)
3951 
3952 /*defines for PCIe Device Page 2 Capabilities field */
3953 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN     (0x00000008)
3954 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT                  (0x00000004)
3955 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT          (0x00000002)
3956 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT                 (0x00000001)
3957 
3958 /* Defines for the NOIOB field */
3959 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED                (0x0000)
3960 
3961 /****************************************************************************
3962 *  PCIe Link Config Pages (MPI v2.6 and later)
3963 ****************************************************************************/
3964 
3965 /*PCIe Link Page 1 */
3966 
3967 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 {
3968 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
3969 	U8	Link;				/*0x08 */
3970 	U8	Reserved1;			/*0x09 */
3971 	U16	Reserved2;			/*0x0A */
3972 	U32	CorrectableErrorCount;		/*0x0C */
3973 	U16	NonFatalErrorCount;		/*0x10 */
3974 	U16	Reserved3;			/*0x12 */
3975 	U16	FatalErrorCount;		/*0x14 */
3976 	U16	Reserved4;			/*0x16 */
3977 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
3978 	Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t;
3979 
3980 #define MPI26_PCIELINK1_PAGEVERSION            (0x00)
3981 
3982 /*PCIe Link Page 2 */
3983 
3984 typedef struct _MPI26_PCIELINK2_LINK_EVENT {
3985 	U8	LinkEventCode;		/*0x00 */
3986 	U8	Reserved1;		/*0x01 */
3987 	U16	Reserved2;		/*0x02 */
3988 	U32	LinkEventInfo;		/*0x04 */
3989 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT,
3990 	Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t;
3991 
3992 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
3993 
3994 
3995 /*
3996  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3997  *one and check the value returned for NumLinkEvents at runtime.
3998  */
3999 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX
4000 #define MPI26_PCIELINK2_LINK_EVENT_MAX      (1)
4001 #endif
4002 
4003 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 {
4004 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
4005 	U8	Link;                       /*0x08 */
4006 	U8	Reserved1;                  /*0x09 */
4007 	U16	Reserved2;                  /*0x0A */
4008 	U8	NumLinkEvents;              /*0x0C */
4009 	U8	Reserved3;                  /*0x0D */
4010 	U16	Reserved4;                  /*0x0E */
4011 	MPI26_PCIELINK2_LINK_EVENT
4012 		LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX];	/*0x10 */
4013 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
4014 	Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t;
4015 
4016 #define MPI26_PCIELINK2_PAGEVERSION            (0x00)
4017 
4018 /*PCIe Link Page 3 */
4019 
4020 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG {
4021 	U8	LinkEventCode;      /*0x00 */
4022 	U8	Reserved1;          /*0x01 */
4023 	U16	Reserved2;          /*0x02 */
4024 	U8	CounterType;        /*0x04 */
4025 	U8	ThresholdWindow;    /*0x05 */
4026 	U8	TimeUnits;          /*0x06 */
4027 	U8	Reserved3;          /*0x07 */
4028 	U32	EventThreshold;     /*0x08 */
4029 	U16	ThresholdFlags;     /*0x0C */
4030 	U16	Reserved4;          /*0x0E */
4031 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
4032 	Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t;
4033 
4034 /*values for LinkEventCode field */
4035 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT                              (0x00)
4036 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED            (0x01)
4037 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED              (0x02)
4038 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED                  (0x03)
4039 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED              (0x04)
4040 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED      (0x05)
4041 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED               (0x06)
4042 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP                          (0x07)
4043 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP                     (0x08)
4044 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP                         (0x09)
4045 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE                  (0x0A)
4046 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE                     (0x0B)
4047 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE                     (0x0C)
4048 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE                        (0x0D)
4049 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE                  (0x0E)
4050 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE                 (0x0F)
4051 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR                          (0x10)
4052 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR                          (0x11)
4053 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR                       (0x12)
4054 
4055 /*values for the CounterType field */
4056 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING               (0x00)
4057 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING             (0x01)
4058 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE             (0x02)
4059 
4060 /*values for the TimeUnits field */
4061 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS            (0x00)
4062 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS           (0x01)
4063 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND              (0x02)
4064 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS            (0x03)
4065 
4066 /*values for the ThresholdFlags field */
4067 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY                 (0x0001)
4068 
4069 /*
4070  *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
4071  *one and check the value returned for NumLinkEvents at runtime.
4072  */
4073 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX
4074 #define MPI26_PCIELINK3_LINK_EVENT_MAX      (1)
4075 #endif
4076 
4077 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 {
4078 	MPI2_CONFIG_EXTENDED_PAGE_HEADER	Header;	/*0x00 */
4079 	U8	Link;                       /*0x08 */
4080 	U8	Reserved1;                  /*0x09 */
4081 	U16	Reserved2;                  /*0x0A */
4082 	U8	NumLinkEvents;              /*0x0C */
4083 	U8	Reserved3;                  /*0x0D */
4084 	U16	Reserved4;                  /*0x0E */
4085 	MPI26_PCIELINK3_LINK_EVENT_CONFIG
4086 		LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /*0x10 */
4087 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
4088 	Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t;
4089 
4090 #define MPI26_PCIELINK3_PAGEVERSION            (0x00)
4091 
4092 
4093 #endif
4094