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Searched refs:pclk_rate (Results 1 – 8 of 8) sorted by relevance

/drivers/watchdog/
Drzg2l_wdt.c252 unsigned long pclk_rate; in rzg2l_wdt_probe() local
277 pclk_rate = clk_get_rate(priv->pclk); in rzg2l_wdt_probe()
278 if (!pclk_rate) in rzg2l_wdt_probe()
281 priv->delay = F2CYCLE_NSEC(priv->osc_clk_rate) * 6 + F2CYCLE_NSEC(pclk_rate) * 9; in rzg2l_wdt_probe()
296 3 * F2CYCLE_NSEC(pclk_rate) + 5 * in rzg2l_wdt_probe()
298 F2CYCLE_NSEC(pclk_rate)); in rzg2l_wdt_probe()
/drivers/clocksource/
Dtimer-microchip-pit64b.c294 unsigned long pclk_rate, diff = 0, best_diff = ULONG_MAX; in mchp_pit64b_init_mode() local
298 pclk_rate = clk_get_rate(timer->pclk); in mchp_pit64b_init_mode()
299 if (!pclk_rate) in mchp_pit64b_init_mode()
309 if (pclk_rate / gclk_round < 3) in mchp_pit64b_init_mode()
324 mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate); in mchp_pit64b_init_mode()
325 diff = abs(pclk_rate / (pres + 1) - max_rate); in mchp_pit64b_init_mode()
342 gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1)); in mchp_pit64b_init_mode()
/drivers/ufs/host/
Dufs-exynos.c418 unsigned long pclk_rate; in exynos_ufs_get_clk_info() local
442 pclk_rate = clk_get_rate(ufs->clk_hci_core); in exynos_ufs_get_clk_info()
448 pclk_rate /= (div + 1); in exynos_ufs_get_clk_info()
450 if (pclk_rate <= f_max) in exynos_ufs_get_clk_info()
453 } while (pclk_rate >= f_min); in exynos_ufs_get_clk_info()
456 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) { in exynos_ufs_get_clk_info()
457 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate); in exynos_ufs_get_clk_info()
462 ufs->pclk_rate = pclk_rate; in exynos_ufs_get_clk_info()
523 long pclk_rate = ufs->pclk_rate; in exynos_ufs_calc_time_cntr() local
527 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate; in exynos_ufs_calc_time_cntr()
Dufs-exynos.h102 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate)
202 u32 pclk_rate; member
/drivers/gpu/drm/tilcdc/
Dtilcdc_crtc.c207 unsigned long clk_rate, real_pclk_rate, pclk_rate; in tilcdc_crtc_set_clk() local
214 pclk_rate = crtc->mode.clock * 1000; in tilcdc_crtc_set_clk()
216 ret = clk_set_rate(priv->clk, pclk_rate * clkdiv); in tilcdc_crtc_set_clk()
219 if (ret < 0 || tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) { in tilcdc_crtc_set_clk()
234 clkdiv = DIV_ROUND_CLOSEST(clk_rate, pclk_rate); in tilcdc_crtc_set_clk()
245 if (tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) { in tilcdc_crtc_set_clk()
248 real_pclk_rate, pclk_rate); in tilcdc_crtc_set_clk()
/drivers/gpu/drm/msm/dsi/
Ddsi_host.c546 unsigned long pclk_rate; in dsi_get_pclk_rate() local
548 pclk_rate = mode->clock * 1000; in dsi_get_pclk_rate()
551 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); in dsi_get_pclk_rate()
560 pclk_rate /= 2; in dsi_get_pclk_rate()
562 return pclk_rate; in dsi_get_pclk_rate()
571 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); in dsi_byte_clk_get_rate() local
581 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); in dsi_byte_clk_get_rate()
583 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); in dsi_byte_clk_get_rate()
/drivers/spi/
Dspi-rzv2m-csi.c346 unsigned long pclk_rate = clk_get_rate(csi->pclk); in rzv2m_csi_setup_clock() local
347 unsigned long csiclk_rate_limit = pclk_rate >> 1; in rzv2m_csi_setup_clock()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder.c1694 u64 pclk_rate; in _dpu_encoder_calculate_linetime() local
1709 pclk_rate = mode->clock; /* pixel clock in kHz */ in _dpu_encoder_calculate_linetime()
1710 if (pclk_rate == 0) { in _dpu_encoder_calculate_linetime()
1715 pclk_period = DIV_ROUND_UP_ULL(1000000000ull, pclk_rate); in _dpu_encoder_calculate_linetime()
1733 pclk_rate, pclk_period, line_time); in _dpu_encoder_calculate_linetime()