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Searched refs:phy_rate (Results 1 – 9 of 9) sorted by relevance

/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dampdu.c321 u32 phy_rate, dma_rate, tmp; in brcms_c_ffpld_calc_mcs2ampdu_table() local
329 phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false); in brcms_c_ffpld_calc_mcs2ampdu_table()
331 (((phy_rate / 100) * in brcms_c_ffpld_calc_mcs2ampdu_table()
340 phy_rate = mcs_2_rate(i, true, false) >> 7; in brcms_c_ffpld_calc_mcs2ampdu_table()
341 if (phy_rate > dma_rate) { in brcms_c_ffpld_calc_mcs2ampdu_table()
342 tmp = ((fifo->ampdu_pld_size * phy_rate) / in brcms_c_ffpld_calc_mcs2ampdu_table()
343 ((phy_rate - dma_rate) * FFPLD_MPDU_SIZE)) + 1; in brcms_c_ffpld_calc_mcs2ampdu_table()
359 u32 phy_rate = mcs_2_rate(FFPLD_MAX_MCS, true, false); in brcms_c_ffpld_check_txfunfl() local
448 (((phy_rate / 100) * in brcms_c_ffpld_check_txfunfl()
Dmain.c3607 u8 phy_rate, index; in brcms_c_write_rate_shm() local
3622 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; in brcms_c_write_rate_shm()
3624 index = phy_rate & 0xf; in brcms_c_write_rate_shm()
5638 u8 phy_rate, index; in brcms_b_rate_shm_offset() local
5649 phy_rate = rate_info[rate] & BRCMS_RATE_MASK; in brcms_b_rate_shm_offset()
5650 index = phy_rate & 0xf; in brcms_b_rate_shm_offset()
/drivers/net/wireless/realtek/rtw89/
Dpci.c1876 __get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate) in __get_target() argument
1882 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val); in __get_target()
1886 phy_rate); in __get_target()
1890 phy_rate); in __get_target()
1896 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar); in __get_target()
1900 phy_rate); in __get_target()
1931 enum rtw89_pcie_phy phy_rate; in rtw89_pci_auto_refclk_cal() local
1948 phy_rate = PCIE_PHY_GEN1; in rtw89_pci_auto_refclk_cal()
1950 phy_rate = PCIE_PHY_GEN2; in rtw89_pci_auto_refclk_cal()
1973 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16); in rtw89_pci_auto_refclk_cal()
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/drivers/net/wireless/broadcom/b43/
Dxmit.h34 __u8 phy_rate; /* PHY rate */ member
Dxmit.c272 txhdr->phy_rate = b43_plcp_get_ratecode_ofdm(rate); in b43_generate_txhdr()
274 txhdr->phy_rate = b43_plcp_get_ratecode_cck(rate); in b43_generate_txhdr()
/drivers/scsi/mvsas/
Dmv_94xx.c231 temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
234 mvi->hba_info_param.phy_rate[phy_id] = 0x2; in mvs_94xx_config_reg_from_hba()
241 mvi->hba_info_param.phy_rate[phy_id]); in mvs_94xx_config_reg_from_hba()
Dmv_sas.h296 u8 phy_rate[8]; member
/drivers/pci/controller/dwc/
Dpci-imx6.c410 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); in imx6_setup_phy_mpll() local
417 switch (phy_rate) { in imx6_setup_phy_mpll()
434 "Unsupported PHY reference clock rate %lu\n", phy_rate); in imx6_setup_phy_mpll()
/drivers/gpu/drm/amd/display/dmub/inc/
Ddmub_cmd.h2363 uint8_t phy_rate; member
2918 uint8_t phy_rate; member