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Searched refs:pixelclock (Results 1 – 25 of 61) sorted by relevance

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/drivers/gpu/drm/omapdrm/dss/
Dsdi.c31 unsigned long pixelclock; member
147 unsigned long pixelclock = mode->clock * 1000; in sdi_bridge_mode_valid() local
152 if (pixelclock == 0) in sdi_bridge_mode_valid()
155 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); in sdi_bridge_mode_valid()
167 unsigned long pixelclock = mode->clock * 1000; in sdi_bridge_mode_fixup() local
173 ret = sdi_calc_clock_div(sdi, pixelclock, &fck, &dispc_cinfo); in sdi_bridge_mode_fixup()
179 if (pck != pixelclock) in sdi_bridge_mode_fixup()
182 pixelclock, pck); in sdi_bridge_mode_fixup()
195 sdi->pixelclock = adjusted_mode->clock * 1000; in sdi_bridge_mode_set()
213 r = sdi_calc_clock_div(sdi, sdi->pixelclock, &fck, &dispc_cinfo); in sdi_bridge_enable()
Ddpi.c40 unsigned long pixelclock; member
334 r = dpi_set_pll_clk(dpi, dpi->pixelclock); in dpi_set_mode()
336 r = dpi_set_dispc_clk(dpi, dpi->pixelclock); in dpi_set_mode()
480 dpi->pixelclock = adjusted_mode->clock * 1000; in dpi_bridge_mode_set()
Dhdmi4.c167 pc = vm->pixelclock; in hdmi_power_on_full()
394 hdmi->cfg.vm.pixelclock); in hdmi4_bridge_enable()
591 hd->cfg.vm.pixelclock); in hdmi_audio_config()
Dhdmi5.c161 pc = vm->pixelclock; in hdmi_power_on_full()
392 hdmi->cfg.vm.pixelclock); in hdmi5_bridge_enable()
575 hd->cfg.vm.pixelclock); in hdmi_audio_config()
/drivers/media/i2c/
Dths7303.c145 state->bt.pixelclock = 0; in ths7303_s_std_output()
170 if (state->bt.pixelclock > 120000000) in ths7303_config()
172 else if (state->bt.pixelclock > 70000000) in ths7303_config()
174 else if (state->bt.pixelclock > 20000000) in ths7303_config()
287 if (state->bt.pixelclock) { in ths7303_log_status()
297 (int)bt->pixelclock / in ths7303_log_status()
300 (int)bt->pixelclock, bt->polarities); in ths7303_log_status()
/drivers/gpu/drm/panel/
Dpanel-simple.c778 .pixelclock = { 29930000, 33260000, 36590000 },
819 .pixelclock = { 34500000, 39600000, 50400000 },
849 .pixelclock = { 26400000, 33300000, 46800000 },
955 .pixelclock = { 33300000, 34209000, 45000000 },
1031 .pixelclock = { 60000000, 74400000, 90000000 },
1055 .pixelclock = { 134000000, 141200000, 149000000 },
1109 .pixelclock = { 120000000, 144000000, 175000000 },
1139 .pixelclock = { 90000000, 108000000, 135000000 },
1169 .pixelclock = { 106000000, 148500000, 164000000 },
1275 .pixelclock = { 69922000, 71000000, 72293000 },
[all …]
Dpanel-olimex-lcd-olinuxino.c28 u32 pixelclock; member
160 mode->clock = lcd_mode->pixelclock; in lcd_olinuxino_get_modes()
/drivers/video/fbdev/omap2/omapfb/dss/
Ddpi.c334 r = dpi_set_dsi_clk(dpi, mgr->id, t->pixelclock, &fck, in dpi_set_mode()
337 r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck, in dpi_set_mode()
344 if (pck != t->pixelclock) { in dpi_set_mode()
346 t->pixelclock, pck); in dpi_set_mode()
348 t->pixelclock = pck; in dpi_set_mode()
508 if (timings->pixelclock == 0) in dpi_check_timings()
512 ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx); in dpi_check_timings()
518 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx); in dpi_check_timings()
530 timings->pixelclock = pck; in dpi_check_timings()
Dsdi.c145 r = sdi_calc_clock_div(t->pixelclock, &fck, &dispc_cinfo); in sdi_display_enable()
153 if (pck != t->pixelclock) { in sdi_display_enable()
155 t->pixelclock, pck); in sdi_display_enable()
157 t->pixelclock = pck; in sdi_display_enable()
239 if (timings->pixelclock == 0) in sdi_check_timings()
Ddisplay.c264 ovt->pixelclock = vm->pixelclock; in videomode_to_omap_video_timings()
296 vm->pixelclock = ovt->pixelclock; in omap_video_timings_to_videomode()
Dhdmi5.c174 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
277 dispc_set_tv_pclk(timings->pixelclock); in hdmi_display_set_timing()
368 hdmi.cfg.timings.pixelclock); in hdmi_display_enable()
662 hd->cfg.timings.pixelclock); in hdmi_audio_config()
Dhdmi4.c162 hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo); in hdmi_power_on_full()
256 dispc_set_tv_pclk(timings->pixelclock); in hdmi_display_set_timing()
338 hdmi.cfg.timings.pixelclock); in hdmi_display_enable()
630 hd->cfg.timings.pixelclock); in hdmi_audio_config()
Ddisplay-sysfs.c98 t.pixelclock, in display_timings_show()
123 &t.pixelclock, in display_timings_store()
/drivers/gpu/ipu-v3/
Dipu-di.c424 clk_set_rate(clk, sig->mode.pixelclock); in ipu_di_config_clock()
427 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); in ipu_di_config_clock()
444 div = DIV_ROUND_CLOSEST(clkrate, sig->mode.pixelclock); in ipu_di_config_clock()
448 error = rate / (sig->mode.pixelclock / 1000); in ipu_di_config_clock()
465 clk_set_rate(clk, sig->mode.pixelclock); in ipu_di_config_clock()
468 div = DIV_ROUND_CLOSEST(in_rate, sig->mode.pixelclock); in ipu_di_config_clock()
495 sig->mode.pixelclock, in ipu_di_config_clock()
573 sig->mode.pixelclock); in ipu_di_init_sync_panel()
/drivers/media/v4l2-core/
Dv4l2-dv-timings.c158 bt->pixelclock < cap->min_pixelclock || in v4l2_valid_dv_timings()
159 bt->pixelclock > cap->max_pixelclock || in v4l2_valid_dv_timings()
277 t1->bt.pixelclock >= t2->bt.pixelclock - pclock_delta && in v4l2_match_dv_timings()
278 t1->bt.pixelclock <= t2->bt.pixelclock + pclock_delta && in v4l2_match_dv_timings()
312 fps = (htot * vtot) > 0 ? div_u64((100 * (u64)bt->pixelclock), in v4l2_print_dv_timings()
338 pr_info("%s: pixelclock: %llu\n", dev_prefix, bt->pixelclock); in v4l2_print_dv_timings()
420 pclk = bt->pixelclock; in v4l2_calc_timeperframe()
652 fmt->bt.pixelclock = pix_clk; in v4l2_detect_cvt()
810 fmt->bt.pixelclock = pix_clk; in v4l2_detect_gtf()
/drivers/video/
Dvideomode.c16 vm->pixelclock = dt->pixelclock.typ; in videomode_from_timing()
/drivers/media/i2c/adv748x/
Dadv748x-hdmi.c278 int pixelclock; in adv748x_hdmi_query_dv_timings() local
299 pixelclock = adv748x_hdmi_read_pixelclock(state); in adv748x_hdmi_query_dv_timings()
300 if (pixelclock < 0) in adv748x_hdmi_query_dv_timings()
305 bt->pixelclock = pixelclock; in adv748x_hdmi_query_dv_timings()
418 return adv748x_csi2_set_pixelrate(tx, timings.bt.pixelclock); in adv748x_hdmi_propagate_pixelrate()
/drivers/gpu/drm/mediatek/
Dmtk_dpi.c521 pll_rate = vm.pixelclock * factor; in mtk_dpi_set_display_mode()
524 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
534 vm.pixelclock = pll_rate / factor; in mtk_dpi_set_display_mode()
535 vm.pixelclock /= dpi->conf->pixels_per_iter; in mtk_dpi_set_display_mode()
539 clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); in mtk_dpi_set_display_mode()
541 clk_set_rate(dpi->pixel_clk, vm.pixelclock); in mtk_dpi_set_display_mode()
544 vm.pixelclock = clk_get_rate(dpi->pixel_clk); in mtk_dpi_set_display_mode()
547 pll_rate, vm.pixelclock); in mtk_dpi_set_display_mode()
/drivers/gpu/drm/bridge/
Dtc358768.c771 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), in tc358768_bridge_pre_enable()
772 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), in tc358768_bridge_pre_enable()
773 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), in tc358768_bridge_pre_enable()
774 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), in tc358768_bridge_pre_enable()
775 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); in tc358768_bridge_pre_enable()
778 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), in tc358768_bridge_pre_enable()
779 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), in tc358768_bridge_pre_enable()
780 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); in tc358768_bridge_pre_enable()
Dtc358767.c509 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) in tc_pxl_pll_en() argument
536 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, in tc_pxl_pll_en()
538 best_delta = pixelclock; in tc_pxl_pll_en()
552 tmp = pixelclock * ext_div[i_pre] * in tc_pxl_pll_en()
566 delta = clk - pixelclock; in tc_pxl_pll_en()
581 pixelclock); in tc_pxl_pll_en()
/drivers/gpu/drm/bridge/analogix/
Danx7625.c360 static int anx7625_calculate_m_n(u32 pixelclock, in anx7625_calculate_m_n() argument
365 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { in anx7625_calculate_m_n()
368 pixelclock, in anx7625_calculate_m_n()
373 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { in anx7625_calculate_m_n()
376 pixelclock, in anx7625_calculate_m_n()
382 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) in anx7625_calculate_m_n()
387 (pixelclock < in anx7625_calculate_m_n()
410 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { in anx7625_calculate_m_n()
412 pixelclock * (*post_divider), in anx7625_calculate_m_n()
417 *m = pixelclock; in anx7625_calculate_m_n()
[all …]
/drivers/media/test-drivers/vivid/
Dvivid-vid-out.c221 u64 pixelclock; in vivid_update_format_out() local
245 pixelclock = div_u64(bt->pixelclock * 1000, 1001); in vivid_update_format_out()
247 pixelclock = bt->pixelclock; in vivid_update_format_out()
250 size / 100, (u32)pixelclock / 100 in vivid_update_format_out()
Dvivid-vid-cap.c379 u64 pixelclock; in vivid_update_format_cap() local
410 pixelclock = div_u64(bt->pixelclock * 1000, 1001); in vivid_update_format_cap()
413 pixelclock = bt->pixelclock; in vivid_update_format_cap()
417 size / 100, (u32)pixelclock / 100 in vivid_update_format_cap()
1465 h_freq = (u32)bt->pixelclock / total_h_pixel; in valid_cvt_gtf_timings()
1525 timings->bt.pixelclock = vivid_dv_timings_cap.bt.max_pixelclock * 2; in vidioc_query_dv_timings()
/drivers/gpu/drm/xen/
Dxen_drm_front_conn.c81 videomode.pixelclock = width * height * XEN_DRM_CRTC_VREFRESH_HZ; in connector_get_modes()
/drivers/gpu/drm/imx/dcss/
Ddcss-dtg.c210 u32 pixclock = vm->pixelclock; in dcss_dtg_sync_set()
224 clk_set_rate(dcss->pix_clk, vm->pixelclock); in dcss_dtg_sync_set()

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