| /drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs() local
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
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| /drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 284 static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) in get_pll_config() argument
292 *pll1 = hibmc_pll_table[i].pll1_config_value; in get_pll_config()
299 *pll1 = CRT_PLL1_HS_25MHZ; in get_pll_config()
315 u32 pll1; /* bit[31:0] of PLL */ in display_ctrl_adjust() local
322 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 set_vclock_hisilicon(dev, pll1); in display_ctrl_adjust()
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| /drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 132 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, in nouveau_hw_decode_pll() argument
140 pllvals->log2P = (pll1 >> 16) & 0x7; in nouveau_hw_decode_pll()
146 if (!(pll1 & 0x1100)) in nouveau_hw_decode_pll()
149 pllvals->NM1 = pll1 & 0xffff; in nouveau_hw_decode_pll()
154 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { in nouveau_hw_decode_pll()
155 pllvals->M2 = (pll1 >> 4) & 0x7; in nouveau_hw_decode_pll()
156 pllvals->N2 = ((pll1 >> 21) & 0x18) | in nouveau_hw_decode_pll()
157 ((pll1 >> 19) & 0x7); in nouveau_hw_decode_pll()
170 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
178 pll1 = nvif_rd32(device, reg1); in nouveau_hw_get_pllvals()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | hdmi.c | 43 u32 pll1; member
141 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
156 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
174 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
202 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
219 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
237 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
256 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
275 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
[all …]
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| D | sor.c | 366 unsigned int pll1; member
770 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
772 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
777 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
780 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
784 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
791 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
794 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
901 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
918 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
[all …]
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| /drivers/media/i2c/ |
| D | ov7251.c | 110 const struct ov7251_pll1_cfg *pll1[]; member
219 .pll1 = {
227 .pll1 = {
816 configs->pll1[ov7251->link_freq_idx]->pre_div); in ov7251_pll_configure()
821 configs->pll1[ov7251->link_freq_idx]->mult); in ov7251_pll_configure()
825 configs->pll1[ov7251->link_freq_idx]->div); in ov7251_pll_configure()
830 configs->pll1[ov7251->link_freq_idx]->pix_div); in ov7251_pll_configure()
835 configs->pll1[ov7251->link_freq_idx]->mipi_div); in ov7251_pll_configure()
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| /drivers/clk/mxs/ |
| D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
169 clks[pll1] = mxs_clk_pll("pll1", "ref_xtal", PLL1CTRL0, 17, 480000000); in mx28_clocks_init()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| D | intel_dpll_mgr.c | 1954 PORT_PLL_N_MASK, pll->state.hw_state.pll1); in bxt_ddi_pll_enable()
2070 hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_get_hw_state()
2071 hw_state->pll1 &= PORT_PLL_N_MASK; in bxt_ddi_pll_get_hw_state()
2212 dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n); in bxt_ddi_set_dpll_hw_state()
2246 clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1); in bxt_ddi_pll_get_freq()
2338 hw_state->pll1, in bxt_dump_hw_state()
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| D | intel_display.c | 5330 PIPE_CONF_CHECK_X(dpll_hw_state.pll1); in intel_pipe_config_compare()
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| /drivers/clk/ |
| D | clk-k210.c | 1002 struct k210_pll pll1; in k210_clk_early_init() local
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
1009 k210_pll_enable_hw(regs, &pll1); in k210_clk_early_init()
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| /drivers/phy/ti/ |
| D | Kconfig | 49 three clock selects (pll0, pll1, dig) and resets for each of the
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