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Searched refs:pll9 (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h207 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
Dintel_dpll_mgr.c1977 PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9); in bxt_ddi_pll_enable()
2087 hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2088 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2224 dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5); in bxt_ddi_set_dpll_hw_state()
2343 hw_state->pll9, in bxt_dump_hw_state()
Dintel_display.c5335 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); in intel_pipe_config_compare()