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Searched refs:pllfh (Results 1 – 3 of 3) sorted by relevance

/drivers/clk/mediatek/
Dclk-pllfh.c88 struct mtk_pllfh_data *pllfh; in fhctl_parse_dt() local
97 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll_id); in fhctl_parse_dt()
98 if (!pllfh) in fhctl_parse_dt()
101 pllfh->state.fh_enable = 1; in fhctl_parse_dt()
102 pllfh->state.ssc_rate = ssc_rate; in fhctl_parse_dt()
103 pllfh->state.base = base; in fhctl_parse_dt()
146 static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh) in fhctl_is_supported_and_enabled() argument
148 return pllfh && (pllfh->state.fh_enable == 1); in fhctl_is_supported_and_enabled()
214 struct mtk_pllfh_data *pllfh; in mtk_clk_register_pllfhs() local
217 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id); in mtk_clk_register_pllfhs()
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DMakefile3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
/drivers/media/dvb-frontends/
Ditd1000.c121 u8 pllfh = itd1000_read_reg(state, PLLFH) & 0x0f; in itd1000_set_lpf_bw() local
133 itd1000_write_reg(state, PLLFH, pllfh | (itd1000_lpf_pga[i].pgaext << 4)); in itd1000_set_lpf_bw()