| /drivers/clk/starfive/ |
| D | clk-starfive-jh7110-pll.c | 84 unsigned prediv : 6; member
97 unsigned int prediv; member
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
152 u32 prediv; member
164 .prediv = 8,
170 .prediv = 6,
176 .prediv = 24,
182 .prediv = 4,
188 .prediv = 24,
194 .prediv = 3,
[all …]
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| /drivers/clk/mmp/ |
| D | clk-audio.c | 120 unsigned int prediv; in audio_pll_recalc_rate() local
137 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_recalc_rate()
138 if (predivs[prediv].parent_rate != parent_rate) in audio_pll_recalc_rate()
147 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); in audio_pll_recalc_rate()
148 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); in audio_pll_recalc_rate()
149 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); in audio_pll_recalc_rate()
158 freq = predivs[prediv].freq_vco; in audio_pll_recalc_rate()
170 unsigned int prediv; in audio_pll_round_rate() local
174 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_round_rate()
175 if (predivs[prediv].parent_rate != *parent_rate) in audio_pll_round_rate()
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| /drivers/media/dvb-frontends/ |
| D | tua6100.c | 62 u32 prediv; in tua6100_set_params() local
105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); in tua6100_set_params()
106 div = prediv / _P_VAL; in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
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| D | dib7000p.c | 493 u8 loopdiv, prediv; in dib7000p_update_pll() local
497 prediv = reg_1856 & 0x3f; in dib7000p_update_pll()
500 if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { in dib7000p_update_pll()
501 …dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->p… in dib7000p_update_pll()
510 xtal = (internal / loopdiv) * prediv; in dib7000p_update_pll()
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| /drivers/clk/sunxi-ng/ |
| D | ccu_mux.c | 21 u16 prediv = 1; in ccu_mux_get_prediv() local
30 return common->prediv; in ccu_mux_get_prediv()
43 prediv = cm->fixed_predivs[i].div; in ccu_mux_get_prediv()
55 prediv = div + 1; in ccu_mux_get_prediv()
59 return prediv; in ccu_mux_get_prediv()
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| D | ccu_gate.h | 77 .prediv = _prediv, \
105 .prediv = _prediv, \
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| D | ccu_gate.c | 85 rate /= cg->common.prediv; in ccu_gate_recalc_rate()
97 div = cg->common.prediv; in ccu_gate_round_rate()
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| D | ccu_common.h | 32 u32 prediv; member
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| D | ccu-sun6i-rtc.c | 229 .prediv = 750,
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| /drivers/clk/pistachio/ |
| D | clk-pll.c | 273 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
276 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_frac_recalc_rate()
293 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
413 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
417 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_laint_recalc_rate()
425 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
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| /drivers/media/i2c/ |
| D | tc358746.c | 1093 const unsigned char prediv[] = { 2, 4, 8 }; in tc358746_find_mclk_settings() local
1133 for (i = 0; i < ARRAY_SIZE(prediv); i++) { in tc358746_find_mclk_settings()
1134 postdiv = mclkdiv / prediv[i]; in tc358746_find_mclk_settings()
1140 mclk_prediv = prediv[i]; in tc358746_find_mclk_settings()
1142 best_mclk_rate = pll_rate / (prediv[i] * postdiv); in tc358746_find_mclk_settings()
1184 unsigned int prediv, postdiv; in tc358746_recalc_rate() local
1199 prediv = FIELD_GET(MCLKDIV_MASK, val); in tc358746_recalc_rate()
1200 if (prediv == MCLKDIV_8) in tc358746_recalc_rate()
1201 prediv = 8; in tc358746_recalc_rate()
1202 else if (prediv == MCLKDIV_4) in tc358746_recalc_rate()
[all …]
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| D | st-vgxy61.c | 459 static void compute_pll_parameters_by_freq(u32 freq, u8 *prediv, u8 *mult) in compute_pll_parameters_by_freq() argument
469 *prediv = predivs[i]; in compute_pll_parameters_by_freq()
470 if (freq / *prediv < 12 * HZ_PER_MHZ) in compute_pll_parameters_by_freq()
479 *mult = ((804 * HZ_PER_MHZ) * (*prediv) + freq / 2) / freq; in compute_pll_parameters_by_freq()
1571 u8 prediv, mult; in vgxy61_configure() local
1575 compute_pll_parameters_by_freq(sensor->clk_freq, &prediv, &mult); in vgxy61_configure()
1576 sensor_freq = (mult * sensor->clk_freq) / prediv; in vgxy61_configure()
1587 vgxy61_write_reg(sensor, VGXY61_REG_CLK_PLL_PREDIV, prediv, &ret); in vgxy61_configure()
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| D | ov5640.c | 1457 u8 prediv, mult, sysdiv; in ov5640_set_mipi_pclk() local
1480 ov5640_calc_sys_clk(sensor, sysclk, &prediv, &mult, &sysdiv); in ov5640_set_mipi_pclk()
1538 root_div | prediv); in ov5640_set_mipi_pclk()
1581 u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div; in ov5640_set_dvp_pclk() local
1589 ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv, in ov5640_set_dvp_pclk()
1615 0x1f, prediv | ((pll_rdiv - 1) << 4)); in ov5640_set_dvp_pclk()
1862 u32 multiplier, prediv, VCO, sysdiv, pll_rdiv; in ov5640_get_sysclk() local
1890 prediv = temp1 & 0x0f; in ov5640_get_sysclk()
1899 if (!prediv || !sysdiv || !pll_rdiv || !bit_div2x) in ov5640_get_sysclk()
1902 VCO = xvclk * multiplier / prediv; in ov5640_get_sysclk()
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| D | ov2659.c | 897 u32 prediv, postdiv, mult; in ov2659_pll_calc_params() local
905 prediv = ctrl3[j].div; in ov2659_pll_calc_params()
909 actual /= prediv; in ov2659_pll_calc_params()
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| /drivers/clk/ |
| D | clk-vt8500.c | 351 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits() argument
359 *prediv = 1; in vt8500_find_pll_bits()
364 *prediv = 2; in vt8500_find_pll_bits()
366 *prediv = 1; in vt8500_find_pll_bits()
368 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
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| D | clk-versaclock3.c | 245 unsigned int prediv, premul; in vc3_pfd_recalc_rate() local
249 regmap_read(vc3->regmap, pfd->offs, &prediv); in vc3_pfd_recalc_rate()
252 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
259 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
262 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
270 mdiv = VC3_PLL2_M_DIV(prediv); in vc3_pfd_recalc_rate()
273 if (prediv & pfd->mdiv1_bitmsk) in vc3_pfd_recalc_rate()
276 mdiv = VC3_PLL3_M_DIV(prediv); in vc3_pfd_recalc_rate()
279 if (prediv & pfd->mdiv2_bitmsk) in vc3_pfd_recalc_rate()
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| D | clk-versaclock5.c | 344 unsigned int prediv, div; in vc5_pfd_recalc_rate() local
347 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); in vc5_pfd_recalc_rate()
352 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) in vc5_pfd_recalc_rate()
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| /drivers/clk/keystone/ |
| D | pll.c | 81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
109 rate /= (prediv + 1); in clk_pllclk_recalc()
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| /drivers/clk/imx/ |
| D | clk-composite-8m.c | 52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
58 *prediv = 1; in imx8m_clk_composite_compute_dividers()
66 *prediv = div1; in imx8m_clk_composite_compute_dividers()
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| /drivers/phy/rockchip/ |
| D | phy-rockchip-inno-dsidphy.c | 220 u8 prediv; member
358 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
385 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_dsidphy_mipi_mode_enable()
529 u8 prediv = 2; in inno_dsidphy_lvds_mode_enable() local
543 REG_PREDIV_MASK, REG_PREDIV(prediv)); in inno_dsidphy_lvds_mode_enable()
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| D | phy-rockchip-inno-hdmi.c | 253 u8 prediv; member
268 u8 prediv; member
799 RK3228_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_clk_set_rate()
953 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_clk_set_rate()
1071 RK3228_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3228_power_on()
1184 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
1192 RK3328_POST_PLL_PRE_DIV(cfg->prediv)); in inno_hdmi_phy_rk3328_power_on()
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| /drivers/clk/ralink/ |
| D | clk-mt7621.c | 262 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
279 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll); in mt7621_cpu_recalc_rate()
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
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| /drivers/media/usb/dvb-usb/ |
| D | dib0700_devices.c | 2035 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; in dib8096p_get_best_sampling() local
2046 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
2065 for (prediv = min_prediv; prediv < max_prediv; prediv++) { in dib8096p_get_best_sampling()
2066 fcp = xtal / prediv; in dib8096p_get_best_sampling()
2069 fmem = ((xtal/prediv) * loopdiv); in dib8096p_get_best_sampling()
2086 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
2090 …he.frequency, fe->dtv_property_cache.bandwidth_hz, xtal, fmem, fdem, fs, prediv, loopdiv, adc->tim… in dib8096p_get_best_sampling()
2560 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; in dib7090p_get_best_sampling() local
2571 adc->pll_prediv = prediv; in dib7090p_get_best_sampling()
2591 for (prediv = min_prediv ; prediv < max_prediv; prediv++) { in dib7090p_get_best_sampling()
[all …]
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| /drivers/phy/mediatek/ |
| D | phy-mtk-hdmi-mt8195.c | 74 static int mtk_hdmi_pll_set_hw(struct clk_hw *hw, u8 prediv, in mtk_hdmi_pll_set_hw() argument
183 prediv_value = ilog2(prediv); in mtk_hdmi_pll_set_hw()
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| /drivers/tty/serial/ |
| D | sh-sci.c | 2331 unsigned int sr, br, prediv, scrate, c; in sci_scbrr_calc() local
2355 prediv = sr << (2 * c + 1); in sci_scbrr_calc()
2366 if (bps > UINT_MAX / prediv) in sci_scbrr_calc()
2369 scrate = prediv * bps; in sci_scbrr_calc()
2373 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()
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