| /drivers/gpu/drm/msm/ |
| D | msm_gpummu.c | 14 dma_addr_t pt_base; member
79 dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base, in msm_gpummu_destroy()
101 gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base, in msm_gpummu_new()
114 void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, in msm_gpummu_params() argument
117 dma_addr_t base = to_msm_gpummu(mmu)->pt_base; in msm_gpummu_params()
119 *pt_base = base; in msm_gpummu_params()
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| D | msm_mmu.h | 56 void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
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| /drivers/iommu/ |
| D | exynos-iommu.c | 262 u32 pt_base; /* page table base address (physical) */ member
366 .pt_base = 0x14,
375 .pt_base = 0x0c,
389 .pt_base = 0x0c,
405 .pt_base = 0x800c,
471 u32 pt_base; in __sysmmu_set_ptbase() local
474 pt_base = pgd; in __sysmmu_set_ptbase()
476 pt_base = pgd >> SPAGE_ORDER; in __sysmmu_set_ptbase()
478 writel(pt_base, SYSMMU_REG(data, pt_base)); in __sysmmu_set_ptbase()
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v1_0.c | 56 uint64_t pt_base; in gfxhub_v1_0_init_gart_aperture_regs() local
59 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_0_init_gart_aperture_regs()
61 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_0_init_gart_aperture_regs()
63 gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); in gfxhub_v1_0_init_gart_aperture_regs()
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| D | gfxhub_v1_2.c | 77 uint64_t pt_base; in gfxhub_v1_2_xcc_init_gart_aperture_regs() local
81 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
83 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
85 gfxhub_v1_2_xcc_setup_vm_pt_regs(adev, 0, pt_base, xcc_mask); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
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| D | mmhub_v1_8.c | 78 uint64_t pt_base; in mmhub_v1_8_init_gart_aperture_regs() local
83 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v1_8_init_gart_aperture_regs()
85 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_8_init_gart_aperture_regs()
87 mmhub_v1_8_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v1_8_init_gart_aperture_regs()
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| D | gfxhub_v3_0_3.c | 138 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v3_0_3_init_gart_aperture_regs() local
140 gfxhub_v3_0_3_setup_vm_pt_regs(adev, 0, pt_base); in gfxhub_v3_0_3_init_gart_aperture_regs()
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| D | gfxhub_v2_0.c | 136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v2_0_init_gart_aperture_regs() local
138 gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); in gfxhub_v2_0_init_gart_aperture_regs()
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| D | gfxhub_v3_0.c | 135 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v3_0_init_gart_aperture_regs() local
137 gfxhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base); in gfxhub_v3_0_init_gart_aperture_regs()
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| D | mmhub_v3_0_2.c | 145 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_0_2_init_gart_aperture_regs() local
147 mmhub_v3_0_2_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v3_0_2_init_gart_aperture_regs()
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| D | mmhub_v3_0_1.c | 154 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_0_1_init_gart_aperture_regs() local
156 mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v3_0_1_init_gart_aperture_regs()
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| D | mmhub_v1_7.c | 68 uint64_t pt_base; in mmhub_v1_7_init_gart_aperture_regs() local
71 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo); in mmhub_v1_7_init_gart_aperture_regs()
73 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_7_init_gart_aperture_regs()
75 mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v1_7_init_gart_aperture_regs()
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| D | mmhub_v2_0.c | 203 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v2_0_init_gart_aperture_regs() local
205 mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v2_0_init_gart_aperture_regs()
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| D | mmhub_v2_3.c | 135 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v2_3_init_gart_aperture_regs() local
137 mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v2_3_init_gart_aperture_regs()
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| D | mmhub_v3_0.c | 152 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_0_init_gart_aperture_regs() local
154 mmhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v3_0_init_gart_aperture_regs()
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| D | mmhub_v1_0.c | 70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_0_init_gart_aperture_regs() local
72 mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); in mmhub_v1_0_init_gart_aperture_regs()
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| D | gfxhub_v2_1.c | 139 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v2_1_init_gart_aperture_regs() local
141 gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base); in gfxhub_v2_1_init_gart_aperture_regs()
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| D | mmhub_v9_4.c | 77 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v9_4_init_gart_aperture_regs() local
79 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base); in mmhub_v9_4_init_gart_aperture_regs()
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| /drivers/gpu/drm/msm/adreno/ |
| D | a2xx_gpu.c | 112 dma_addr_t pt_base, tran_error; in a2xx_hw_init() local
116 msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error); in a2xx_hw_init()
158 gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base); in a2xx_hw_init()
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm.c | 1235 u64 pt_base; in mmhub_read_system_context() local
1278 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_read_system_context()
1288 page_table_base.high_part = upper_32_bits(pt_base); in mmhub_read_system_context()
1289 page_table_base.low_part = lower_32_bits(pt_base); in mmhub_read_system_context()
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