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Searched refs:pv (Results 1 – 25 of 25) sorted by relevance

/drivers/tty/hvc/
Dhvsi_lib.c10 static int hvsi_send_packet(struct hvsi_priv *pv, struct hvsi_header *packet) in hvsi_send_packet() argument
12 packet->seqno = cpu_to_be16(atomic_inc_return(&pv->seqno)); in hvsi_send_packet()
15 return pv->put_chars(pv->termno, (char *)packet, packet->len); in hvsi_send_packet()
18 static void hvsi_start_handshake(struct hvsi_priv *pv) in hvsi_start_handshake() argument
23 pv->established = 0; in hvsi_start_handshake()
24 atomic_set(&pv->seqno, 0); in hvsi_start_handshake()
26 pr_devel("HVSI@%x: Handshaking started\n", pv->termno); in hvsi_start_handshake()
32 hvsi_send_packet(pv, &q.hdr); in hvsi_start_handshake()
35 static int hvsi_send_close(struct hvsi_priv *pv) in hvsi_send_close() argument
39 pv->established = 0; in hvsi_send_close()
[all …]
Dhvc_vio.c71 struct hvterm_priv *pv = hvterm_privs[vtermno]; in hvterm_raw_get_chars() local
76 if (WARN_ON(!pv)) in hvterm_raw_get_chars()
79 spin_lock_irqsave(&pv->buf_lock, flags); in hvterm_raw_get_chars()
81 if (pv->left == 0) { in hvterm_raw_get_chars()
82 pv->offset = 0; in hvterm_raw_get_chars()
83 pv->left = hvc_get_chars(pv->termno, pv->buf, count); in hvterm_raw_get_chars()
89 for (i = 1; i < pv->left; ++i) { in hvterm_raw_get_chars()
90 if (pv->buf[i] == 0 && pv->buf[i-1] == '\r') { in hvterm_raw_get_chars()
91 --pv->left; in hvterm_raw_get_chars()
92 if (i < pv->left) { in hvterm_raw_get_chars()
[all …]
Dhvc_opal.c63 struct hvc_opal_priv *pv = hvc_opal_privs[vtermno]; in hvc_opal_hvsi_get_chars() local
65 if (WARN_ON(!pv)) in hvc_opal_hvsi_get_chars()
68 return hvsilib_get_chars(&pv->hvsi, buf, count); in hvc_opal_hvsi_get_chars()
73 struct hvc_opal_priv *pv = hvc_opal_privs[vtermno]; in hvc_opal_hvsi_put_chars() local
75 if (WARN_ON(!pv)) in hvc_opal_hvsi_put_chars()
78 return hvsilib_put_chars(&pv->hvsi, buf, count); in hvc_opal_hvsi_put_chars()
83 struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno]; in hvc_opal_hvsi_open() local
92 return hvsilib_open(&pv->hvsi, hp); in hvc_opal_hvsi_open()
97 struct hvc_opal_priv *pv = hvc_opal_privs[hp->vtermno]; in hvc_opal_hvsi_close() local
101 hvsilib_close(&pv->hvsi, hp); in hvc_opal_hvsi_close()
[all …]
/drivers/macintosh/
Dwindfarm_ad7417_sensor.c38 struct wf_ad7417_priv *pv = sr->priv; in wf_ad7417_temp_get() local
44 mutex_lock(&pv->lock); in wf_ad7417_temp_get()
48 rc = i2c_master_send(pv->i2c, buf, 1); in wf_ad7417_temp_get()
51 rc = i2c_master_recv(pv->i2c, buf, 2); in wf_ad7417_temp_get()
61 mutex_unlock(&pv->lock); in wf_ad7417_temp_get()
65 mutex_unlock(&pv->lock); in wf_ad7417_temp_get()
79 static void wf_ad7417_adc_convert(struct wf_ad7417_priv *pv, in wf_ad7417_adc_convert() argument
84 *value = (raw * (s32)pv->mpu->mdiode + in wf_ad7417_adc_convert()
85 ((s32)pv->mpu->bdiode << 12)) >> 2; in wf_ad7417_adc_convert()
101 struct wf_ad7417_priv *pv = sr->priv; in wf_ad7417_adc_get() local
[all …]
Dwindfarm_fcu_controls.c73 struct wf_fcu_priv *pv = container_of(ref, struct wf_fcu_priv, ref); in wf_fcu_release() local
75 kfree(pv); in wf_fcu_release()
86 static int wf_fcu_read_reg(struct wf_fcu_priv *pv, int reg, in wf_fcu_read_reg() argument
91 mutex_lock(&pv->lock); in wf_fcu_read_reg()
96 nw = i2c_master_send(pv->i2c, buf, 1); in wf_fcu_read_reg()
109 nr = i2c_master_recv(pv->i2c, buf, nb); in wf_fcu_read_reg()
118 mutex_unlock(&pv->lock); in wf_fcu_read_reg()
122 static int wf_fcu_write_reg(struct wf_fcu_priv *pv, int reg, in wf_fcu_write_reg() argument
133 nw = i2c_master_send(pv->i2c, buf, nb); in wf_fcu_write_reg()
147 struct wf_fcu_priv *pv = fan->fcu_priv; in wf_fcu_fan_set_rpm() local
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c144 struct nvkm_pll_vals *pv) in setPLL_single() argument
150 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_single()
164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
169 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); in setPLL_single()
199 struct nvkm_pll_vals *pv) in setPLL_double_highregs() argument
207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; in setPLL_double_highregs()
208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs()
210 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ in setPLL_double_highregs()
216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | in setPLL_double_highregs()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv04.c33 int clk, struct nvkm_pll_vals *pv) in nv04_clk_pll_calc() argument
38 pv->refclk = info->refclk; in nv04_clk_pll_calc()
39 pv->N1 = N1; in nv04_clk_pll_calc()
40 pv->M1 = M1; in nv04_clk_pll_calc()
41 pv->N2 = N2; in nv04_clk_pll_calc()
42 pv->M2 = M2; in nv04_clk_pll_calc()
43 pv->log2P = P; in nv04_clk_pll_calc()
49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
[all …]
/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) in nouveau_hw_pllvals_to_clk() argument
208 if (!pv->M1 || !pv->M2) in nouveau_hw_pllvals_to_clk()
211 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; in nouveau_hw_pllvals_to_clk()
265 struct nvkm_pll_vals pv; in nouveau_hw_fix_bad_vpll() local
270 nouveau_hw_get_pllvals(dev, pll, &pv); in nouveau_hw_fix_bad_vpll()
272 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && in nouveau_hw_fix_bad_vpll()
273 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && in nouveau_hw_fix_bad_vpll()
274 pv.log2P <= pll_lim.max_p) in nouveau_hw_fix_bad_vpll()
280 pv.M1 = pll_lim.vco1.max_m; in nouveau_hw_fix_bad_vpll()
281 pv.N1 = pll_lim.vco1.min_n; in nouveau_hw_fix_bad_vpll()
[all …]
Dcrtc.c126 struct nvkm_pll_vals *pv = &regp->pllvals; in nv_crtc_calc_state_ext() local
134 pv->NM2 = 0; in nv_crtc_calc_state_ext()
150 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) in nv_crtc_calc_state_ext()
164 if (pv->NM2) in nv_crtc_calc_state_ext()
166 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); in nv_crtc_calc_state_ext()
169 pv->N1, pv->M1, pv->log2P); in nv_crtc_calc_state_ext()
/drivers/pwm/
Dpwm-vt8500.c74 unsigned long period_cycles, prescale, pv, dc; in vt8500_pwm_config() local
92 pv = period_cycles / (prescale + 1) - 1; in vt8500_pwm_config()
93 if (pv > 4095) in vt8500_pwm_config()
94 pv = 4095; in vt8500_pwm_config()
101 c = (unsigned long long)pv * duty_ns; in vt8500_pwm_config()
108 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
Dpwm-spear.c82 unsigned long prescale = PWMCR_MIN_PRESCALE, pv, dc; in spear_pwm_config() local
100 pv = div64_u64(val, div); in spear_pwm_config()
105 if (pv < PWMPCR_MIN_PERIOD || dc < PWMDCR_MIN_DUTY) in spear_pwm_config()
112 if (pv > PWMPCR_MAX_PERIOD || dc > PWMDCR_MAX_DUTY) { in spear_pwm_config()
131 spear_pwm_writel(pc, pwm->hwpwm, PWMPCR, pv); in spear_pwm_config()
Dpwm-rz-mtu3.c285 u16 dc, pv; in rz_mtu3_pwm_get_state() local
290 rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRA, &pv, in rz_mtu3_pwm_get_state()
293 rz_mtu3_pwm_read_tgr_registers(priv, RZ_MTU3_TGRC, &pv, in rz_mtu3_pwm_get_state()
300 tmp = NSEC_PER_SEC * (u64)pv << (2 * prescale); in rz_mtu3_pwm_get_state()
328 u16 pv, dc; in rz_mtu3_pwm_config() local
352 pv = rz_mtu3_pwm_calculate_pv_or_dc(period_cycles, prescale); in rz_mtu3_pwm_config()
379 rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRA, pv, in rz_mtu3_pwm_config()
384 rz_mtu3_pwm_write_tgr_registers(priv, RZ_MTU3_TGRC, pv, in rz_mtu3_pwm_config()
Dpwm-pxa.c73 unsigned long period_cycles, prescale, pv, dc; in pxa_pwm_config() local
86 pv = period_cycles / (prescale + 1) - 1; in pxa_pwm_config()
94 dc = mul_u64_u64_div_u64(pv + 1, duty_ns, period_ns); in pxa_pwm_config()
98 writel(pv, pc->mmio_base + offset + PWMPCR); in pxa_pwm_config()
/drivers/isdn/hardware/mISDN/
Dhfcmulti.c885 u_int pv; in hfcmulti_resync() local
914 pv = readl(plx_acc_32); in hfcmulti_resync()
915 pv &= ~PLX_SYNC_O_EN; in hfcmulti_resync()
916 writel(pv, plx_acc_32); in hfcmulti_resync()
936 pv = readl(plx_acc_32); in hfcmulti_resync()
937 pv |= PLX_SYNC_O_EN; in hfcmulti_resync()
938 writel(pv, plx_acc_32); in hfcmulti_resync()
967 pv = readl(plx_acc_32); in hfcmulti_resync()
968 pv |= PLX_SYNC_O_EN; in hfcmulti_resync()
969 writel(pv, plx_acc_32); in hfcmulti_resync()
[all …]
/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_fid.c524 struct mlxsw_sp_fid_port_vid *pv, in mlxsw_sp_fid_port_vid_to_fid_rif_update_one() argument
530 mlxsw_reg_svfa_port_vid_pack(svfa_pl, pv->local_port, true, in mlxsw_sp_fid_port_vid_to_fid_rif_update_one()
531 fid->fid_index, pv->vid, irif_valid, in mlxsw_sp_fid_port_vid_to_fid_rif_update_one()
541 struct mlxsw_sp_fid_port_vid *pv; in mlxsw_sp_fid_vid_to_fid_rif_set() local
551 list_for_each_entry(pv, &fid->port_vid_list, list) { in mlxsw_sp_fid_vid_to_fid_rif_set()
556 if (!mlxsw_sp->fid_core->port_fid_mappings[pv->local_port]) in mlxsw_sp_fid_vid_to_fid_rif_set()
559 err = mlxsw_sp_fid_port_vid_to_fid_rif_update_one(fid, pv, in mlxsw_sp_fid_vid_to_fid_rif_set()
569 list_for_each_entry_continue_reverse(pv, &fid->port_vid_list, list) { in mlxsw_sp_fid_vid_to_fid_rif_set()
570 if (!mlxsw_sp->fid_core->port_fid_mappings[pv->local_port]) in mlxsw_sp_fid_vid_to_fid_rif_set()
573 mlxsw_sp_fid_port_vid_to_fid_rif_update_one(fid, pv, false, 0); in mlxsw_sp_fid_vid_to_fid_rif_set()
[all …]
/drivers/input/touchscreen/
Dili210x.c439 u8 pv[2]; in ili251x_firmware_update_protocol_version() local
443 &pv, sizeof(pv)); in ili251x_firmware_update_protocol_version()
445 memcpy(priv->version_proto, pv, sizeof(pv)); in ili251x_firmware_update_protocol_version()
534 u8 *pv = priv->version_proto; in ili251x_protocol_version_show() local
536 return sysfs_emit(buf, "%02x.%02x\n", pv[0], pv[1]); in ili251x_protocol_version_show()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Dclk.h116 struct nvkm_pll_vals *pv);
117 int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
/drivers/xen/xenbus/
Dxenbus_client.c61 } pv; member
765 node->pv.area = area; in xenbus_map_ring_pv()
796 if (node->pv.area->addr == vaddr) { in xenbus_unmap_ring_pv()
838 free_vm_area(node->pv.area); in xenbus_unmap_ring_pv()
841 node->pv.area, node->nr_handles); in xenbus_unmap_ring_pv()
/drivers/hte/
Dhte-tegra194.c600 u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id; in tegra_hte_read_fifo() local
615 pv = tegra_hte_readl(gs, HTE_TEPCV); in tegra_hte_read_fifo()
617 acv = pv ^ cv; in tegra_hte_read_fifo()
/drivers/nubus/
Dnubus.c69 unsigned long pv = (unsigned long)p; in not_useful() local
71 pv &= 3; in not_useful()
72 if (map & (1 << pv)) in not_useful()
/drivers/misc/
Dfastrpc.c127 u64 pv; /* buffer pointer */ member
974 rpra[i].buf.pv = 0; in fastrpc_get_args()
985 rpra[i].buf.pv = (u64) ctx->args[i].ptr; in fastrpc_get_args()
1012 rpra[i].buf.pv = args - ctx->olaps[oix].offset; in fastrpc_get_args()
1026 void *dst = (void *)(uintptr_t)rpra[i].buf.pv; in fastrpc_get_args()
1080 void *src = (void *)(uintptr_t)rpra[i].buf.pv; in fastrpc_put_args()
/drivers/media/radio/si4713/
Dsi4713.c258 static int si4713_read_property(struct si4713_device *sdev, u16 prop, u32 *pv) in si4713_read_property() argument
280 *pv = compose_u16(val[2], val[3]); in si4713_read_property()
284 __func__, prop, *pv, val[0]); in si4713_read_property()
/drivers/scsi/sym53c8xx_2/
Dsym_glue.c978 static int get_int_arg(char *ptr, int len, u_long *pv) in get_int_arg() argument
982 *pv = simple_strtoul(ptr, &end, 10); in get_int_arg()
/drivers/clk/
Dclk.c5387 u32 pv; in of_clk_get_parent_name() local
5403 of_property_for_each_u32(clkspec.np, "clock-indices", prop, vp, pv) { in of_clk_get_parent_name()
5404 if (index == pv) { in of_clk_get_parent_name()
/drivers/scsi/
Dncr53c8xx.c660 char *pc, *pv; in sym53c8xx__setup() local
668 pv = pc; in sym53c8xx__setup()
669 c = *++pv; in sym53c8xx__setup()
676 val = (int) simple_strtoul(pv, &pe, 0); in sym53c8xx__setup()