Searched refs:r15 (Results 1 – 20 of 20) sorted by relevance
60 */ mov b32 $r15 reg /*65 // In: $r15 error code (see os.h)69 nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)70 mov $r15 171 nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)88 */ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_ENABLE /*89 */ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*92 */ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_CMD_DISABLE /*93 */ gpc_wr32(NV_PGRAPH_GPC0_TPCX_STRAND_CMD, $r15) /*96 */ mov $r15 NV_PGRAPH_GPC0_TPCX_STRAND_INDEX_ALL /*[all …]
52 // In: $r15 error code (see os.h)55 nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15)56 mov $r15 157 nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15)122 extr $r1 $r15 16:20124 and $r15 0x1f125 st b32 D[$r0 + #gpc_count] $r15129 shl b32 $r1 $r15138 mov $r15 2141 mov $r15 0x10[all …]
31 // $r15 data40 mov $r15 E_CMD_OVERFLOW51 st b32 D[$r8 + 0x4] $r1565 // $r15 data79 ld b32 $r15 D[$r9 + 0x4]92 // Out: $r15 value104 nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0)110 // $r15 value113 nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15)155 // $r15 mmio list tail[all …]
246 */ mov b32 reg $r15249 */ mov b32 $r15 reg /*
48 // $r15 - current65 // $r15 - current94 // $r15 - current112 // $r15 - current136 // $r15 - current (kern)186 push $r15187 mov $r15 #proc_kern231 pop $r15245 // $r15 - current279 // $r15 - current[all …]
79 // $r15 - current (memx)123 // $r15 - current (memx)166 // $r15 - current (memx)204 // $r15 - current (memx)217 // $r15 - current (memx)234 // $r15 - current (memx)254 // $r15 - current (memx)267 // $r15 - current (memx)362 // $r15 - current (memx)403 // $r15 - current (memx)[all …]
41 // $r15 - current (idle)49 // $r15 - current (idle)77 cmp b32 $r1 $r15
42 // $r15 - current (perf)53 // $r15 - current (perf)
41 // $r15 - current (test)57 // $r15 - current (test)
64 // $r15 - current (host)93 // $r15 - current (host)132 // $r15 - current (host)
305 // $r15 - current (i2c)389 // $r15 - current (i2c)
46 // $r15 - current
204 u8 r12, r15, r17, r18, r3D, r82, r84, r89; in mxl111sf_config_pin_mux_modes() local218 ret = mxl111sf_read_reg(state, 0x15, &r15); in mxl111sf_config_pin_mux_modes()247 r15 &= ~PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()275 r15 &= ~PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()303 r15 &= ~PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()331 r15 &= ~PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()359 r15 &= ~PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()387 r15 |= PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()415 r15 |= PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()443 r15 &= ~PIN_MUX_I2S_ENABLE_MASK; in mxl111sf_config_pin_mux_modes()[all …]
198 mov $r15 0x61c199 shl b32 $r15 6201 iowrs I[$r15] $r5220 iowrs I[$r15] $r14248 xbit $r15 $r3 0x1e582 shl b32 $r15 $r14 12584 or $r15 $r14588 iowr I[$r6 + 0x000] $r15595 ld b32 $r15 D[$r5 + #ctx_src_xsize]597 mulu $r15 $r11[all …]
117 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ argument134 .radio_pad2g_tune_pus_core0 = r15, \149 r10, r11, r12, r13, r14, r15, r16, r17) \ argument165 .radio_txmix2g_tune_boost_pu_core1 = r15, \
23 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ argument40 .radio_rxtx5a = r15, \
259 r12, r13, r14, r15, r16, r17, r18, r19, r20, r21) \ argument275 .radio_c1_tx_pgapadtn = r15, \
3026 r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \ argument3044 .radio_syn_logen_buf3 = r15, \
179 unsigned char r15; in __load_zsregs() local235 r15 = read_zsreg(channel, R15); in __load_zsregs()236 if (r15 & 0x01) { in __load_zsregs()
173 shl b32 $r15 $r4 1174 cmps b32 $r15 0