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Searched refs:rc_range_params (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c333 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); in dsc_log_pps()
334 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); in dsc_log_pps()
335 …DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_o… in dsc_log_pps()
711 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, in dsc_write_to_registers()
712 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, in dsc_write_to_registers()
713 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
716 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, in dsc_write_to_registers()
717 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, in dsc_write_to_registers()
718 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
719 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, in dsc_write_to_registers()
[all …]
/drivers/gpu/drm/amd/display/dc/dsc/
Drc_calc_dpi.c54 memcpy(&to->rc_range_params, &from->rc_range_params, sizeof(from->rc_range_params)); in copy_pps_fields()
84 dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; in copy_rc_to_cfg()
85 dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i]; in copy_rc_to_cfg()
87 dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; in copy_rc_to_cfg()
/drivers/gpu/drm/display/
Ddrm_dsc_helper.c246 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << in drm_dsc_pps_payload_pack()
248 (dsc_cfg->rc_range_params[i].range_max_qp << in drm_dsc_pps_payload_pack()
250 (dsc_cfg->rc_range_params[i].range_bpg_offset)); in drm_dsc_pps_payload_pack()
338 struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; member
1284 vdsc_cfg->rc_range_params[i].range_min_qp = in drm_dsc_setup_rc_params()
1285 rc_params->rc_range_params[i].range_min_qp; in drm_dsc_setup_rc_params()
1286 vdsc_cfg->rc_range_params[i].range_max_qp = in drm_dsc_setup_rc_params()
1287 rc_params->rc_range_params[i].range_max_qp; in drm_dsc_setup_rc_params()
1292 vdsc_cfg->rc_range_params[i].range_bpg_offset = in drm_dsc_setup_rc_params()
1293 rc_params->rc_range_params[i].range_bpg_offset & in drm_dsc_setup_rc_params()
/drivers/gpu/drm/i915/display/
Dintel_vdsc.c62 vdsc_cfg->rc_range_params[buf].range_min_qp = in intel_vdsc_set_min_max_qp()
64 vdsc_cfg->rc_range_params[buf].range_max_qp = in intel_vdsc_set_min_max_qp()
171 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
211 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
782 (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << in intel_dsc_pps_configure()
784 (vdsc_cfg->rc_range_params[i].range_max_qp << in intel_dsc_pps_configure()
786 (vdsc_cfg->rc_range_params[i].range_min_qp << in intel_dsc_pps_configure()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_dsc.c128 struct drm_dsc_rc_range_parameters *rc = dsc->rc_range_params; in dpu_hw_dsc_config_thresh()
Ddpu_hw_dsc_1_2.c253 rc = dsc->rc_range_params; in dpu_hw_dsc_config_thresh_1_2()