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Searched refs:reg_bit (Results 1 – 8 of 8) sorted by relevance

/drivers/net/ipa/
Dipa_main.c234 val &= ~reg_bit(reg, PA_MASK_EN); in ipa_hardware_config_tx()
255 val = reg_bit(reg, CLKON_MISC); in ipa_hardware_config_clkon()
258 val = reg_bit(reg, CLKON_GLOBAL); in ipa_hardware_config_clkon()
259 val |= reg_bit(reg, GLOBAL_2X_CLK); in ipa_hardware_config_clkon()
282 val &= ~reg_bit(reg, IPA_QMB_SELECT_CONS_EN); in ipa_hardware_config_comp()
283 val &= ~reg_bit(reg, IPA_QMB_SELECT_PROD_EN); in ipa_hardware_config_comp()
284 val &= ~reg_bit(reg, IPA_QMB_SELECT_GLOBAL_EN); in ipa_hardware_config_comp()
286 val |= reg_bit(reg, GSI_MULTI_AXI_MASTERS_DIS); in ipa_hardware_config_comp()
291 val |= reg_bit(reg, GSI_MULTI_INORDER_RD_DIS); in ipa_hardware_config_comp()
292 val |= reg_bit(reg, GSI_MULTI_INORDER_WR_DIS); in ipa_hardware_config_comp()
[all …]
Dipa_table.c366 val = reg_bit(reg, IPV6_ROUTER_HASH); in ipa_table_hash_flush()
367 val |= reg_bit(reg, IPV6_FILTER_HASH); in ipa_table_hash_flush()
368 val |= reg_bit(reg, IPV4_ROUTER_HASH); in ipa_table_hash_flush()
369 val |= reg_bit(reg, IPV4_FILTER_HASH); in ipa_table_hash_flush()
374 val = reg_bit(reg, ROUTER_CACHE); in ipa_table_hash_flush()
375 val |= reg_bit(reg, FILTER_CACHE); in ipa_table_hash_flush()
Dipa_endpoint.c467 mask = reg_bit(reg, field_id); in ipa_endpoint_init_ctrl()
811 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); in ipa_endpoint_init_hdr()
815 val |= reg_bit(reg, HDR_OFST_METADATA_VALID); in ipa_endpoint_init_hdr()
837 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */ in ipa_endpoint_init_hdr_ext()
847 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); in ipa_endpoint_init_hdr_ext()
849 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); in ipa_endpoint_init_hdr_ext()
1022 val |= reg_bit(reg, SW_EOF_ACTIVE); in ipa_endpoint_init_aggr()
1133 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0; in ipa_endpoint_init_hol_block_en()
1278 val |= reg_bit(reg, STATUS_EN); in ipa_endpoint_status()
1644 val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE); in ipa_endpoint_default_route_set()
[all …]
Dreg.h81 static inline u32 reg_bit(const struct reg *reg, u32 field_id) in reg_bit() function
Dipa_uc.c246 val = reg_bit(reg, UC_INTR); in send_uc_command()
Dgsi.c729 val |= reg_bit(reg, EV_INTYPE); in gsi_evt_ring_program()
842 val |= reg_bit(reg, CHTYPE_DIR); in gsi_channel_program()
877 val |= reg_bit(reg, USE_DB_ENG); in gsi_channel_program()
885 val |= reg_bit(reg, USE_ESCAPE_BUF_ONLY); in gsi_channel_program()
891 val |= reg_bit(reg, DB_IN_BYTES); in gsi_channel_program()
1972 iowrite32(reg_bit(reg, INTYPE), gsi->virt + reg_offset(reg)); in gsi_irq_setup()
2076 if (!(val & reg_bit(reg, ENABLED))) { in gsi_setup()
/drivers/perf/arm_cspmu/
Darm_cspmu.c746 u32 reg_id, reg_bit, inten_off, cnten_off; in arm_cspmu_enable_counter() local
749 reg_bit = COUNTER_TO_SET_CLR_BIT(idx); in arm_cspmu_enable_counter()
754 writel(BIT(reg_bit), cspmu->base0 + inten_off); in arm_cspmu_enable_counter()
755 writel(BIT(reg_bit), cspmu->base0 + cnten_off); in arm_cspmu_enable_counter()
760 u32 reg_id, reg_bit, inten_off, cnten_off; in arm_cspmu_disable_counter() local
763 reg_bit = COUNTER_TO_SET_CLR_BIT(idx); in arm_cspmu_disable_counter()
768 writel(BIT(reg_bit), cspmu->base0 + cnten_off); in arm_cspmu_disable_counter()
769 writel(BIT(reg_bit), cspmu->base0 + inten_off); in arm_cspmu_disable_counter()
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
Dhclge_main.c3779 u32 val, reg, reg_bit; in hclge_reset_wait() local
3785 reg_bit = HCLGE_IMP_RESET_BIT; in hclge_reset_wait()
3789 reg_bit = HCLGE_GLOBAL_RESET_BIT; in hclge_reset_wait()
3793 reg_bit = HCLGE_FUN_RST_ING_B; in hclge_reset_wait()
3803 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { in hclge_reset_wait()