Searched refs:reg_ofs (Results 1 – 7 of 7) sorted by relevance
| /drivers/staging/vt6656/ |
| D | mac.c | 80 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_off() argument
87 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_off()
91 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits) in vnt_mac_reg_bits_on() argument
98 return vnt_control_out(priv, MESSAGE_TYPE_WRITE_MASK, reg_ofs, in vnt_mac_reg_bits_on()
102 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word) in vnt_mac_write_word() argument
109 return vnt_control_out(priv, MESSAGE_TYPE_WRITE, reg_ofs, in vnt_mac_write_word()
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| D | mac.h | 362 int vnt_mac_reg_bits_off(struct vnt_private *priv, u8 reg_ofs, u8 bits);
363 int vnt_mac_reg_bits_on(struct vnt_private *priv, u8 reg_ofs, u8 bits);
364 int vnt_mac_write_word(struct vnt_private *priv, u8 reg_ofs, u16 word);
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| /drivers/reset/ |
| D | reset-ma35d1.c | 29 u32 reg_ofs; member
135 data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_restart_handler()
149 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
154 writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
178 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_status()
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| /drivers/gpu/drm/imx/dcss/ |
| D | dcss-ctxld.c | 341 u32 reg_ofs) in dcss_ctxld_write_irqsafe() argument
357 ctx[ctx_id][item_idx].ofs = reg_ofs; in dcss_ctxld_write_irqsafe()
362 u32 val, u32 reg_ofs) in dcss_ctxld_write() argument
365 dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs); in dcss_ctxld_write()
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| D | dcss-dev.h | 117 u32 reg_ofs);
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| /drivers/clk/ |
| D | clk-cdce925.c | 227 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare() local
233 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_prepare()
262 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); in cdce925_pll_prepare()
265 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); in cdce925_pll_prepare()
274 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare() local
277 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); in cdce925_pll_unprepare()
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| /drivers/gpu/drm/bridge/ |
| D | samsung-dsim.c | 403 .reg_ofs = exynos_reg_ofs,
420 .reg_ofs = exynos_reg_ofs,
437 .reg_ofs = exynos_reg_ofs,
451 .reg_ofs = exynos5433_reg_ofs,
466 .reg_ofs = exynos5433_reg_ofs,
481 .reg_ofs = exynos5433_reg_ofs,
523 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
528 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()
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