1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A7790 processor support
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 */
10
11 #include <linux/errno.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/sys_soc.h>
15
16 #include "core.h"
17 #include "sh_pfc.h"
18
19 /*
20 * All pins assigned to GPIO bank 3 can be used for SD interfaces in
21 * which case they support both 3.3V and 1.8V signalling.
22 */
23 #define CPU_ALL_GP(fn, sfx) \
24 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
30
31 #define CPU_ALL_NOGP(fn) \
32 PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
33 PIN_NOGP(IIC0_SDA, "AF15", fn), \
34 PIN_NOGP(IIC0_SCL, "AG15", fn), \
35 PIN_NOGP(IIC3_SDA, "AH15", fn), \
36 PIN_NOGP(IIC3_SCL, "AJ15", fn), \
37 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
38 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
39 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
40 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
41
42 enum {
43 PINMUX_RESERVED = 0,
44
45 PINMUX_DATA_BEGIN,
46 GP_ALL(DATA),
47 PINMUX_DATA_END,
48
49 PINMUX_FUNCTION_BEGIN,
50 GP_ALL(FN),
51
52 /* GPSR0 */
53 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
54 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
55 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
56 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
57 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
58 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
59 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
60 FN_IP3_14_12, FN_IP3_17_15,
61
62 /* GPSR1 */
63 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
64 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
65 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
66 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
67 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
68 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
69 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
70
71 /* GPSR2 */
72 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
73 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
74 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
75 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
76 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
77 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
78 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
79
80 /* GPSR3 */
81 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
82 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
83 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
84 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
85 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
86 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
87 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
88
89 /* GPSR4 */
90 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
91 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
92 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
93 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
94 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
95 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
96 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
97 FN_IP14_15_12, FN_IP14_18_16,
98
99 /* GPSR5 */
100 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
101 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
102 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
103 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
104 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
105 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
106 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
107
108 /* IPSR0 */
109 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
110 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
111 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
112 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
113 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
114 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
115 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
116 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
117 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
118 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
119 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
120 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
121 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
122 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
123
124 /* IPSR1 */
125 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
126 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
127 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
128 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
129 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
130 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
131 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
132 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
133 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
134 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
135 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
136 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
137 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
138 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
139 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
140
141 /* IPSR2 */
142 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
143 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
144 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
145 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
146 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
147 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
148 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
149 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
150 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
151 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
152 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
153
154 /* IPSR3 */
155 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
156 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
157 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
158 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
159 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
160 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
161 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
162 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
163 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
164 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
165 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
166 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
167 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
168
169 /* IPSR4 */
170 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
171 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
172 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
173 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
174 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
175 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
176 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
177 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
178 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
179 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
180 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
181 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
182 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
183 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
184 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
185
186 /* IPSR5 */
187 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
188 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
189 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
190 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
191 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
192 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
193 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
194 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
195 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
196 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
197 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
198 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
199 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
200 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
201 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3,
202 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
203 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
204 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
205 FN_SSI_WS78_B,
206
207 /* IPSR6 */
208 FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B,
209 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
210 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
211 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
212 FN_SSI_WS6_B, FN_SSI_SDATA8_C,
213 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
214 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2,
215 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
216 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
217 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
218 FN_I2C2_SCL_E, FN_ETH_RX_ER,
219 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
220 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
221 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
222 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
223 FN_HRX0_E, FN_STP_ISSYNC_0_B,
224 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
225 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
226 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
227 FN_ETH_REF_CLK, FN_HCTS0_N_E,
228 FN_STP_IVCXO27_1_B, FN_HRX0_F,
229
230 /* IPSR7 */
231 FN_ETH_MDIO, FN_HRTS0_N_E,
232 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
233 FN_HTX0_F, FN_BPFCLK_G,
234 FN_ETH_TX_EN, FN_SIM0_CLK_C,
235 FN_HRTS0_N_F, FN_ETH_MAGIC,
236 FN_SIM0_RST_C, FN_ETH_TXD0,
237 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
238 FN_ETH_MDC, FN_STP_ISD_1_B,
239 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
240 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
241 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
242 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
243 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
244 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
245 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
246 FN_ATACS00_N, FN_AVB_RXD1,
247 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
248
249 /* IPSR8 */
250 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
251 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
252 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
253 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
254 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
255 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
256 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
257 FN_VI1_CLK, FN_AVB_RX_DV,
258 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
259 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
260 FN_SCIFA1_RXD_D, FN_AVB_MDC,
261 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
262 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
263 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
264 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
265 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
266 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
267 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
268
269 /* IPSR9 */
270 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
271 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
272 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
273 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
274 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
275 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
276 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
277 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
278 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
279 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
280 FN_AVB_TX_EN, FN_SD1_CMD,
281 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
282 FN_SD1_DAT0, FN_AVB_TX_CLK,
283 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
284 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
285 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
286 FN_SD1_DAT3, FN_AVB_RXD0,
287 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
288 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
289 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
290 FN_VI3_CLK_B,
291
292 /* IPSR10 */
293 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
294 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
295 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
296 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
297 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
298 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
299 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
300 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
301 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
302 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
303 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
304 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
305 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
306 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
307 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
308 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
309 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
310 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
311 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
312 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
313 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
314 FN_GLO_I0_B, FN_VI3_DATA6_B,
315
316 /* IPSR11 */
317 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
318 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
319 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
320 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
321 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
322 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
323 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
324 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
325 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
326 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
327 FN_FMIN_E, FN_FMIN_F,
328 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
329 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
330 FN_I2C2_SDA_B, FN_MLB_DAT,
331 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
332 FN_SSI_SCK0129, FN_CAN_CLK_B,
333 FN_MOUT0,
334
335 /* IPSR12 */
336 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
337 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
338 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
339 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
340 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
341 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
342 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
343 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
344 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
345 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
346 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
347 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
348 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
349 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
350 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
351 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
352 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
353 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
354 FN_CAN_DEBUGOUT4,
355
356 /* IPSR13 */
357 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
358 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
359 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
360 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
361 FN_BPFCLK_F, FN_SSI_WS6,
362 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
363 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
364 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
365 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
366 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
367 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
368 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
369 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
370 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
371 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
372 FN_BPFCLK_E, FN_SSI_SDATA7_B,
373 FN_FMIN_G, FN_SSI_SDATA8,
374 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
375 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
376 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
377 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
378 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
379
380 /* IPSR14 */
381 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
382 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
383 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
384 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
385 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
386 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
387 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
388 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
389 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
390 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
391 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
392 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
393 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
394 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
395 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
396 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
397 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
398 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
399 FN_HRTS0_N_C,
400
401 /* IPSR15 */
402 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
403 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
404 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
405 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
406 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
407 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
408 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
409 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
410 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
411 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
412 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
413 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
414 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
415 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
416 FN_DU2_DG6, FN_LCDOUT14,
417
418 /* IPSR16 */
419 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
420 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
421 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
422 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
423 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
424 FN_TCLK1_B,
425
426 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
427 FN_SEL_SCIF1_4,
428 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
429 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
430 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
431 FN_SEL_SCIFB1_4,
432 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
433 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
434 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
435 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
436 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
437 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
438 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
439 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
440 FN_SEL_VI3_0, FN_SEL_VI3_1,
441 FN_SEL_VI2_0, FN_SEL_VI2_1,
442 FN_SEL_VI1_0, FN_SEL_VI1_1,
443 FN_SEL_VI0_0, FN_SEL_VI0_1,
444 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
445 FN_SEL_LBS_0, FN_SEL_LBS_1,
446 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
447 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
448 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
449
450 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
451 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
452 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
453 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
454 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
455 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
456 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
457 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
458 FN_SEL_ADI_0, FN_SEL_ADI_1,
459 FN_SEL_SSP_0, FN_SEL_SSP_1,
460 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
461 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
462 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
463 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
464 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
465 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
466 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
467
468 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
469 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
470 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
471 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
472 FN_SEL_IIC2_4,
473 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
474 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
475 FN_SEL_I2C2_4,
476 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
477 PINMUX_FUNCTION_END,
478
479 PINMUX_MARK_BEGIN,
480
481 VI1_DATA7_VI1_B7_MARK,
482
483 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
484 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
485 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
486
487 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
488 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
489 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
490 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
491 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
492 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
493 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
494 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
495 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
496 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
497 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
498 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
499 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
500 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
501
502 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
503 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
504 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
505 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
506 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
507 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
508 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
509 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
510 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
511 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
512 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
513 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
514 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
515 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
516 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
517
518 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
519 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
520 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
521 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
522 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
523 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
524 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
525 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
526 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
527 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
528 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
529
530 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
531 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
532 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
533 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
534 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
535 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
536 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
537 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
538 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
539 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
540 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
541 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
542 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
543
544 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
545 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
546 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
547 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
548 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
549 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
550 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
551 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
552 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
553 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
554 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
555 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
556 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
557 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
558 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
559
560 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
561 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
562 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
563 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
564 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
565 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
566 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
567 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
568 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
569 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
570 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
571 WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
572 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
573 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
574 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
575 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK,
576 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
577 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
578 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
579 SSI_WS78_B_MARK,
580
581 DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK,
582 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
583 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
584 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
585 SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
586 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
587 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK,
588 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
589 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
590 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
591 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
592 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
593 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
594 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
595 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
596 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
597 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
598 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
599 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
600 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
601 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
602
603 ETH_MDIO_MARK, HRTS0_N_E_MARK,
604 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
605 HTX0_F_MARK, BPFCLK_G_MARK,
606 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
607 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
608 SIM0_RST_C_MARK, ETH_TXD0_MARK,
609 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
610 ETH_MDC_MARK, STP_ISD_1_B_MARK,
611 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
612 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
613 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
614 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
615 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
616 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
617 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
618 ATACS00_N_MARK, AVB_RXD1_MARK,
619 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
620
621 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
622 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
623 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
624 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
625 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
626 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
627 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
628 VI1_CLK_MARK, AVB_RX_DV_MARK,
629 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
630 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
631 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
632 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
633 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
634 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
635 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
636 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
637 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
638 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
639
640 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
641 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
642 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
643 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
644 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
645 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
646 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
647 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
648 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
649 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
650 AVB_TX_EN_MARK, SD1_CMD_MARK,
651 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
652 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
653 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
654 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
655 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
656 SD1_DAT3_MARK, AVB_RXD0_MARK,
657 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
658 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
659 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
660 VI3_CLK_B_MARK,
661
662 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
663 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
664 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
665 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
666 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
667 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
668 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
669 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
670 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
671 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
672 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
673 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
674 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
675 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
676 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
677 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
678 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
679 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
680 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
681 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
682 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
683 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
684
685 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
686 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
687 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
688 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
689 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
690 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
691 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
692 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
693 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
694 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
695 FMIN_E_MARK, FMIN_F_MARK,
696 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
697 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
698 I2C2_SDA_B_MARK, MLB_DAT_MARK,
699 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
700 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
701 MOUT0_MARK,
702
703 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
704 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
705 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
706 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
707 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
708 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
709 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
710 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
711 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
712 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
713 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
714 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
715 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
716 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
717 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
718 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
719 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
720 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
721 CAN_DEBUGOUT4_MARK,
722
723 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
724 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
725 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
726 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
727 BPFCLK_F_MARK, SSI_WS6_MARK,
728 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
729 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
730 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
731 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
732 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
733 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
734 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
735 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
736 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
737 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
738 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
739 FMIN_G_MARK, SSI_SDATA8_MARK,
740 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
741 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
742 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
743 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
744 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
745
746 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
747 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
748 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
749 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
750 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
751 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
752 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
753 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
754 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
755 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
756 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
757 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
758 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
759 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
760 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
761 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
762 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
763 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
764 HRTS0_N_C_MARK,
765
766 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
767 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
768 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
769 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
770 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
771 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
772 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
773 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
774 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
775 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
776 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
777 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
778 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
779 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
780 DU2_DG6_MARK, LCDOUT14_MARK,
781
782 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
783 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
784 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
785 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
786 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
787 TCLK1_B_MARK,
788
789 IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
790 IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
791 PINMUX_MARK_END,
792 };
793
794 static const u16 pinmux_data[] = {
795 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
796
797 PINMUX_SINGLE(VI1_DATA7_VI1_B7),
798 PINMUX_SINGLE(USB0_PWEN),
799 PINMUX_SINGLE(USB0_OVC_VBUS),
800 PINMUX_SINGLE(USB2_PWEN),
801 PINMUX_SINGLE(USB2_OVC),
802 PINMUX_SINGLE(AVS1),
803 PINMUX_SINGLE(AVS2),
804 PINMUX_SINGLE(DU_DOTCLKIN0),
805 PINMUX_SINGLE(DU_DOTCLKIN2),
806
807 PINMUX_IPSR_GPSR(IP0_2_0, D0),
808 PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
809 PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
810 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
811 PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
812 PINMUX_IPSR_GPSR(IP0_5_3, D1),
813 PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
814 PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
815 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
816 PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
817 PINMUX_IPSR_GPSR(IP0_8_6, D2),
818 PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
820 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
821 PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
822 PINMUX_IPSR_GPSR(IP0_11_9, D3),
823 PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
824 PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
825 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
826 PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
827 PINMUX_IPSR_GPSR(IP0_15_12, D4),
828 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
829 PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
830 PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
831 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
832 PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
833 PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
834 PINMUX_IPSR_GPSR(IP0_19_16, D5),
835 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
836 PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
837 PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
838 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
839 PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
840 PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
841 PINMUX_IPSR_GPSR(IP0_22_20, D6),
842 PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
843 PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
844 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
845 PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
846 PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
847 PINMUX_IPSR_GPSR(IP0_26_23, D7),
848 PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
849 PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
850 PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
851 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
852 PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
853 PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
854 PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
855 PINMUX_IPSR_GPSR(IP0_30_27, D8),
856 PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
857 PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
858 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
859 PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
860 PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
861
862 PINMUX_IPSR_GPSR(IP1_3_0, D9),
863 PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
864 PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
865 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
866 PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
867 PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
868 PINMUX_IPSR_GPSR(IP1_7_4, D10),
869 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
870 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
871 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
872 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
873 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
874 PINMUX_IPSR_GPSR(IP1_11_8, D11),
875 PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
876 PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
877 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
878 PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
879 PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
880 PINMUX_IPSR_GPSR(IP1_14_12, D12),
881 PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
882 PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
883 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
884 PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
885 PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
886 PINMUX_IPSR_GPSR(IP1_17_15, D13),
887 PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
888 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
889 PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
890 PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
891 PINMUX_IPSR_GPSR(IP1_21_18, D14),
892 PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
893 PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
894 PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
895 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
896 PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
897 PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
898 PINMUX_IPSR_GPSR(IP1_25_22, D15),
899 PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
900 PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
901 PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
902 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
903 PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
904 PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
905 PINMUX_IPSR_GPSR(IP1_27_26, A0),
906 PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
907 PINMUX_IPSR_GPSR(IP1_29_28, A1),
908 PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
909
910 PINMUX_IPSR_GPSR(IP2_2_0, A2),
911 PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
912 PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
913 PINMUX_IPSR_GPSR(IP2_5_3, A3),
914 PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
915 PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
916 PINMUX_IPSR_GPSR(IP2_8_6, A4),
917 PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
918 PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
919 PINMUX_IPSR_GPSR(IP2_11_9, A5),
920 PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
921 PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
922 PINMUX_IPSR_GPSR(IP2_14_12, A6),
923 PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
924 PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
925 PINMUX_IPSR_GPSR(IP2_17_15, A7),
926 PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
927 PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
928 PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
929 PINMUX_IPSR_GPSR(IP2_21_18, A8),
930 PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
931 PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
932 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
933 PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
934 PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
935 PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
936 PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
937 PINMUX_IPSR_GPSR(IP2_25_22, A9),
938 PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
939 PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
940 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
941 PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
942 PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
943 PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
944 PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
945 PINMUX_IPSR_GPSR(IP2_28_26, A10),
946 PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
947 PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
948 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
949 PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
950 PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
951
952 PINMUX_IPSR_GPSR(IP3_3_0, A11),
953 PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
954 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
955 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
956 PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
957 PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
958 PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
959 PINMUX_IPSR_GPSR(IP3_7_4, A12),
960 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
961 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
962 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
963 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
964 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
965 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
966 PINMUX_IPSR_GPSR(IP3_11_8, A13),
967 PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
968 PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
969 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
970 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
971 PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
972 PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
973 PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
974 PINMUX_IPSR_GPSR(IP3_14_12, A14),
975 PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
976 PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
977 PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
978 PINMUX_IPSR_GPSR(IP3_17_15, A15),
979 PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
980 PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
981 PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
982 PINMUX_IPSR_GPSR(IP3_19_18, A16),
983 PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
984 PINMUX_IPSR_GPSR(IP3_22_20, A17),
985 PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
986 PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
987 PINMUX_IPSR_GPSR(IP3_25_23, A18),
988 PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
989 PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
990 PINMUX_IPSR_GPSR(IP3_28_26, A19),
991 PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
992 PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
993 PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
994 PINMUX_IPSR_GPSR(IP3_31_29, A20),
995 PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
996 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
997 PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
998 PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
999
1000 PINMUX_IPSR_GPSR(IP4_2_0, A21),
1001 PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
1002 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
1003 PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
1004 PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1005 PINMUX_IPSR_GPSR(IP4_5_3, A22),
1006 PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1007 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1008 PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1009 PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1010 PINMUX_IPSR_GPSR(IP4_8_6, A23),
1011 PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1012 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1013 PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1014 PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1015 PINMUX_IPSR_GPSR(IP4_11_9, A24),
1016 PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1017 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1018 PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1019 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1020 PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1021 PINMUX_IPSR_GPSR(IP4_14_12, A25),
1022 PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1023 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1024 PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1025 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1026 PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1027 PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1028 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1029 PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1030 PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1031 PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1032 PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1033 PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1034 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1035 PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1036 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1037 PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1038 PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1039 PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1040 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1041 PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1042 PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1043 PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1044 PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1045 PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1046 PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1047 PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1048 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1049 PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1050 PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1051 PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1052 PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1053 PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1054 PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1055 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1056 PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1057 PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1058
1059 PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1060 PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1061 PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1062 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1063 PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1064 PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1065 PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1066 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1067 PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1068 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1069 PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1070 PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1071 PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1072 PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1073 PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1074 PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1075 PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1076 PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1077 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1078 PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1079 PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1080 PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1081 PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1082 PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1083 PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1084 PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1085 PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1086 PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1087 PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1088 PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1089 PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1090 PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1091 PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1092 PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1093 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1094 PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1095 PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1096 PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1097 PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1098 PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1099 PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1100 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1101 PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1102 PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1103 PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1104 PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1105 PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1106 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1107 PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1108 PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1109 PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1110 PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1111 PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1112 PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1113 PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1114 PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1115 PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1116 PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1117 PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1118 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1119 PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1120 PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1121 PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1122 PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1123
1124 PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1125 PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1126 PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1127 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1128 PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1129 PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1130 PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1131 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1132 PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1133 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1134 PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1135 PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1136 PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1137 PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1138 PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1139 PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1140 PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1141 PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1142 PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1143 PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1144 PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1145 PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146 PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147 PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148 PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1149 PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1152 PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1154 PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1155 PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1158 PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159 PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1160 PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1161 PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162 PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164 PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165 PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166 PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1167 PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168 PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169 PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171 PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172 PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173 PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1174 PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175 PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176 PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177 PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178 PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1179 PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180 PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181 PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1182
1183 PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1184 PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185 PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186 PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1188 PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189 PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1190 PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1191 PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192 PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193 PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1194 PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195 PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1196 PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197 PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199 PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1200 PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201 PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203 PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1204 PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205 PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206 PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208 PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1209 PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210 PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213 PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1214 PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1215 PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1216 PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217 PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1218 PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1219 PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1220 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1221 PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1222 PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223 PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1224 PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1225 PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226 PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1227 PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1228
1229 PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230 PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1231 PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1232 PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233 PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1234 PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1235 PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236 PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1237 PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1238 PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239 PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1240 PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1241 PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242 PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1243 PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1244 PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245 PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1246 PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247 PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1248 PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249 PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1250 PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251 PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1253 PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254 PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1256 PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257 PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1259 PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260 PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261 PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1262 PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263 PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264 PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1265 PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1266 PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1267 PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268 PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1269 PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1270 PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271 PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1272 PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273 PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1274
1275 PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1276 PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278 PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1279 PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281 PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1282 PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283 PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284 PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1285 PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286 PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287 PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1288 PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1289 PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290 PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1291 PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292 PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1293 PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294 PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1295 PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296 PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1297 PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1298 PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299 PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1300 PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301 PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1302 PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303 PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1304 PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305 PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1306 PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1307 PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1308 PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1309 PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1311 PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1312 PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1314 PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1315 PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1317 PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1318 PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319 PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1320 PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1321 PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322 PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1323 PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1324 PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325 PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1326 PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1327 PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1328 PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329 PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1330 PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331 PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1332
1333 PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1334 PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1335 PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336 PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1337 PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338 PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1339 PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340 PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1341 PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342 PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1343 PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1344 PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345 PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346 PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347 PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348 PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349 PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1350 PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1351 PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1352 PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353 PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354 PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355 PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356 PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357 PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358 PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1359 PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1360 PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1361 PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362 PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363 PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364 PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366 PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367 PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1368 PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1369 PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1370 PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371 PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375 PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376 PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1377 PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1378 PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1379 PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380 PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381 PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382 PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384 PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1385 PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1386 PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387 PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388 PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389 PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390 PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391 PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392 PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1393 PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1394 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395 PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1396 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1397 PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398 PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1402
1403 PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1404 PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1405 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1407 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1408 PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409 PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410 PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411 PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412 PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413 PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1414 PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1415 PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1416 PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1417 PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1418 PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1419 PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1420 PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1421 PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1422 PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1423 PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1424 PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1425 PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1426 PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1427 PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1428 PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1429 PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1430 PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1431 PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1432 PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433 PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1434 PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435 PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436 PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1437 PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1438 PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439 PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1441 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1442 PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1443 PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1444 PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445 PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1446 PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1447 PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448 PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1449 PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450 PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1451 PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1452 PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453 PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454 PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1455 PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1456 PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457 PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1458
1459 PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1460 PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461 PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1462 PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1463 PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464 PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1465 PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1466 PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467 PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1468 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1469 PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1470 PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1471 PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1472 PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1473 PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1474 PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475 PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476 PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477 PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1478 PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479 PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480 PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1481 PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1482 PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1483 PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484 PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485 PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486 PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1487 PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1488 PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489 PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491 PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1493 PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1494 PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495 PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496 PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497 PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498 PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1499 PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1500 PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501 PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502 PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1503 PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504 PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1506 PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507 PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1508 PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1509 PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510 PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511 PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1512 PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513 PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1514 PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1515
1516 PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1519 PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1520 PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1521 PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1522 PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523 PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1525 PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1526 PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1527 PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1528 PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1529 PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530 PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531 PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532 PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1533 PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1534 PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1535 PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536 PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1537 PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1538 PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1539 PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1540 PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541 PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542 PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1543 PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544 PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1545 PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1546 PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1547 PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548 PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549 PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550 PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1551 PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1552 PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1553 PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1554 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555 PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556 PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557 PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1558 PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1559 PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1560 PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1561 PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1562 PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563 PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1564 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565 PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566 PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567 PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568 PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1569 PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570 PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1571 PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572 PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573 PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1574 PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575 PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1576 PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1577 PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578 PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1579
1580 PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1581 PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583 PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1584 PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585 PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1586 PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1587 PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588 PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589 PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1590 PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1591 PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1592 PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1593 PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594 PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1595 PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596 PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597 PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1598 PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1599 PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1600 PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601 PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602 PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1603 PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1604 PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1605 PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606 PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1607 PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1608 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609 PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1610 PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1611 PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1612 PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613 PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1614 PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615 PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1616 PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1617 PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1618 PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1619 PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1620 PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1621 PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622 PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1623 PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1624 PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625 PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1626 PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627 PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1628 PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1629 PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1630 PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1631 PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1633 PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1634 PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635 PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1636 PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1637 PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638 PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1639 PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1640 PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641 PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1642 PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1643 PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1644
1645 PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646 PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1647 PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1648 PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649 PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1650 PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1651 PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1652 PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653 PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1654 PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1655 PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1656 PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1657 PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658 PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1659 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660 PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1661 PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1662 PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1663 PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1664 PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665 PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1666 PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1667 PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668 PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1669 PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1670 PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1671 PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1673 PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1674 PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675 PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1676 PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1677 PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678 PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1679 PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1680 PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1681 PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682 PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1683 PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1684 PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1685 PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686 PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687 PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1688 PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1689 PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1690 PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1691 PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692 PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1693 PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1694 PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1695 PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1696 PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1697 PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698 PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1699 PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1700 PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1701 PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702 PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1703 PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1704 PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1705
1706 PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707 PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1708 PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1709 PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1710 PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1711 PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712 PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713 PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714 PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715 PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1716 PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1717 PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1718 PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1719 PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1720 PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1721 PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1722 PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1724
1725 PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1726 PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1727 PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1728 PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1729
1730 PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1731 PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1732 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1733 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1734 };
1735
1736 /*
1737 * Pins not associated with a GPIO port.
1738 */
1739 enum {
1740 GP_ASSIGN_LAST(),
1741 NOGP_ALL(),
1742 };
1743
1744 static const struct sh_pfc_pin pinmux_pins[] = {
1745 PINMUX_GPIO_GP_ALL(),
1746 PINMUX_NOGP_ALL(),
1747 };
1748
1749 /* - AUDIO CLOCK ------------------------------------------------------------ */
1750 static const unsigned int audio_clk_a_pins[] = {
1751 /* CLK A */
1752 RCAR_GP_PIN(4, 25),
1753 };
1754 static const unsigned int audio_clk_a_mux[] = {
1755 AUDIO_CLKA_MARK,
1756 };
1757 static const unsigned int audio_clk_b_pins[] = {
1758 /* CLK B */
1759 RCAR_GP_PIN(4, 26),
1760 };
1761 static const unsigned int audio_clk_b_mux[] = {
1762 AUDIO_CLKB_MARK,
1763 };
1764 static const unsigned int audio_clk_c_pins[] = {
1765 /* CLK C */
1766 RCAR_GP_PIN(5, 27),
1767 };
1768 static const unsigned int audio_clk_c_mux[] = {
1769 AUDIO_CLKC_MARK,
1770 };
1771 static const unsigned int audio_clkout_pins[] = {
1772 /* CLK OUT */
1773 RCAR_GP_PIN(5, 16),
1774 };
1775 static const unsigned int audio_clkout_mux[] = {
1776 AUDIO_CLKOUT_MARK,
1777 };
1778 static const unsigned int audio_clkout_b_pins[] = {
1779 /* CLK OUT B */
1780 RCAR_GP_PIN(0, 23),
1781 };
1782 static const unsigned int audio_clkout_b_mux[] = {
1783 AUDIO_CLKOUT_B_MARK,
1784 };
1785 static const unsigned int audio_clkout_c_pins[] = {
1786 /* CLK OUT C */
1787 RCAR_GP_PIN(5, 27),
1788 };
1789 static const unsigned int audio_clkout_c_mux[] = {
1790 AUDIO_CLKOUT_C_MARK,
1791 };
1792 static const unsigned int audio_clkout_d_pins[] = {
1793 /* CLK OUT D */
1794 RCAR_GP_PIN(5, 20),
1795 };
1796 static const unsigned int audio_clkout_d_mux[] = {
1797 AUDIO_CLKOUT_D_MARK,
1798 };
1799 /* - AVB -------------------------------------------------------------------- */
1800 static const unsigned int avb_link_pins[] = {
1801 RCAR_GP_PIN(3, 11),
1802 };
1803 static const unsigned int avb_link_mux[] = {
1804 AVB_LINK_MARK,
1805 };
1806 static const unsigned int avb_magic_pins[] = {
1807 RCAR_GP_PIN(2, 14),
1808 };
1809 static const unsigned int avb_magic_mux[] = {
1810 AVB_MAGIC_MARK,
1811 };
1812 static const unsigned int avb_phy_int_pins[] = {
1813 RCAR_GP_PIN(2, 15),
1814 };
1815 static const unsigned int avb_phy_int_mux[] = {
1816 AVB_PHY_INT_MARK,
1817 };
1818 static const unsigned int avb_mdio_pins[] = {
1819 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1820 };
1821 static const unsigned int avb_mdio_mux[] = {
1822 AVB_MDC_MARK, AVB_MDIO_MARK,
1823 };
1824 static const unsigned int avb_mii_pins[] = {
1825 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1826 RCAR_GP_PIN(0, 11),
1827
1828 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1829 RCAR_GP_PIN(2, 2),
1830
1831 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1832 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1833 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
1834 };
1835 static const unsigned int avb_mii_mux[] = {
1836 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1837 AVB_TXD3_MARK,
1838
1839 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1840 AVB_RXD3_MARK,
1841
1842 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1843 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1844 AVB_TX_CLK_MARK, AVB_COL_MARK,
1845 };
1846 static const unsigned int avb_gmii_pins[] = {
1847 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1848 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1849 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1850
1851 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1852 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1853 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1854
1855 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1856 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1857 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1858 RCAR_GP_PIN(3, 12),
1859 };
1860 static const unsigned int avb_gmii_mux[] = {
1861 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1862 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1863 AVB_TXD6_MARK, AVB_TXD7_MARK,
1864
1865 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1866 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1867 AVB_RXD6_MARK, AVB_RXD7_MARK,
1868
1869 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1870 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1871 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1872 AVB_COL_MARK,
1873 };
1874 /* - CAN0 ----------------------------------------------------------------- */
1875 static const unsigned int can0_data_pins[] = {
1876 /* CAN0 RX */
1877 RCAR_GP_PIN(1, 17),
1878 /* CAN0 TX */
1879 RCAR_GP_PIN(1, 19),
1880 };
1881 static const unsigned int can0_data_mux[] = {
1882 CAN0_RX_MARK,
1883 CAN0_TX_MARK,
1884 };
1885 static const unsigned int can0_data_b_pins[] = {
1886 /* CAN0 RXB */
1887 RCAR_GP_PIN(4, 5),
1888 /* CAN0 TXB */
1889 RCAR_GP_PIN(4, 4),
1890 };
1891 static const unsigned int can0_data_b_mux[] = {
1892 CAN0_RX_B_MARK,
1893 CAN0_TX_B_MARK,
1894 };
1895 static const unsigned int can0_data_c_pins[] = {
1896 /* CAN0 RXC */
1897 RCAR_GP_PIN(4, 26),
1898 /* CAN0 TXC */
1899 RCAR_GP_PIN(4, 23),
1900 };
1901 static const unsigned int can0_data_c_mux[] = {
1902 CAN0_RX_C_MARK,
1903 CAN0_TX_C_MARK,
1904 };
1905 static const unsigned int can0_data_d_pins[] = {
1906 /* CAN0 RXD */
1907 RCAR_GP_PIN(4, 26),
1908 /* CAN0 TXD */
1909 RCAR_GP_PIN(4, 18),
1910 };
1911 static const unsigned int can0_data_d_mux[] = {
1912 CAN0_RX_D_MARK,
1913 CAN0_TX_D_MARK,
1914 };
1915 /* - CAN1 ----------------------------------------------------------------- */
1916 static const unsigned int can1_data_pins[] = {
1917 /* CAN1 RX */
1918 RCAR_GP_PIN(1, 22),
1919 /* CAN1 TX */
1920 RCAR_GP_PIN(1, 18),
1921 };
1922 static const unsigned int can1_data_mux[] = {
1923 CAN1_RX_MARK,
1924 CAN1_TX_MARK,
1925 };
1926 static const unsigned int can1_data_b_pins[] = {
1927 /* CAN1 RXB */
1928 RCAR_GP_PIN(4, 7),
1929 /* CAN1 TXB */
1930 RCAR_GP_PIN(4, 6),
1931 };
1932 static const unsigned int can1_data_b_mux[] = {
1933 CAN1_RX_B_MARK,
1934 CAN1_TX_B_MARK,
1935 };
1936 /* - CAN Clock -------------------------------------------------------------- */
1937 static const unsigned int can_clk_pins[] = {
1938 /* CLK */
1939 RCAR_GP_PIN(1, 21),
1940 };
1941
1942 static const unsigned int can_clk_mux[] = {
1943 CAN_CLK_MARK,
1944 };
1945
1946 static const unsigned int can_clk_b_pins[] = {
1947 /* CLK */
1948 RCAR_GP_PIN(4, 3),
1949 };
1950
1951 static const unsigned int can_clk_b_mux[] = {
1952 CAN_CLK_B_MARK,
1953 };
1954 /* - DU RGB ----------------------------------------------------------------- */
1955 static const unsigned int du_rgb666_pins[] = {
1956 /* R[7:2], G[7:2], B[7:2] */
1957 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1958 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1959 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1960 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1961 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1962 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1963 };
1964 static const unsigned int du_rgb666_mux[] = {
1965 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1966 DU2_DR3_MARK, DU2_DR2_MARK,
1967 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1968 DU2_DG3_MARK, DU2_DG2_MARK,
1969 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1970 DU2_DB3_MARK, DU2_DB2_MARK,
1971 };
1972 static const unsigned int du_rgb888_pins[] = {
1973 /* R[7:0], G[7:0], B[7:0] */
1974 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1975 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1976 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1977 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1978 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1979 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1980 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1981 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1982 };
1983 static const unsigned int du_rgb888_mux[] = {
1984 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1985 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1986 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1987 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1988 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1989 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1990 };
1991 static const unsigned int du_clk_out_0_pins[] = {
1992 /* CLKOUT */
1993 RCAR_GP_PIN(5, 2),
1994 };
1995 static const unsigned int du_clk_out_0_mux[] = {
1996 DU0_DOTCLKOUT_MARK
1997 };
1998 static const unsigned int du_clk_out_1_pins[] = {
1999 /* CLKOUT */
2000 RCAR_GP_PIN(5, 3),
2001 };
2002 static const unsigned int du_clk_out_1_mux[] = {
2003 DU1_DOTCLKOUT_MARK
2004 };
2005 static const unsigned int du_sync_0_pins[] = {
2006 /* VSYNC, HSYNC, DISP */
2007 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
2008 };
2009 static const unsigned int du_sync_0_mux[] = {
2010 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2011 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
2012 };
2013 static const unsigned int du_sync_1_pins[] = {
2014 /* VSYNC, HSYNC, DISP */
2015 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
2016 };
2017 static const unsigned int du_sync_1_mux[] = {
2018 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
2019 DU2_DISP_MARK
2020 };
2021 static const unsigned int du_cde_pins[] = {
2022 /* CDE */
2023 RCAR_GP_PIN(5, 17),
2024 };
2025 static const unsigned int du_cde_mux[] = {
2026 DU2_CDE_MARK,
2027 };
2028 /* - DU0 -------------------------------------------------------------------- */
2029 static const unsigned int du0_clk_in_pins[] = {
2030 /* CLKIN */
2031 RCAR_GP_PIN(5, 26),
2032 };
2033 static const unsigned int du0_clk_in_mux[] = {
2034 DU_DOTCLKIN0_MARK
2035 };
2036 /* - DU1 -------------------------------------------------------------------- */
2037 static const unsigned int du1_clk_in_pins[] = {
2038 /* CLKIN */
2039 RCAR_GP_PIN(5, 27),
2040 };
2041 static const unsigned int du1_clk_in_mux[] = {
2042 DU_DOTCLKIN1_MARK,
2043 };
2044 /* - DU2 -------------------------------------------------------------------- */
2045 static const unsigned int du2_clk_in_pins[] = {
2046 /* CLKIN */
2047 RCAR_GP_PIN(5, 28),
2048 };
2049 static const unsigned int du2_clk_in_mux[] = {
2050 DU_DOTCLKIN2_MARK,
2051 };
2052 /* - ETH -------------------------------------------------------------------- */
2053 static const unsigned int eth_link_pins[] = {
2054 /* LINK */
2055 RCAR_GP_PIN(2, 22),
2056 };
2057 static const unsigned int eth_link_mux[] = {
2058 ETH_LINK_MARK,
2059 };
2060 static const unsigned int eth_magic_pins[] = {
2061 /* MAGIC */
2062 RCAR_GP_PIN(2, 27),
2063 };
2064 static const unsigned int eth_magic_mux[] = {
2065 ETH_MAGIC_MARK,
2066 };
2067 static const unsigned int eth_mdio_pins[] = {
2068 /* MDC, MDIO */
2069 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
2070 };
2071 static const unsigned int eth_mdio_mux[] = {
2072 ETH_MDC_MARK, ETH_MDIO_MARK,
2073 };
2074 static const unsigned int eth_rmii_pins[] = {
2075 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2076 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
2077 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2078 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2079 };
2080 static const unsigned int eth_rmii_mux[] = {
2081 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2082 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2083 };
2084 /* - HSCIF0 ----------------------------------------------------------------- */
2085 static const unsigned int hscif0_data_pins[] = {
2086 /* RX, TX */
2087 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2088 };
2089 static const unsigned int hscif0_data_mux[] = {
2090 HRX0_MARK, HTX0_MARK,
2091 };
2092 static const unsigned int hscif0_clk_pins[] = {
2093 /* SCK */
2094 RCAR_GP_PIN(5, 7),
2095 };
2096 static const unsigned int hscif0_clk_mux[] = {
2097 HSCK0_MARK,
2098 };
2099 static const unsigned int hscif0_ctrl_pins[] = {
2100 /* RTS, CTS */
2101 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2102 };
2103 static const unsigned int hscif0_ctrl_mux[] = {
2104 HRTS0_N_MARK, HCTS0_N_MARK,
2105 };
2106 static const unsigned int hscif0_data_b_pins[] = {
2107 /* RX, TX */
2108 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2109 };
2110 static const unsigned int hscif0_data_b_mux[] = {
2111 HRX0_B_MARK, HTX0_B_MARK,
2112 };
2113 static const unsigned int hscif0_ctrl_b_pins[] = {
2114 /* RTS, CTS */
2115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2116 };
2117 static const unsigned int hscif0_ctrl_b_mux[] = {
2118 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2119 };
2120 static const unsigned int hscif0_data_c_pins[] = {
2121 /* RX, TX */
2122 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2123 };
2124 static const unsigned int hscif0_data_c_mux[] = {
2125 HRX0_C_MARK, HTX0_C_MARK,
2126 };
2127 static const unsigned int hscif0_ctrl_c_pins[] = {
2128 /* RTS, CTS */
2129 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2130 };
2131 static const unsigned int hscif0_ctrl_c_mux[] = {
2132 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2133 };
2134 static const unsigned int hscif0_data_d_pins[] = {
2135 /* RX, TX */
2136 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2137 };
2138 static const unsigned int hscif0_data_d_mux[] = {
2139 HRX0_D_MARK, HTX0_D_MARK,
2140 };
2141 static const unsigned int hscif0_ctrl_d_pins[] = {
2142 /* RTS, CTS */
2143 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2144 };
2145 static const unsigned int hscif0_ctrl_d_mux[] = {
2146 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2147 };
2148 static const unsigned int hscif0_data_e_pins[] = {
2149 /* RX, TX */
2150 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2151 };
2152 static const unsigned int hscif0_data_e_mux[] = {
2153 HRX0_E_MARK, HTX0_E_MARK,
2154 };
2155 static const unsigned int hscif0_ctrl_e_pins[] = {
2156 /* RTS, CTS */
2157 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2158 };
2159 static const unsigned int hscif0_ctrl_e_mux[] = {
2160 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2161 };
2162 static const unsigned int hscif0_data_f_pins[] = {
2163 /* RX, TX */
2164 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2165 };
2166 static const unsigned int hscif0_data_f_mux[] = {
2167 HRX0_F_MARK, HTX0_F_MARK,
2168 };
2169 static const unsigned int hscif0_ctrl_f_pins[] = {
2170 /* RTS, CTS */
2171 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2172 };
2173 static const unsigned int hscif0_ctrl_f_mux[] = {
2174 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2175 };
2176 /* - HSCIF1 ----------------------------------------------------------------- */
2177 static const unsigned int hscif1_data_pins[] = {
2178 /* RX, TX */
2179 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2180 };
2181 static const unsigned int hscif1_data_mux[] = {
2182 HRX1_MARK, HTX1_MARK,
2183 };
2184 static const unsigned int hscif1_clk_pins[] = {
2185 /* SCK */
2186 RCAR_GP_PIN(4, 27),
2187 };
2188 static const unsigned int hscif1_clk_mux[] = {
2189 HSCK1_MARK,
2190 };
2191 static const unsigned int hscif1_ctrl_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2194 };
2195 static const unsigned int hscif1_ctrl_mux[] = {
2196 HRTS1_N_MARK, HCTS1_N_MARK,
2197 };
2198 static const unsigned int hscif1_data_b_pins[] = {
2199 /* RX, TX */
2200 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2201 };
2202 static const unsigned int hscif1_data_b_mux[] = {
2203 HRX1_B_MARK, HTX1_B_MARK,
2204 };
2205 static const unsigned int hscif1_clk_b_pins[] = {
2206 /* SCK */
2207 RCAR_GP_PIN(1, 28),
2208 };
2209 static const unsigned int hscif1_clk_b_mux[] = {
2210 HSCK1_B_MARK,
2211 };
2212 static const unsigned int hscif1_ctrl_b_pins[] = {
2213 /* RTS, CTS */
2214 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2215 };
2216 static const unsigned int hscif1_ctrl_b_mux[] = {
2217 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2218 };
2219 /* - I2C0 ------------------------------------------------------------------- */
2220 static const unsigned int i2c0_pins[] = {
2221 /* SCL, SDA */
2222 PIN_IIC0_SCL, PIN_IIC0_SDA,
2223 };
2224 static const unsigned int i2c0_mux[] = {
2225 I2C0_SCL_MARK, I2C0_SDA_MARK,
2226 };
2227 /* - I2C1 ------------------------------------------------------------------- */
2228 static const unsigned int i2c1_pins[] = {
2229 /* SCL, SDA */
2230 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2231 };
2232 static const unsigned int i2c1_mux[] = {
2233 I2C1_SCL_MARK, I2C1_SDA_MARK,
2234 };
2235 static const unsigned int i2c1_b_pins[] = {
2236 /* SCL, SDA */
2237 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2238 };
2239 static const unsigned int i2c1_b_mux[] = {
2240 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2241 };
2242 static const unsigned int i2c1_c_pins[] = {
2243 /* SCL, SDA */
2244 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2245 };
2246 static const unsigned int i2c1_c_mux[] = {
2247 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2248 };
2249 /* - I2C2 ------------------------------------------------------------------- */
2250 static const unsigned int i2c2_pins[] = {
2251 /* SCL, SDA */
2252 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2253 };
2254 static const unsigned int i2c2_mux[] = {
2255 I2C2_SCL_MARK, I2C2_SDA_MARK,
2256 };
2257 static const unsigned int i2c2_b_pins[] = {
2258 /* SCL, SDA */
2259 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2260 };
2261 static const unsigned int i2c2_b_mux[] = {
2262 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2263 };
2264 static const unsigned int i2c2_c_pins[] = {
2265 /* SCL, SDA */
2266 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2267 };
2268 static const unsigned int i2c2_c_mux[] = {
2269 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2270 };
2271 static const unsigned int i2c2_d_pins[] = {
2272 /* SCL, SDA */
2273 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2274 };
2275 static const unsigned int i2c2_d_mux[] = {
2276 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2277 };
2278 static const unsigned int i2c2_e_pins[] = {
2279 /* SCL, SDA */
2280 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2281 };
2282 static const unsigned int i2c2_e_mux[] = {
2283 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2284 };
2285 /* - I2C3 ------------------------------------------------------------------- */
2286 static const unsigned int i2c3_pins[] = {
2287 /* SCL, SDA */
2288 PIN_IIC3_SCL, PIN_IIC3_SDA,
2289 };
2290 static const unsigned int i2c3_mux[] = {
2291 I2C3_SCL_MARK, I2C3_SDA_MARK,
2292 };
2293 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2294 static const unsigned int iic0_pins[] = {
2295 /* SCL, SDA */
2296 PIN_IIC0_SCL, PIN_IIC0_SDA,
2297 };
2298 static const unsigned int iic0_mux[] = {
2299 IIC0_SCL_MARK, IIC0_SDA_MARK,
2300 };
2301 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2302 static const unsigned int iic1_pins[] = {
2303 /* SCL, SDA */
2304 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2305 };
2306 static const unsigned int iic1_mux[] = {
2307 IIC1_SCL_MARK, IIC1_SDA_MARK,
2308 };
2309 static const unsigned int iic1_b_pins[] = {
2310 /* SCL, SDA */
2311 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2312 };
2313 static const unsigned int iic1_b_mux[] = {
2314 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2315 };
2316 static const unsigned int iic1_c_pins[] = {
2317 /* SCL, SDA */
2318 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2319 };
2320 static const unsigned int iic1_c_mux[] = {
2321 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2322 };
2323 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2324 static const unsigned int iic2_pins[] = {
2325 /* SCL, SDA */
2326 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2327 };
2328 static const unsigned int iic2_mux[] = {
2329 IIC2_SCL_MARK, IIC2_SDA_MARK,
2330 };
2331 static const unsigned int iic2_b_pins[] = {
2332 /* SCL, SDA */
2333 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2334 };
2335 static const unsigned int iic2_b_mux[] = {
2336 IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2337 };
2338 static const unsigned int iic2_c_pins[] = {
2339 /* SCL, SDA */
2340 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2341 };
2342 static const unsigned int iic2_c_mux[] = {
2343 IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2344 };
2345 static const unsigned int iic2_d_pins[] = {
2346 /* SCL, SDA */
2347 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2348 };
2349 static const unsigned int iic2_d_mux[] = {
2350 IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2351 };
2352 static const unsigned int iic2_e_pins[] = {
2353 /* SCL, SDA */
2354 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2355 };
2356 static const unsigned int iic2_e_mux[] = {
2357 IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2358 };
2359 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2360 static const unsigned int iic3_pins[] = {
2361 /* SCL, SDA */
2362 PIN_IIC3_SCL, PIN_IIC3_SDA,
2363 };
2364 static const unsigned int iic3_mux[] = {
2365 IIC3_SCL_MARK, IIC3_SDA_MARK,
2366 };
2367 /* - INTC ------------------------------------------------------------------- */
2368 static const unsigned int intc_irq0_pins[] = {
2369 /* IRQ */
2370 RCAR_GP_PIN(1, 25),
2371 };
2372 static const unsigned int intc_irq0_mux[] = {
2373 IRQ0_MARK,
2374 };
2375 static const unsigned int intc_irq1_pins[] = {
2376 /* IRQ */
2377 RCAR_GP_PIN(1, 27),
2378 };
2379 static const unsigned int intc_irq1_mux[] = {
2380 IRQ1_MARK,
2381 };
2382 static const unsigned int intc_irq2_pins[] = {
2383 /* IRQ */
2384 RCAR_GP_PIN(1, 29),
2385 };
2386 static const unsigned int intc_irq2_mux[] = {
2387 IRQ2_MARK,
2388 };
2389 static const unsigned int intc_irq3_pins[] = {
2390 /* IRQ */
2391 RCAR_GP_PIN(1, 23),
2392 };
2393 static const unsigned int intc_irq3_mux[] = {
2394 IRQ3_MARK,
2395 };
2396
2397 #ifdef CONFIG_PINCTRL_PFC_R8A7790
2398 /* - MLB+ ------------------------------------------------------------------- */
2399 static const unsigned int mlb_3pin_pins[] = {
2400 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2401 };
2402 static const unsigned int mlb_3pin_mux[] = {
2403 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2404 };
2405 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
2406
2407 /* - MMCIF0 ----------------------------------------------------------------- */
2408 static const unsigned int mmc0_data_pins[] = {
2409 /* D[0:7] */
2410 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2411 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2412 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2413 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2414 };
2415 static const unsigned int mmc0_data_mux[] = {
2416 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2417 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2418 };
2419 static const unsigned int mmc0_ctrl_pins[] = {
2420 /* CLK, CMD */
2421 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2422 };
2423 static const unsigned int mmc0_ctrl_mux[] = {
2424 MMC0_CLK_MARK, MMC0_CMD_MARK,
2425 };
2426 /* - MMCIF1 ----------------------------------------------------------------- */
2427 static const unsigned int mmc1_data_pins[] = {
2428 /* D[0:7] */
2429 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2430 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2431 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2432 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2433 };
2434 static const unsigned int mmc1_data_mux[] = {
2435 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2436 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2437 };
2438 static const unsigned int mmc1_ctrl_pins[] = {
2439 /* CLK, CMD */
2440 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2441 };
2442 static const unsigned int mmc1_ctrl_mux[] = {
2443 MMC1_CLK_MARK, MMC1_CMD_MARK,
2444 };
2445 /* - MSIOF0 ----------------------------------------------------------------- */
2446 static const unsigned int msiof0_clk_pins[] = {
2447 /* SCK */
2448 RCAR_GP_PIN(5, 12),
2449 };
2450 static const unsigned int msiof0_clk_mux[] = {
2451 MSIOF0_SCK_MARK,
2452 };
2453 static const unsigned int msiof0_sync_pins[] = {
2454 /* SYNC */
2455 RCAR_GP_PIN(5, 13),
2456 };
2457 static const unsigned int msiof0_sync_mux[] = {
2458 MSIOF0_SYNC_MARK,
2459 };
2460 static const unsigned int msiof0_ss1_pins[] = {
2461 /* SS1 */
2462 RCAR_GP_PIN(5, 14),
2463 };
2464 static const unsigned int msiof0_ss1_mux[] = {
2465 MSIOF0_SS1_MARK,
2466 };
2467 static const unsigned int msiof0_ss2_pins[] = {
2468 /* SS2 */
2469 RCAR_GP_PIN(5, 16),
2470 };
2471 static const unsigned int msiof0_ss2_mux[] = {
2472 MSIOF0_SS2_MARK,
2473 };
2474 static const unsigned int msiof0_rx_pins[] = {
2475 /* RXD */
2476 RCAR_GP_PIN(5, 17),
2477 };
2478 static const unsigned int msiof0_rx_mux[] = {
2479 MSIOF0_RXD_MARK,
2480 };
2481 static const unsigned int msiof0_tx_pins[] = {
2482 /* TXD */
2483 RCAR_GP_PIN(5, 15),
2484 };
2485 static const unsigned int msiof0_tx_mux[] = {
2486 MSIOF0_TXD_MARK,
2487 };
2488
2489 static const unsigned int msiof0_clk_b_pins[] = {
2490 /* SCK */
2491 RCAR_GP_PIN(1, 23),
2492 };
2493 static const unsigned int msiof0_clk_b_mux[] = {
2494 MSIOF0_SCK_B_MARK,
2495 };
2496 static const unsigned int msiof0_ss1_b_pins[] = {
2497 /* SS1 */
2498 RCAR_GP_PIN(1, 12),
2499 };
2500 static const unsigned int msiof0_ss1_b_mux[] = {
2501 MSIOF0_SS1_B_MARK,
2502 };
2503 static const unsigned int msiof0_ss2_b_pins[] = {
2504 /* SS2 */
2505 RCAR_GP_PIN(1, 10),
2506 };
2507 static const unsigned int msiof0_ss2_b_mux[] = {
2508 MSIOF0_SS2_B_MARK,
2509 };
2510 static const unsigned int msiof0_rx_b_pins[] = {
2511 /* RXD */
2512 RCAR_GP_PIN(1, 29),
2513 };
2514 static const unsigned int msiof0_rx_b_mux[] = {
2515 MSIOF0_RXD_B_MARK,
2516 };
2517 static const unsigned int msiof0_tx_b_pins[] = {
2518 /* TXD */
2519 RCAR_GP_PIN(1, 28),
2520 };
2521 static const unsigned int msiof0_tx_b_mux[] = {
2522 MSIOF0_TXD_B_MARK,
2523 };
2524 /* - MSIOF1 ----------------------------------------------------------------- */
2525 static const unsigned int msiof1_clk_pins[] = {
2526 /* SCK */
2527 RCAR_GP_PIN(4, 8),
2528 };
2529 static const unsigned int msiof1_clk_mux[] = {
2530 MSIOF1_SCK_MARK,
2531 };
2532 static const unsigned int msiof1_sync_pins[] = {
2533 /* SYNC */
2534 RCAR_GP_PIN(4, 9),
2535 };
2536 static const unsigned int msiof1_sync_mux[] = {
2537 MSIOF1_SYNC_MARK,
2538 };
2539 static const unsigned int msiof1_ss1_pins[] = {
2540 /* SS1 */
2541 RCAR_GP_PIN(4, 10),
2542 };
2543 static const unsigned int msiof1_ss1_mux[] = {
2544 MSIOF1_SS1_MARK,
2545 };
2546 static const unsigned int msiof1_ss2_pins[] = {
2547 /* SS2 */
2548 RCAR_GP_PIN(4, 11),
2549 };
2550 static const unsigned int msiof1_ss2_mux[] = {
2551 MSIOF1_SS2_MARK,
2552 };
2553 static const unsigned int msiof1_rx_pins[] = {
2554 /* RXD */
2555 RCAR_GP_PIN(4, 13),
2556 };
2557 static const unsigned int msiof1_rx_mux[] = {
2558 MSIOF1_RXD_MARK,
2559 };
2560 static const unsigned int msiof1_tx_pins[] = {
2561 /* TXD */
2562 RCAR_GP_PIN(4, 12),
2563 };
2564 static const unsigned int msiof1_tx_mux[] = {
2565 MSIOF1_TXD_MARK,
2566 };
2567
2568 static const unsigned int msiof1_clk_b_pins[] = {
2569 /* SCK */
2570 RCAR_GP_PIN(1, 16),
2571 };
2572 static const unsigned int msiof1_clk_b_mux[] = {
2573 MSIOF1_SCK_B_MARK,
2574 };
2575 static const unsigned int msiof1_ss1_b_pins[] = {
2576 /* SS1 */
2577 RCAR_GP_PIN(0, 18),
2578 };
2579 static const unsigned int msiof1_ss1_b_mux[] = {
2580 MSIOF1_SS1_B_MARK,
2581 };
2582 static const unsigned int msiof1_ss2_b_pins[] = {
2583 /* SS2 */
2584 RCAR_GP_PIN(0, 19),
2585 };
2586 static const unsigned int msiof1_ss2_b_mux[] = {
2587 MSIOF1_SS2_B_MARK,
2588 };
2589 static const unsigned int msiof1_rx_b_pins[] = {
2590 /* RXD */
2591 RCAR_GP_PIN(1, 17),
2592 };
2593 static const unsigned int msiof1_rx_b_mux[] = {
2594 MSIOF1_RXD_B_MARK,
2595 };
2596 static const unsigned int msiof1_tx_b_pins[] = {
2597 /* TXD */
2598 RCAR_GP_PIN(0, 20),
2599 };
2600 static const unsigned int msiof1_tx_b_mux[] = {
2601 MSIOF1_TXD_B_MARK,
2602 };
2603 /* - MSIOF2 ----------------------------------------------------------------- */
2604 static const unsigned int msiof2_clk_pins[] = {
2605 /* SCK */
2606 RCAR_GP_PIN(0, 27),
2607 };
2608 static const unsigned int msiof2_clk_mux[] = {
2609 MSIOF2_SCK_MARK,
2610 };
2611 static const unsigned int msiof2_sync_pins[] = {
2612 /* SYNC */
2613 RCAR_GP_PIN(0, 26),
2614 };
2615 static const unsigned int msiof2_sync_mux[] = {
2616 MSIOF2_SYNC_MARK,
2617 };
2618 static const unsigned int msiof2_ss1_pins[] = {
2619 /* SS1 */
2620 RCAR_GP_PIN(0, 30),
2621 };
2622 static const unsigned int msiof2_ss1_mux[] = {
2623 MSIOF2_SS1_MARK,
2624 };
2625 static const unsigned int msiof2_ss2_pins[] = {
2626 /* SS2 */
2627 RCAR_GP_PIN(0, 31),
2628 };
2629 static const unsigned int msiof2_ss2_mux[] = {
2630 MSIOF2_SS2_MARK,
2631 };
2632 static const unsigned int msiof2_rx_pins[] = {
2633 /* RXD */
2634 RCAR_GP_PIN(0, 29),
2635 };
2636 static const unsigned int msiof2_rx_mux[] = {
2637 MSIOF2_RXD_MARK,
2638 };
2639 static const unsigned int msiof2_tx_pins[] = {
2640 /* TXD */
2641 RCAR_GP_PIN(0, 28),
2642 };
2643 static const unsigned int msiof2_tx_mux[] = {
2644 MSIOF2_TXD_MARK,
2645 };
2646 /* - MSIOF3 ----------------------------------------------------------------- */
2647 static const unsigned int msiof3_clk_pins[] = {
2648 /* SCK */
2649 RCAR_GP_PIN(5, 4),
2650 };
2651 static const unsigned int msiof3_clk_mux[] = {
2652 MSIOF3_SCK_MARK,
2653 };
2654 static const unsigned int msiof3_sync_pins[] = {
2655 /* SYNC */
2656 RCAR_GP_PIN(4, 30),
2657 };
2658 static const unsigned int msiof3_sync_mux[] = {
2659 MSIOF3_SYNC_MARK,
2660 };
2661 static const unsigned int msiof3_ss1_pins[] = {
2662 /* SS1 */
2663 RCAR_GP_PIN(4, 31),
2664 };
2665 static const unsigned int msiof3_ss1_mux[] = {
2666 MSIOF3_SS1_MARK,
2667 };
2668 static const unsigned int msiof3_ss2_pins[] = {
2669 /* SS2 */
2670 RCAR_GP_PIN(4, 27),
2671 };
2672 static const unsigned int msiof3_ss2_mux[] = {
2673 MSIOF3_SS2_MARK,
2674 };
2675 static const unsigned int msiof3_rx_pins[] = {
2676 /* RXD */
2677 RCAR_GP_PIN(5, 2),
2678 };
2679 static const unsigned int msiof3_rx_mux[] = {
2680 MSIOF3_RXD_MARK,
2681 };
2682 static const unsigned int msiof3_tx_pins[] = {
2683 /* TXD */
2684 RCAR_GP_PIN(5, 3),
2685 };
2686 static const unsigned int msiof3_tx_mux[] = {
2687 MSIOF3_TXD_MARK,
2688 };
2689
2690 static const unsigned int msiof3_clk_b_pins[] = {
2691 /* SCK */
2692 RCAR_GP_PIN(0, 0),
2693 };
2694 static const unsigned int msiof3_clk_b_mux[] = {
2695 MSIOF3_SCK_B_MARK,
2696 };
2697 static const unsigned int msiof3_sync_b_pins[] = {
2698 /* SYNC */
2699 RCAR_GP_PIN(0, 1),
2700 };
2701 static const unsigned int msiof3_sync_b_mux[] = {
2702 MSIOF3_SYNC_B_MARK,
2703 };
2704 static const unsigned int msiof3_rx_b_pins[] = {
2705 /* RXD */
2706 RCAR_GP_PIN(0, 2),
2707 };
2708 static const unsigned int msiof3_rx_b_mux[] = {
2709 MSIOF3_RXD_B_MARK,
2710 };
2711 static const unsigned int msiof3_tx_b_pins[] = {
2712 /* TXD */
2713 RCAR_GP_PIN(0, 3),
2714 };
2715 static const unsigned int msiof3_tx_b_mux[] = {
2716 MSIOF3_TXD_B_MARK,
2717 };
2718 /* - PWM -------------------------------------------------------------------- */
2719 static const unsigned int pwm0_pins[] = {
2720 RCAR_GP_PIN(5, 29),
2721 };
2722 static const unsigned int pwm0_mux[] = {
2723 PWM0_MARK,
2724 };
2725 static const unsigned int pwm0_b_pins[] = {
2726 RCAR_GP_PIN(4, 30),
2727 };
2728 static const unsigned int pwm0_b_mux[] = {
2729 PWM0_B_MARK,
2730 };
2731 static const unsigned int pwm1_pins[] = {
2732 RCAR_GP_PIN(5, 30),
2733 };
2734 static const unsigned int pwm1_mux[] = {
2735 PWM1_MARK,
2736 };
2737 static const unsigned int pwm1_b_pins[] = {
2738 RCAR_GP_PIN(4, 31),
2739 };
2740 static const unsigned int pwm1_b_mux[] = {
2741 PWM1_B_MARK,
2742 };
2743 static const unsigned int pwm2_pins[] = {
2744 RCAR_GP_PIN(5, 31),
2745 };
2746 static const unsigned int pwm2_mux[] = {
2747 PWM2_MARK,
2748 };
2749 static const unsigned int pwm3_pins[] = {
2750 RCAR_GP_PIN(0, 16),
2751 };
2752 static const unsigned int pwm3_mux[] = {
2753 PWM3_MARK,
2754 };
2755 static const unsigned int pwm4_pins[] = {
2756 RCAR_GP_PIN(0, 17),
2757 };
2758 static const unsigned int pwm4_mux[] = {
2759 PWM4_MARK,
2760 };
2761 static const unsigned int pwm5_pins[] = {
2762 RCAR_GP_PIN(0, 18),
2763 };
2764 static const unsigned int pwm5_mux[] = {
2765 PWM5_MARK,
2766 };
2767 static const unsigned int pwm6_pins[] = {
2768 RCAR_GP_PIN(0, 19),
2769 };
2770 static const unsigned int pwm6_mux[] = {
2771 PWM6_MARK,
2772 };
2773 /* - QSPI ------------------------------------------------------------------- */
2774 static const unsigned int qspi_ctrl_pins[] = {
2775 /* SPCLK, SSL */
2776 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2777 };
2778 static const unsigned int qspi_ctrl_mux[] = {
2779 SPCLK_MARK, SSL_MARK,
2780 };
2781 static const unsigned int qspi_data_pins[] = {
2782 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2783 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2784 RCAR_GP_PIN(1, 8),
2785 };
2786 static const unsigned int qspi_data_mux[] = {
2787 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2788 };
2789 /* - SCIF0 ------------------------------------------------------------------ */
2790 static const unsigned int scif0_data_pins[] = {
2791 /* RX, TX */
2792 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2793 };
2794 static const unsigned int scif0_data_mux[] = {
2795 RX0_MARK, TX0_MARK,
2796 };
2797 static const unsigned int scif0_clk_pins[] = {
2798 /* SCK */
2799 RCAR_GP_PIN(4, 27),
2800 };
2801 static const unsigned int scif0_clk_mux[] = {
2802 SCK0_MARK,
2803 };
2804 static const unsigned int scif0_ctrl_pins[] = {
2805 /* RTS, CTS */
2806 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2807 };
2808 static const unsigned int scif0_ctrl_mux[] = {
2809 RTS0_N_MARK, CTS0_N_MARK,
2810 };
2811 static const unsigned int scif0_data_b_pins[] = {
2812 /* RX, TX */
2813 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2814 };
2815 static const unsigned int scif0_data_b_mux[] = {
2816 RX0_B_MARK, TX0_B_MARK,
2817 };
2818 /* - SCIF1 ------------------------------------------------------------------ */
2819 static const unsigned int scif1_data_pins[] = {
2820 /* RX, TX */
2821 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2822 };
2823 static const unsigned int scif1_data_mux[] = {
2824 RX1_MARK, TX1_MARK,
2825 };
2826 static const unsigned int scif1_clk_pins[] = {
2827 /* SCK */
2828 RCAR_GP_PIN(4, 20),
2829 };
2830 static const unsigned int scif1_clk_mux[] = {
2831 SCK1_MARK,
2832 };
2833 static const unsigned int scif1_ctrl_pins[] = {
2834 /* RTS, CTS */
2835 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2836 };
2837 static const unsigned int scif1_ctrl_mux[] = {
2838 RTS1_N_MARK, CTS1_N_MARK,
2839 };
2840 static const unsigned int scif1_data_b_pins[] = {
2841 /* RX, TX */
2842 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2843 };
2844 static const unsigned int scif1_data_b_mux[] = {
2845 RX1_B_MARK, TX1_B_MARK,
2846 };
2847 static const unsigned int scif1_data_c_pins[] = {
2848 /* RX, TX */
2849 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2850 };
2851 static const unsigned int scif1_data_c_mux[] = {
2852 RX1_C_MARK, TX1_C_MARK,
2853 };
2854 static const unsigned int scif1_data_d_pins[] = {
2855 /* RX, TX */
2856 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2857 };
2858 static const unsigned int scif1_data_d_mux[] = {
2859 RX1_D_MARK, TX1_D_MARK,
2860 };
2861 static const unsigned int scif1_clk_d_pins[] = {
2862 /* SCK */
2863 RCAR_GP_PIN(3, 17),
2864 };
2865 static const unsigned int scif1_clk_d_mux[] = {
2866 SCK1_D_MARK,
2867 };
2868 static const unsigned int scif1_data_e_pins[] = {
2869 /* RX, TX */
2870 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2871 };
2872 static const unsigned int scif1_data_e_mux[] = {
2873 RX1_E_MARK, TX1_E_MARK,
2874 };
2875 static const unsigned int scif1_clk_e_pins[] = {
2876 /* SCK */
2877 RCAR_GP_PIN(2, 20),
2878 };
2879 static const unsigned int scif1_clk_e_mux[] = {
2880 SCK1_E_MARK,
2881 };
2882 /* - SCIF2 ------------------------------------------------------------------ */
2883 static const unsigned int scif2_data_pins[] = {
2884 /* RX, TX */
2885 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2886 };
2887 static const unsigned int scif2_data_mux[] = {
2888 RX2_MARK, TX2_MARK,
2889 };
2890 static const unsigned int scif2_clk_pins[] = {
2891 /* SCK */
2892 RCAR_GP_PIN(5, 4),
2893 };
2894 static const unsigned int scif2_clk_mux[] = {
2895 SCK2_MARK,
2896 };
2897 static const unsigned int scif2_data_b_pins[] = {
2898 /* RX, TX */
2899 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2900 };
2901 static const unsigned int scif2_data_b_mux[] = {
2902 RX2_B_MARK, TX2_B_MARK,
2903 };
2904 /* - SCIFA0 ----------------------------------------------------------------- */
2905 static const unsigned int scifa0_data_pins[] = {
2906 /* RXD, TXD */
2907 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2908 };
2909 static const unsigned int scifa0_data_mux[] = {
2910 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2911 };
2912 static const unsigned int scifa0_clk_pins[] = {
2913 /* SCK */
2914 RCAR_GP_PIN(4, 27),
2915 };
2916 static const unsigned int scifa0_clk_mux[] = {
2917 SCIFA0_SCK_MARK,
2918 };
2919 static const unsigned int scifa0_ctrl_pins[] = {
2920 /* RTS, CTS */
2921 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2922 };
2923 static const unsigned int scifa0_ctrl_mux[] = {
2924 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2925 };
2926 static const unsigned int scifa0_data_b_pins[] = {
2927 /* RXD, TXD */
2928 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2929 };
2930 static const unsigned int scifa0_data_b_mux[] = {
2931 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2932 };
2933 static const unsigned int scifa0_clk_b_pins[] = {
2934 /* SCK */
2935 RCAR_GP_PIN(1, 19),
2936 };
2937 static const unsigned int scifa0_clk_b_mux[] = {
2938 SCIFA0_SCK_B_MARK,
2939 };
2940 static const unsigned int scifa0_ctrl_b_pins[] = {
2941 /* RTS, CTS */
2942 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2943 };
2944 static const unsigned int scifa0_ctrl_b_mux[] = {
2945 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2946 };
2947 /* - SCIFA1 ----------------------------------------------------------------- */
2948 static const unsigned int scifa1_data_pins[] = {
2949 /* RXD, TXD */
2950 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2951 };
2952 static const unsigned int scifa1_data_mux[] = {
2953 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2954 };
2955 static const unsigned int scifa1_clk_pins[] = {
2956 /* SCK */
2957 RCAR_GP_PIN(4, 20),
2958 };
2959 static const unsigned int scifa1_clk_mux[] = {
2960 SCIFA1_SCK_MARK,
2961 };
2962 static const unsigned int scifa1_ctrl_pins[] = {
2963 /* RTS, CTS */
2964 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2965 };
2966 static const unsigned int scifa1_ctrl_mux[] = {
2967 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2968 };
2969 static const unsigned int scifa1_data_b_pins[] = {
2970 /* RXD, TXD */
2971 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2972 };
2973 static const unsigned int scifa1_data_b_mux[] = {
2974 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2975 };
2976 static const unsigned int scifa1_clk_b_pins[] = {
2977 /* SCK */
2978 RCAR_GP_PIN(0, 23),
2979 };
2980 static const unsigned int scifa1_clk_b_mux[] = {
2981 SCIFA1_SCK_B_MARK,
2982 };
2983 static const unsigned int scifa1_ctrl_b_pins[] = {
2984 /* RTS, CTS */
2985 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2986 };
2987 static const unsigned int scifa1_ctrl_b_mux[] = {
2988 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2989 };
2990 static const unsigned int scifa1_data_c_pins[] = {
2991 /* RXD, TXD */
2992 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2993 };
2994 static const unsigned int scifa1_data_c_mux[] = {
2995 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2996 };
2997 static const unsigned int scifa1_clk_c_pins[] = {
2998 /* SCK */
2999 RCAR_GP_PIN(0, 8),
3000 };
3001 static const unsigned int scifa1_clk_c_mux[] = {
3002 SCIFA1_SCK_C_MARK,
3003 };
3004 static const unsigned int scifa1_ctrl_c_pins[] = {
3005 /* RTS, CTS */
3006 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
3007 };
3008 static const unsigned int scifa1_ctrl_c_mux[] = {
3009 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
3010 };
3011 static const unsigned int scifa1_data_d_pins[] = {
3012 /* RXD, TXD */
3013 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3014 };
3015 static const unsigned int scifa1_data_d_mux[] = {
3016 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
3017 };
3018 static const unsigned int scifa1_clk_d_pins[] = {
3019 /* SCK */
3020 RCAR_GP_PIN(2, 10),
3021 };
3022 static const unsigned int scifa1_clk_d_mux[] = {
3023 SCIFA1_SCK_D_MARK,
3024 };
3025 static const unsigned int scifa1_ctrl_d_pins[] = {
3026 /* RTS, CTS */
3027 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3028 };
3029 static const unsigned int scifa1_ctrl_d_mux[] = {
3030 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
3031 };
3032 /* - SCIFA2 ----------------------------------------------------------------- */
3033 static const unsigned int scifa2_data_pins[] = {
3034 /* RXD, TXD */
3035 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3036 };
3037 static const unsigned int scifa2_data_mux[] = {
3038 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3039 };
3040 static const unsigned int scifa2_clk_pins[] = {
3041 /* SCK */
3042 RCAR_GP_PIN(5, 4),
3043 };
3044 static const unsigned int scifa2_clk_mux[] = {
3045 SCIFA2_SCK_MARK,
3046 };
3047 static const unsigned int scifa2_ctrl_pins[] = {
3048 /* RTS, CTS */
3049 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3050 };
3051 static const unsigned int scifa2_ctrl_mux[] = {
3052 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3053 };
3054 static const unsigned int scifa2_data_b_pins[] = {
3055 /* RXD, TXD */
3056 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3057 };
3058 static const unsigned int scifa2_data_b_mux[] = {
3059 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3060 };
3061 static const unsigned int scifa2_data_c_pins[] = {
3062 /* RXD, TXD */
3063 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3064 };
3065 static const unsigned int scifa2_data_c_mux[] = {
3066 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3067 };
3068 static const unsigned int scifa2_clk_c_pins[] = {
3069 /* SCK */
3070 RCAR_GP_PIN(5, 29),
3071 };
3072 static const unsigned int scifa2_clk_c_mux[] = {
3073 SCIFA2_SCK_C_MARK,
3074 };
3075 /* - SCIFB0 ----------------------------------------------------------------- */
3076 static const unsigned int scifb0_data_pins[] = {
3077 /* RXD, TXD */
3078 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3079 };
3080 static const unsigned int scifb0_data_mux[] = {
3081 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3082 };
3083 static const unsigned int scifb0_clk_pins[] = {
3084 /* SCK */
3085 RCAR_GP_PIN(4, 8),
3086 };
3087 static const unsigned int scifb0_clk_mux[] = {
3088 SCIFB0_SCK_MARK,
3089 };
3090 static const unsigned int scifb0_ctrl_pins[] = {
3091 /* RTS, CTS */
3092 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3093 };
3094 static const unsigned int scifb0_ctrl_mux[] = {
3095 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3096 };
3097 static const unsigned int scifb0_data_b_pins[] = {
3098 /* RXD, TXD */
3099 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3100 };
3101 static const unsigned int scifb0_data_b_mux[] = {
3102 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3103 };
3104 static const unsigned int scifb0_clk_b_pins[] = {
3105 /* SCK */
3106 RCAR_GP_PIN(3, 9),
3107 };
3108 static const unsigned int scifb0_clk_b_mux[] = {
3109 SCIFB0_SCK_B_MARK,
3110 };
3111 static const unsigned int scifb0_ctrl_b_pins[] = {
3112 /* RTS, CTS */
3113 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3114 };
3115 static const unsigned int scifb0_ctrl_b_mux[] = {
3116 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3117 };
3118 static const unsigned int scifb0_data_c_pins[] = {
3119 /* RXD, TXD */
3120 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3121 };
3122 static const unsigned int scifb0_data_c_mux[] = {
3123 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3124 };
3125 /* - SCIFB1 ----------------------------------------------------------------- */
3126 static const unsigned int scifb1_data_pins[] = {
3127 /* RXD, TXD */
3128 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3129 };
3130 static const unsigned int scifb1_data_mux[] = {
3131 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3132 };
3133 static const unsigned int scifb1_clk_pins[] = {
3134 /* SCK */
3135 RCAR_GP_PIN(4, 14),
3136 };
3137 static const unsigned int scifb1_clk_mux[] = {
3138 SCIFB1_SCK_MARK,
3139 };
3140 static const unsigned int scifb1_ctrl_pins[] = {
3141 /* RTS, CTS */
3142 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3143 };
3144 static const unsigned int scifb1_ctrl_mux[] = {
3145 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3146 };
3147 static const unsigned int scifb1_data_b_pins[] = {
3148 /* RXD, TXD */
3149 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3150 };
3151 static const unsigned int scifb1_data_b_mux[] = {
3152 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3153 };
3154 static const unsigned int scifb1_clk_b_pins[] = {
3155 /* SCK */
3156 RCAR_GP_PIN(3, 1),
3157 };
3158 static const unsigned int scifb1_clk_b_mux[] = {
3159 SCIFB1_SCK_B_MARK,
3160 };
3161 static const unsigned int scifb1_ctrl_b_pins[] = {
3162 /* RTS, CTS */
3163 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3164 };
3165 static const unsigned int scifb1_ctrl_b_mux[] = {
3166 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3167 };
3168 static const unsigned int scifb1_data_c_pins[] = {
3169 /* RXD, TXD */
3170 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3171 };
3172 static const unsigned int scifb1_data_c_mux[] = {
3173 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3174 };
3175 static const unsigned int scifb1_data_d_pins[] = {
3176 /* RXD, TXD */
3177 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3178 };
3179 static const unsigned int scifb1_data_d_mux[] = {
3180 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3181 };
3182 static const unsigned int scifb1_data_e_pins[] = {
3183 /* RXD, TXD */
3184 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3185 };
3186 static const unsigned int scifb1_data_e_mux[] = {
3187 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3188 };
3189 static const unsigned int scifb1_clk_e_pins[] = {
3190 /* SCK */
3191 RCAR_GP_PIN(3, 17),
3192 };
3193 static const unsigned int scifb1_clk_e_mux[] = {
3194 SCIFB1_SCK_E_MARK,
3195 };
3196 static const unsigned int scifb1_data_f_pins[] = {
3197 /* RXD, TXD */
3198 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3199 };
3200 static const unsigned int scifb1_data_f_mux[] = {
3201 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3202 };
3203 static const unsigned int scifb1_data_g_pins[] = {
3204 /* RXD, TXD */
3205 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3206 };
3207 static const unsigned int scifb1_data_g_mux[] = {
3208 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3209 };
3210 static const unsigned int scifb1_clk_g_pins[] = {
3211 /* SCK */
3212 RCAR_GP_PIN(2, 20),
3213 };
3214 static const unsigned int scifb1_clk_g_mux[] = {
3215 SCIFB1_SCK_G_MARK,
3216 };
3217 /* - SCIFB2 ----------------------------------------------------------------- */
3218 static const unsigned int scifb2_data_pins[] = {
3219 /* RXD, TXD */
3220 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3221 };
3222 static const unsigned int scifb2_data_mux[] = {
3223 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3224 };
3225 static const unsigned int scifb2_clk_pins[] = {
3226 /* SCK */
3227 RCAR_GP_PIN(4, 21),
3228 };
3229 static const unsigned int scifb2_clk_mux[] = {
3230 SCIFB2_SCK_MARK,
3231 };
3232 static const unsigned int scifb2_ctrl_pins[] = {
3233 /* RTS, CTS */
3234 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3235 };
3236 static const unsigned int scifb2_ctrl_mux[] = {
3237 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3238 };
3239 static const unsigned int scifb2_data_b_pins[] = {
3240 /* RXD, TXD */
3241 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3242 };
3243 static const unsigned int scifb2_data_b_mux[] = {
3244 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3245 };
3246 static const unsigned int scifb2_clk_b_pins[] = {
3247 /* SCK */
3248 RCAR_GP_PIN(0, 31),
3249 };
3250 static const unsigned int scifb2_clk_b_mux[] = {
3251 SCIFB2_SCK_B_MARK,
3252 };
3253 static const unsigned int scifb2_ctrl_b_pins[] = {
3254 /* RTS, CTS */
3255 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3256 };
3257 static const unsigned int scifb2_ctrl_b_mux[] = {
3258 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3259 };
3260 static const unsigned int scifb2_data_c_pins[] = {
3261 /* RXD, TXD */
3262 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3263 };
3264 static const unsigned int scifb2_data_c_mux[] = {
3265 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3266 };
3267 /* - SCIF Clock ------------------------------------------------------------- */
3268 static const unsigned int scif_clk_pins[] = {
3269 /* SCIF_CLK */
3270 RCAR_GP_PIN(4, 26),
3271 };
3272 static const unsigned int scif_clk_mux[] = {
3273 SCIF_CLK_MARK,
3274 };
3275 static const unsigned int scif_clk_b_pins[] = {
3276 /* SCIF_CLK */
3277 RCAR_GP_PIN(5, 4),
3278 };
3279 static const unsigned int scif_clk_b_mux[] = {
3280 SCIF_CLK_B_MARK,
3281 };
3282 /* - SDHI0 ------------------------------------------------------------------ */
3283 static const unsigned int sdhi0_data_pins[] = {
3284 /* D[0:3] */
3285 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3286 };
3287 static const unsigned int sdhi0_data_mux[] = {
3288 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3289 };
3290 static const unsigned int sdhi0_ctrl_pins[] = {
3291 /* CLK, CMD */
3292 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3293 };
3294 static const unsigned int sdhi0_ctrl_mux[] = {
3295 SD0_CLK_MARK, SD0_CMD_MARK,
3296 };
3297 static const unsigned int sdhi0_cd_pins[] = {
3298 /* CD */
3299 RCAR_GP_PIN(3, 6),
3300 };
3301 static const unsigned int sdhi0_cd_mux[] = {
3302 SD0_CD_MARK,
3303 };
3304 static const unsigned int sdhi0_wp_pins[] = {
3305 /* WP */
3306 RCAR_GP_PIN(3, 7),
3307 };
3308 static const unsigned int sdhi0_wp_mux[] = {
3309 SD0_WP_MARK,
3310 };
3311 /* - SDHI1 ------------------------------------------------------------------ */
3312 static const unsigned int sdhi1_data_pins[] = {
3313 /* D[0:3] */
3314 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3315 };
3316 static const unsigned int sdhi1_data_mux[] = {
3317 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3318 };
3319 static const unsigned int sdhi1_ctrl_pins[] = {
3320 /* CLK, CMD */
3321 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3322 };
3323 static const unsigned int sdhi1_ctrl_mux[] = {
3324 SD1_CLK_MARK, SD1_CMD_MARK,
3325 };
3326 static const unsigned int sdhi1_cd_pins[] = {
3327 /* CD */
3328 RCAR_GP_PIN(3, 14),
3329 };
3330 static const unsigned int sdhi1_cd_mux[] = {
3331 SD1_CD_MARK,
3332 };
3333 static const unsigned int sdhi1_wp_pins[] = {
3334 /* WP */
3335 RCAR_GP_PIN(3, 15),
3336 };
3337 static const unsigned int sdhi1_wp_mux[] = {
3338 SD1_WP_MARK,
3339 };
3340 /* - SDHI2 ------------------------------------------------------------------ */
3341 static const unsigned int sdhi2_data_pins[] = {
3342 /* D[0:3] */
3343 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3344 };
3345 static const unsigned int sdhi2_data_mux[] = {
3346 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3347 };
3348 static const unsigned int sdhi2_ctrl_pins[] = {
3349 /* CLK, CMD */
3350 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3351 };
3352 static const unsigned int sdhi2_ctrl_mux[] = {
3353 SD2_CLK_MARK, SD2_CMD_MARK,
3354 };
3355 static const unsigned int sdhi2_cd_pins[] = {
3356 /* CD */
3357 RCAR_GP_PIN(3, 22),
3358 };
3359 static const unsigned int sdhi2_cd_mux[] = {
3360 SD2_CD_MARK,
3361 };
3362 static const unsigned int sdhi2_wp_pins[] = {
3363 /* WP */
3364 RCAR_GP_PIN(3, 23),
3365 };
3366 static const unsigned int sdhi2_wp_mux[] = {
3367 SD2_WP_MARK,
3368 };
3369 /* - SDHI3 ------------------------------------------------------------------ */
3370 static const unsigned int sdhi3_data_pins[] = {
3371 /* D[0:3] */
3372 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3373 };
3374 static const unsigned int sdhi3_data_mux[] = {
3375 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3376 };
3377 static const unsigned int sdhi3_ctrl_pins[] = {
3378 /* CLK, CMD */
3379 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3380 };
3381 static const unsigned int sdhi3_ctrl_mux[] = {
3382 SD3_CLK_MARK, SD3_CMD_MARK,
3383 };
3384 static const unsigned int sdhi3_cd_pins[] = {
3385 /* CD */
3386 RCAR_GP_PIN(3, 30),
3387 };
3388 static const unsigned int sdhi3_cd_mux[] = {
3389 SD3_CD_MARK,
3390 };
3391 static const unsigned int sdhi3_wp_pins[] = {
3392 /* WP */
3393 RCAR_GP_PIN(3, 31),
3394 };
3395 static const unsigned int sdhi3_wp_mux[] = {
3396 SD3_WP_MARK,
3397 };
3398 /* - SSI -------------------------------------------------------------------- */
3399 static const unsigned int ssi0_data_pins[] = {
3400 /* SDATA0 */
3401 RCAR_GP_PIN(4, 5),
3402 };
3403 static const unsigned int ssi0_data_mux[] = {
3404 SSI_SDATA0_MARK,
3405 };
3406 static const unsigned int ssi0129_ctrl_pins[] = {
3407 /* SCK, WS */
3408 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3409 };
3410 static const unsigned int ssi0129_ctrl_mux[] = {
3411 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3412 };
3413 static const unsigned int ssi1_data_pins[] = {
3414 /* SDATA1 */
3415 RCAR_GP_PIN(4, 6),
3416 };
3417 static const unsigned int ssi1_data_mux[] = {
3418 SSI_SDATA1_MARK,
3419 };
3420 static const unsigned int ssi1_ctrl_pins[] = {
3421 /* SCK, WS */
3422 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3423 };
3424 static const unsigned int ssi1_ctrl_mux[] = {
3425 SSI_SCK1_MARK, SSI_WS1_MARK,
3426 };
3427 static const unsigned int ssi2_data_pins[] = {
3428 /* SDATA2 */
3429 RCAR_GP_PIN(4, 7),
3430 };
3431 static const unsigned int ssi2_data_mux[] = {
3432 SSI_SDATA2_MARK,
3433 };
3434 static const unsigned int ssi2_ctrl_pins[] = {
3435 /* SCK, WS */
3436 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3437 };
3438 static const unsigned int ssi2_ctrl_mux[] = {
3439 SSI_SCK2_MARK, SSI_WS2_MARK,
3440 };
3441 static const unsigned int ssi3_data_pins[] = {
3442 /* SDATA3 */
3443 RCAR_GP_PIN(4, 10),
3444 };
3445 static const unsigned int ssi3_data_mux[] = {
3446 SSI_SDATA3_MARK
3447 };
3448 static const unsigned int ssi34_ctrl_pins[] = {
3449 /* SCK, WS */
3450 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3451 };
3452 static const unsigned int ssi34_ctrl_mux[] = {
3453 SSI_SCK34_MARK, SSI_WS34_MARK,
3454 };
3455 static const unsigned int ssi4_data_pins[] = {
3456 /* SDATA4 */
3457 RCAR_GP_PIN(4, 13),
3458 };
3459 static const unsigned int ssi4_data_mux[] = {
3460 SSI_SDATA4_MARK,
3461 };
3462 static const unsigned int ssi4_ctrl_pins[] = {
3463 /* SCK, WS */
3464 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3465 };
3466 static const unsigned int ssi4_ctrl_mux[] = {
3467 SSI_SCK4_MARK, SSI_WS4_MARK,
3468 };
3469 static const unsigned int ssi5_pins[] = {
3470 /* SDATA5, SCK, WS */
3471 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3472 };
3473 static const unsigned int ssi5_mux[] = {
3474 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3475 };
3476 static const unsigned int ssi5_b_pins[] = {
3477 /* SDATA5, SCK, WS */
3478 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3479 };
3480 static const unsigned int ssi5_b_mux[] = {
3481 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3482 };
3483 static const unsigned int ssi5_c_pins[] = {
3484 /* SDATA5, SCK, WS */
3485 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3486 };
3487 static const unsigned int ssi5_c_mux[] = {
3488 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3489 };
3490 static const unsigned int ssi6_pins[] = {
3491 /* SDATA6, SCK, WS */
3492 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3493 };
3494 static const unsigned int ssi6_mux[] = {
3495 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3496 };
3497 static const unsigned int ssi6_b_pins[] = {
3498 /* SDATA6, SCK, WS */
3499 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3500 };
3501 static const unsigned int ssi6_b_mux[] = {
3502 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3503 };
3504 static const unsigned int ssi7_data_pins[] = {
3505 /* SDATA7 */
3506 RCAR_GP_PIN(4, 22),
3507 };
3508 static const unsigned int ssi7_data_mux[] = {
3509 SSI_SDATA7_MARK,
3510 };
3511 static const unsigned int ssi7_b_data_pins[] = {
3512 /* SDATA7 */
3513 RCAR_GP_PIN(4, 22),
3514 };
3515 static const unsigned int ssi7_b_data_mux[] = {
3516 SSI_SDATA7_B_MARK,
3517 };
3518 static const unsigned int ssi7_c_data_pins[] = {
3519 /* SDATA7 */
3520 RCAR_GP_PIN(1, 26),
3521 };
3522 static const unsigned int ssi7_c_data_mux[] = {
3523 SSI_SDATA7_C_MARK,
3524 };
3525 static const unsigned int ssi78_ctrl_pins[] = {
3526 /* SCK, WS */
3527 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3528 };
3529 static const unsigned int ssi78_ctrl_mux[] = {
3530 SSI_SCK78_MARK, SSI_WS78_MARK,
3531 };
3532 static const unsigned int ssi78_b_ctrl_pins[] = {
3533 /* SCK, WS */
3534 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3535 };
3536 static const unsigned int ssi78_b_ctrl_mux[] = {
3537 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3538 };
3539 static const unsigned int ssi78_c_ctrl_pins[] = {
3540 /* SCK, WS */
3541 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3542 };
3543 static const unsigned int ssi78_c_ctrl_mux[] = {
3544 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3545 };
3546 static const unsigned int ssi8_data_pins[] = {
3547 /* SDATA8 */
3548 RCAR_GP_PIN(4, 23),
3549 };
3550 static const unsigned int ssi8_data_mux[] = {
3551 SSI_SDATA8_MARK,
3552 };
3553 static const unsigned int ssi8_b_data_pins[] = {
3554 /* SDATA8 */
3555 RCAR_GP_PIN(4, 23),
3556 };
3557 static const unsigned int ssi8_b_data_mux[] = {
3558 SSI_SDATA8_B_MARK,
3559 };
3560 static const unsigned int ssi8_c_data_pins[] = {
3561 /* SDATA8 */
3562 RCAR_GP_PIN(1, 27),
3563 };
3564 static const unsigned int ssi8_c_data_mux[] = {
3565 SSI_SDATA8_C_MARK,
3566 };
3567 static const unsigned int ssi9_data_pins[] = {
3568 /* SDATA9 */
3569 RCAR_GP_PIN(4, 24),
3570 };
3571 static const unsigned int ssi9_data_mux[] = {
3572 SSI_SDATA9_MARK,
3573 };
3574 static const unsigned int ssi9_ctrl_pins[] = {
3575 /* SCK, WS */
3576 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3577 };
3578 static const unsigned int ssi9_ctrl_mux[] = {
3579 SSI_SCK9_MARK, SSI_WS9_MARK,
3580 };
3581 /* - TPU0 ------------------------------------------------------------------- */
3582 static const unsigned int tpu0_to0_pins[] = {
3583 /* TO */
3584 RCAR_GP_PIN(0, 20),
3585 };
3586 static const unsigned int tpu0_to0_mux[] = {
3587 TPU0TO0_MARK,
3588 };
3589 static const unsigned int tpu0_to1_pins[] = {
3590 /* TO */
3591 RCAR_GP_PIN(0, 21),
3592 };
3593 static const unsigned int tpu0_to1_mux[] = {
3594 TPU0TO1_MARK,
3595 };
3596 static const unsigned int tpu0_to2_pins[] = {
3597 /* TO */
3598 RCAR_GP_PIN(0, 22),
3599 };
3600 static const unsigned int tpu0_to2_mux[] = {
3601 TPU0TO2_MARK,
3602 };
3603 static const unsigned int tpu0_to3_pins[] = {
3604 /* TO */
3605 RCAR_GP_PIN(0, 23),
3606 };
3607 static const unsigned int tpu0_to3_mux[] = {
3608 TPU0TO3_MARK,
3609 };
3610 /* - USB0 ------------------------------------------------------------------- */
3611 static const unsigned int usb0_pins[] = {
3612 /* OVC/VBUS, PWEN */
3613 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18),
3614 };
3615 static const unsigned int usb0_mux[] = {
3616 USB0_OVC_VBUS_MARK, USB0_PWEN_MARK,
3617 };
3618 /* - USB1 ------------------------------------------------------------------- */
3619 static const unsigned int usb1_pins[] = {
3620 /* PWEN, OVC */
3621 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3622 };
3623 static const unsigned int usb1_mux[] = {
3624 USB1_PWEN_MARK, USB1_OVC_MARK,
3625 };
3626 /* - USB2 ------------------------------------------------------------------- */
3627 static const unsigned int usb2_pins[] = {
3628 /* PWEN, OVC */
3629 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3630 };
3631 static const unsigned int usb2_mux[] = {
3632 USB2_PWEN_MARK, USB2_OVC_MARK,
3633 };
3634 /* - VIN0 ------------------------------------------------------------------- */
3635 static const unsigned int vin0_data_pins[] = {
3636 /* B */
3637 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3638 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3639 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3640 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3641 /* G */
3642 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3643 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3644 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3645 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3646 /* R */
3647 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3648 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3649 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3650 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3651 };
3652 static const unsigned int vin0_data_mux[] = {
3653 /* B */
3654 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3655 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3656 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3657 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3658 /* G */
3659 VI0_G0_MARK, VI0_G1_MARK,
3660 VI0_G2_MARK, VI0_G3_MARK,
3661 VI0_G4_MARK, VI0_G5_MARK,
3662 VI0_G6_MARK, VI0_G7_MARK,
3663 /* R */
3664 VI0_R0_MARK, VI0_R1_MARK,
3665 VI0_R2_MARK, VI0_R3_MARK,
3666 VI0_R4_MARK, VI0_R5_MARK,
3667 VI0_R6_MARK, VI0_R7_MARK,
3668 };
3669 static const unsigned int vin0_data18_pins[] = {
3670 /* B */
3671 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3672 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3673 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3674 /* G */
3675 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3676 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3677 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3678 /* R */
3679 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3680 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3681 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3682 };
3683 static const unsigned int vin0_data18_mux[] = {
3684 /* B */
3685 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3686 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3687 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3688 /* G */
3689 VI0_G2_MARK, VI0_G3_MARK,
3690 VI0_G4_MARK, VI0_G5_MARK,
3691 VI0_G6_MARK, VI0_G7_MARK,
3692 /* R */
3693 VI0_R2_MARK, VI0_R3_MARK,
3694 VI0_R4_MARK, VI0_R5_MARK,
3695 VI0_R6_MARK, VI0_R7_MARK,
3696 };
3697 static const unsigned int vin0_sync_pins[] = {
3698 RCAR_GP_PIN(0, 12), /* HSYNC */
3699 RCAR_GP_PIN(0, 13), /* VSYNC */
3700 };
3701 static const unsigned int vin0_sync_mux[] = {
3702 VI0_HSYNC_N_MARK,
3703 VI0_VSYNC_N_MARK,
3704 };
3705 static const unsigned int vin0_field_pins[] = {
3706 RCAR_GP_PIN(0, 15),
3707 };
3708 static const unsigned int vin0_field_mux[] = {
3709 VI0_FIELD_MARK,
3710 };
3711 static const unsigned int vin0_clkenb_pins[] = {
3712 RCAR_GP_PIN(0, 14),
3713 };
3714 static const unsigned int vin0_clkenb_mux[] = {
3715 VI0_CLKENB_MARK,
3716 };
3717 static const unsigned int vin0_clk_pins[] = {
3718 RCAR_GP_PIN(2, 0),
3719 };
3720 static const unsigned int vin0_clk_mux[] = {
3721 VI0_CLK_MARK,
3722 };
3723 /* - VIN1 ------------------------------------------------------------------- */
3724 static const unsigned int vin1_data_pins[] = {
3725 /* B */
3726 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3727 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3728 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3729 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3730 /* G */
3731 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3732 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3733 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3734 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3735 /* R */
3736 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3737 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3738 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3739 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3740 };
3741 static const unsigned int vin1_data_mux[] = {
3742 /* B */
3743 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3744 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3745 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3746 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3747 /* G */
3748 VI1_G0_MARK, VI1_G1_MARK,
3749 VI1_G2_MARK, VI1_G3_MARK,
3750 VI1_G4_MARK, VI1_G5_MARK,
3751 VI1_G6_MARK, VI1_G7_MARK,
3752 /* R */
3753 VI1_R0_MARK, VI1_R1_MARK,
3754 VI1_R2_MARK, VI1_R3_MARK,
3755 VI1_R4_MARK, VI1_R5_MARK,
3756 VI1_R6_MARK, VI1_R7_MARK,
3757 };
3758 static const unsigned int vin1_data18_pins[] = {
3759 /* B */
3760 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3761 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3762 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3763 /* G */
3764 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3765 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3766 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3767 /* R */
3768 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3769 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3770 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3771 };
3772 static const unsigned int vin1_data18_mux[] = {
3773 /* B */
3774 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3775 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3776 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3777 /* G */
3778 VI1_G2_MARK, VI1_G3_MARK,
3779 VI1_G4_MARK, VI1_G5_MARK,
3780 VI1_G6_MARK, VI1_G7_MARK,
3781 /* R */
3782 VI1_R2_MARK, VI1_R3_MARK,
3783 VI1_R4_MARK, VI1_R5_MARK,
3784 VI1_R6_MARK, VI1_R7_MARK,
3785 };
3786 static const unsigned int vin1_data_b_pins[] = {
3787 /* B */
3788 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3789 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3790 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3791 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3792 /* G */
3793 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3794 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3795 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3796 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3797 /* R */
3798 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3799 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3800 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3801 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3802 };
3803 static const unsigned int vin1_data_b_mux[] = {
3804 /* B */
3805 VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
3806 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3807 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3808 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3809 /* G */
3810 VI1_G0_B_MARK, VI1_G1_B_MARK,
3811 VI1_G2_B_MARK, VI1_G3_B_MARK,
3812 VI1_G4_B_MARK, VI1_G5_B_MARK,
3813 VI1_G6_B_MARK, VI1_G7_B_MARK,
3814 /* R */
3815 VI1_R0_B_MARK, VI1_R1_B_MARK,
3816 VI1_R2_B_MARK, VI1_R3_B_MARK,
3817 VI1_R4_B_MARK, VI1_R5_B_MARK,
3818 VI1_R6_B_MARK, VI1_R7_B_MARK,
3819 };
3820 static const unsigned int vin1_data18_b_pins[] = {
3821 /* B */
3822 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3823 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3824 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3825 /* G */
3826 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3827 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3828 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3829 /* R */
3830 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3831 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3832 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3833 };
3834 static const unsigned int vin1_data18_b_mux[] = {
3835 /* B */
3836 VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
3837 VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
3838 VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK,
3839 /* G */
3840 VI1_G2_B_MARK, VI1_G3_B_MARK,
3841 VI1_G4_B_MARK, VI1_G5_B_MARK,
3842 VI1_G6_B_MARK, VI1_G7_B_MARK,
3843 /* R */
3844 VI1_R2_B_MARK, VI1_R3_B_MARK,
3845 VI1_R4_B_MARK, VI1_R5_B_MARK,
3846 VI1_R6_B_MARK, VI1_R7_B_MARK,
3847 };
3848 static const unsigned int vin1_sync_pins[] = {
3849 RCAR_GP_PIN(1, 24), /* HSYNC */
3850 RCAR_GP_PIN(1, 25), /* VSYNC */
3851 };
3852 static const unsigned int vin1_sync_mux[] = {
3853 VI1_HSYNC_N_MARK,
3854 VI1_VSYNC_N_MARK,
3855 };
3856 static const unsigned int vin1_sync_b_pins[] = {
3857 RCAR_GP_PIN(1, 24), /* HSYNC */
3858 RCAR_GP_PIN(1, 25), /* VSYNC */
3859 };
3860 static const unsigned int vin1_sync_b_mux[] = {
3861 VI1_HSYNC_N_B_MARK,
3862 VI1_VSYNC_N_B_MARK,
3863 };
3864 static const unsigned int vin1_field_pins[] = {
3865 RCAR_GP_PIN(1, 13),
3866 };
3867 static const unsigned int vin1_field_mux[] = {
3868 VI1_FIELD_MARK,
3869 };
3870 static const unsigned int vin1_field_b_pins[] = {
3871 RCAR_GP_PIN(1, 13),
3872 };
3873 static const unsigned int vin1_field_b_mux[] = {
3874 VI1_FIELD_B_MARK,
3875 };
3876 static const unsigned int vin1_clkenb_pins[] = {
3877 RCAR_GP_PIN(1, 26),
3878 };
3879 static const unsigned int vin1_clkenb_mux[] = {
3880 VI1_CLKENB_MARK,
3881 };
3882 static const unsigned int vin1_clkenb_b_pins[] = {
3883 RCAR_GP_PIN(1, 26),
3884 };
3885 static const unsigned int vin1_clkenb_b_mux[] = {
3886 VI1_CLKENB_B_MARK,
3887 };
3888 static const unsigned int vin1_clk_pins[] = {
3889 RCAR_GP_PIN(2, 9),
3890 };
3891 static const unsigned int vin1_clk_mux[] = {
3892 VI1_CLK_MARK,
3893 };
3894 static const unsigned int vin1_clk_b_pins[] = {
3895 RCAR_GP_PIN(3, 15),
3896 };
3897 static const unsigned int vin1_clk_b_mux[] = {
3898 VI1_CLK_B_MARK,
3899 };
3900 /* - VIN2 ----------------------------------------------------------------- */
3901 static const unsigned int vin2_data_pins[] = {
3902 /* B */
3903 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3904 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3905 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3906 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3907 /* G */
3908 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3909 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3910 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3911 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3912 /* R */
3913 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3914 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3915 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3916 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3917 };
3918 static const unsigned int vin2_data_mux[] = {
3919 /* B */
3920 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3921 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3922 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3923 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3924 /* G */
3925 VI2_G0_MARK, VI2_G1_MARK,
3926 VI2_G2_MARK, VI2_G3_MARK,
3927 VI2_G4_MARK, VI2_G5_MARK,
3928 VI2_G6_MARK, VI2_G7_MARK,
3929 /* R */
3930 VI2_R0_MARK, VI2_R1_MARK,
3931 VI2_R2_MARK, VI2_R3_MARK,
3932 VI2_R4_MARK, VI2_R5_MARK,
3933 VI2_R6_MARK, VI2_R7_MARK,
3934 };
3935 static const unsigned int vin2_data18_pins[] = {
3936 /* B */
3937 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3938 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3939 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3940 /* G */
3941 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3942 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3943 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3944 /* R */
3945 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3946 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3947 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3948 };
3949 static const unsigned int vin2_data18_mux[] = {
3950 /* B */
3951 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3952 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3953 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3954 /* G */
3955 VI2_G2_MARK, VI2_G3_MARK,
3956 VI2_G4_MARK, VI2_G5_MARK,
3957 VI2_G6_MARK, VI2_G7_MARK,
3958 /* R */
3959 VI2_R2_MARK, VI2_R3_MARK,
3960 VI2_R4_MARK, VI2_R5_MARK,
3961 VI2_R6_MARK, VI2_R7_MARK,
3962 };
3963 static const unsigned int vin2_sync_pins[] = {
3964 RCAR_GP_PIN(1, 16), /* HSYNC */
3965 RCAR_GP_PIN(1, 21), /* VSYNC */
3966 };
3967 static const unsigned int vin2_sync_mux[] = {
3968 VI2_HSYNC_N_MARK,
3969 VI2_VSYNC_N_MARK,
3970 };
3971 static const unsigned int vin2_field_pins[] = {
3972 RCAR_GP_PIN(1, 9),
3973 };
3974 static const unsigned int vin2_field_mux[] = {
3975 VI2_FIELD_MARK,
3976 };
3977 static const unsigned int vin2_clkenb_pins[] = {
3978 RCAR_GP_PIN(1, 8),
3979 };
3980 static const unsigned int vin2_clkenb_mux[] = {
3981 VI2_CLKENB_MARK,
3982 };
3983 static const unsigned int vin2_clk_pins[] = {
3984 RCAR_GP_PIN(1, 11),
3985 };
3986 static const unsigned int vin2_clk_mux[] = {
3987 VI2_CLK_MARK,
3988 };
3989 /* - VIN3 ----------------------------------------------------------------- */
3990 static const unsigned int vin3_data8_pins[] = {
3991 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3992 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3993 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3994 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3995 };
3996 static const unsigned int vin3_data8_mux[] = {
3997 VI3_DATA0_MARK, VI3_DATA1_MARK,
3998 VI3_DATA2_MARK, VI3_DATA3_MARK,
3999 VI3_DATA4_MARK, VI3_DATA5_MARK,
4000 VI3_DATA6_MARK, VI3_DATA7_MARK,
4001 };
4002 static const unsigned int vin3_sync_pins[] = {
4003 RCAR_GP_PIN(1, 16), /* HSYNC */
4004 RCAR_GP_PIN(1, 17), /* VSYNC */
4005 };
4006 static const unsigned int vin3_sync_mux[] = {
4007 VI3_HSYNC_N_MARK,
4008 VI3_VSYNC_N_MARK,
4009 };
4010 static const unsigned int vin3_field_pins[] = {
4011 RCAR_GP_PIN(1, 15),
4012 };
4013 static const unsigned int vin3_field_mux[] = {
4014 VI3_FIELD_MARK,
4015 };
4016 static const unsigned int vin3_clkenb_pins[] = {
4017 RCAR_GP_PIN(1, 14),
4018 };
4019 static const unsigned int vin3_clkenb_mux[] = {
4020 VI3_CLKENB_MARK,
4021 };
4022 static const unsigned int vin3_clk_pins[] = {
4023 RCAR_GP_PIN(1, 23),
4024 };
4025 static const unsigned int vin3_clk_mux[] = {
4026 VI3_CLK_MARK,
4027 };
4028
4029 static const struct {
4030 struct sh_pfc_pin_group common[311];
4031 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4032 struct sh_pfc_pin_group automotive[1];
4033 #endif
4034 } pinmux_groups = {
4035 .common = {
4036 SH_PFC_PIN_GROUP(audio_clk_a),
4037 SH_PFC_PIN_GROUP(audio_clk_b),
4038 SH_PFC_PIN_GROUP(audio_clk_c),
4039 SH_PFC_PIN_GROUP(audio_clkout),
4040 SH_PFC_PIN_GROUP(audio_clkout_b),
4041 SH_PFC_PIN_GROUP(audio_clkout_c),
4042 SH_PFC_PIN_GROUP(audio_clkout_d),
4043 SH_PFC_PIN_GROUP(avb_link),
4044 SH_PFC_PIN_GROUP(avb_magic),
4045 SH_PFC_PIN_GROUP(avb_phy_int),
4046 SH_PFC_PIN_GROUP(avb_mdio),
4047 SH_PFC_PIN_GROUP(avb_mii),
4048 SH_PFC_PIN_GROUP(avb_gmii),
4049 SH_PFC_PIN_GROUP(can0_data),
4050 SH_PFC_PIN_GROUP(can0_data_b),
4051 SH_PFC_PIN_GROUP(can0_data_c),
4052 SH_PFC_PIN_GROUP(can0_data_d),
4053 SH_PFC_PIN_GROUP(can1_data),
4054 SH_PFC_PIN_GROUP(can1_data_b),
4055 SH_PFC_PIN_GROUP(can_clk),
4056 SH_PFC_PIN_GROUP(can_clk_b),
4057 SH_PFC_PIN_GROUP(du_rgb666),
4058 SH_PFC_PIN_GROUP(du_rgb888),
4059 SH_PFC_PIN_GROUP(du_clk_out_0),
4060 SH_PFC_PIN_GROUP(du_clk_out_1),
4061 SH_PFC_PIN_GROUP(du_sync_0),
4062 SH_PFC_PIN_GROUP(du_sync_1),
4063 SH_PFC_PIN_GROUP(du_cde),
4064 SH_PFC_PIN_GROUP(du0_clk_in),
4065 SH_PFC_PIN_GROUP(du1_clk_in),
4066 SH_PFC_PIN_GROUP(du2_clk_in),
4067 SH_PFC_PIN_GROUP(eth_link),
4068 SH_PFC_PIN_GROUP(eth_magic),
4069 SH_PFC_PIN_GROUP(eth_mdio),
4070 SH_PFC_PIN_GROUP(eth_rmii),
4071 SH_PFC_PIN_GROUP(hscif0_data),
4072 SH_PFC_PIN_GROUP(hscif0_clk),
4073 SH_PFC_PIN_GROUP(hscif0_ctrl),
4074 SH_PFC_PIN_GROUP(hscif0_data_b),
4075 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4076 SH_PFC_PIN_GROUP(hscif0_data_c),
4077 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
4078 SH_PFC_PIN_GROUP(hscif0_data_d),
4079 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
4080 SH_PFC_PIN_GROUP(hscif0_data_e),
4081 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
4082 SH_PFC_PIN_GROUP(hscif0_data_f),
4083 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
4084 SH_PFC_PIN_GROUP(hscif1_data),
4085 SH_PFC_PIN_GROUP(hscif1_clk),
4086 SH_PFC_PIN_GROUP(hscif1_ctrl),
4087 SH_PFC_PIN_GROUP(hscif1_data_b),
4088 SH_PFC_PIN_GROUP(hscif1_clk_b),
4089 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4090 SH_PFC_PIN_GROUP(i2c0),
4091 SH_PFC_PIN_GROUP(i2c1),
4092 SH_PFC_PIN_GROUP(i2c1_b),
4093 SH_PFC_PIN_GROUP(i2c1_c),
4094 SH_PFC_PIN_GROUP(i2c2),
4095 SH_PFC_PIN_GROUP(i2c2_b),
4096 SH_PFC_PIN_GROUP(i2c2_c),
4097 SH_PFC_PIN_GROUP(i2c2_d),
4098 SH_PFC_PIN_GROUP(i2c2_e),
4099 SH_PFC_PIN_GROUP(i2c3),
4100 SH_PFC_PIN_GROUP(iic0),
4101 SH_PFC_PIN_GROUP(iic1),
4102 SH_PFC_PIN_GROUP(iic1_b),
4103 SH_PFC_PIN_GROUP(iic1_c),
4104 SH_PFC_PIN_GROUP(iic2),
4105 SH_PFC_PIN_GROUP(iic2_b),
4106 SH_PFC_PIN_GROUP(iic2_c),
4107 SH_PFC_PIN_GROUP(iic2_d),
4108 SH_PFC_PIN_GROUP(iic2_e),
4109 SH_PFC_PIN_GROUP(iic3),
4110 SH_PFC_PIN_GROUP(intc_irq0),
4111 SH_PFC_PIN_GROUP(intc_irq1),
4112 SH_PFC_PIN_GROUP(intc_irq2),
4113 SH_PFC_PIN_GROUP(intc_irq3),
4114 BUS_DATA_PIN_GROUP(mmc0_data, 1),
4115 BUS_DATA_PIN_GROUP(mmc0_data, 4),
4116 BUS_DATA_PIN_GROUP(mmc0_data, 8),
4117 SH_PFC_PIN_GROUP(mmc0_ctrl),
4118 BUS_DATA_PIN_GROUP(mmc1_data, 1),
4119 BUS_DATA_PIN_GROUP(mmc1_data, 4),
4120 BUS_DATA_PIN_GROUP(mmc1_data, 8),
4121 SH_PFC_PIN_GROUP(mmc1_ctrl),
4122 SH_PFC_PIN_GROUP(msiof0_clk),
4123 SH_PFC_PIN_GROUP(msiof0_sync),
4124 SH_PFC_PIN_GROUP(msiof0_ss1),
4125 SH_PFC_PIN_GROUP(msiof0_ss2),
4126 SH_PFC_PIN_GROUP(msiof0_rx),
4127 SH_PFC_PIN_GROUP(msiof0_tx),
4128 SH_PFC_PIN_GROUP(msiof0_clk_b),
4129 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4130 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4131 SH_PFC_PIN_GROUP(msiof0_rx_b),
4132 SH_PFC_PIN_GROUP(msiof0_tx_b),
4133 SH_PFC_PIN_GROUP(msiof1_clk),
4134 SH_PFC_PIN_GROUP(msiof1_sync),
4135 SH_PFC_PIN_GROUP(msiof1_ss1),
4136 SH_PFC_PIN_GROUP(msiof1_ss2),
4137 SH_PFC_PIN_GROUP(msiof1_rx),
4138 SH_PFC_PIN_GROUP(msiof1_tx),
4139 SH_PFC_PIN_GROUP(msiof1_clk_b),
4140 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4141 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4142 SH_PFC_PIN_GROUP(msiof1_rx_b),
4143 SH_PFC_PIN_GROUP(msiof1_tx_b),
4144 SH_PFC_PIN_GROUP(msiof2_clk),
4145 SH_PFC_PIN_GROUP(msiof2_sync),
4146 SH_PFC_PIN_GROUP(msiof2_ss1),
4147 SH_PFC_PIN_GROUP(msiof2_ss2),
4148 SH_PFC_PIN_GROUP(msiof2_rx),
4149 SH_PFC_PIN_GROUP(msiof2_tx),
4150 SH_PFC_PIN_GROUP(msiof3_clk),
4151 SH_PFC_PIN_GROUP(msiof3_sync),
4152 SH_PFC_PIN_GROUP(msiof3_ss1),
4153 SH_PFC_PIN_GROUP(msiof3_ss2),
4154 SH_PFC_PIN_GROUP(msiof3_rx),
4155 SH_PFC_PIN_GROUP(msiof3_tx),
4156 SH_PFC_PIN_GROUP(msiof3_clk_b),
4157 SH_PFC_PIN_GROUP(msiof3_sync_b),
4158 SH_PFC_PIN_GROUP(msiof3_rx_b),
4159 SH_PFC_PIN_GROUP(msiof3_tx_b),
4160 SH_PFC_PIN_GROUP(pwm0),
4161 SH_PFC_PIN_GROUP(pwm0_b),
4162 SH_PFC_PIN_GROUP(pwm1),
4163 SH_PFC_PIN_GROUP(pwm1_b),
4164 SH_PFC_PIN_GROUP(pwm2),
4165 SH_PFC_PIN_GROUP(pwm3),
4166 SH_PFC_PIN_GROUP(pwm4),
4167 SH_PFC_PIN_GROUP(pwm5),
4168 SH_PFC_PIN_GROUP(pwm6),
4169 SH_PFC_PIN_GROUP(qspi_ctrl),
4170 BUS_DATA_PIN_GROUP(qspi_data, 2),
4171 BUS_DATA_PIN_GROUP(qspi_data, 4),
4172 SH_PFC_PIN_GROUP(scif0_data),
4173 SH_PFC_PIN_GROUP(scif0_clk),
4174 SH_PFC_PIN_GROUP(scif0_ctrl),
4175 SH_PFC_PIN_GROUP(scif0_data_b),
4176 SH_PFC_PIN_GROUP(scif1_data),
4177 SH_PFC_PIN_GROUP(scif1_clk),
4178 SH_PFC_PIN_GROUP(scif1_ctrl),
4179 SH_PFC_PIN_GROUP(scif1_data_b),
4180 SH_PFC_PIN_GROUP(scif1_data_c),
4181 SH_PFC_PIN_GROUP(scif1_data_d),
4182 SH_PFC_PIN_GROUP(scif1_clk_d),
4183 SH_PFC_PIN_GROUP(scif1_data_e),
4184 SH_PFC_PIN_GROUP(scif1_clk_e),
4185 SH_PFC_PIN_GROUP(scif2_data),
4186 SH_PFC_PIN_GROUP(scif2_clk),
4187 SH_PFC_PIN_GROUP(scif2_data_b),
4188 SH_PFC_PIN_GROUP(scifa0_data),
4189 SH_PFC_PIN_GROUP(scifa0_clk),
4190 SH_PFC_PIN_GROUP(scifa0_ctrl),
4191 SH_PFC_PIN_GROUP(scifa0_data_b),
4192 SH_PFC_PIN_GROUP(scifa0_clk_b),
4193 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4194 SH_PFC_PIN_GROUP(scifa1_data),
4195 SH_PFC_PIN_GROUP(scifa1_clk),
4196 SH_PFC_PIN_GROUP(scifa1_ctrl),
4197 SH_PFC_PIN_GROUP(scifa1_data_b),
4198 SH_PFC_PIN_GROUP(scifa1_clk_b),
4199 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4200 SH_PFC_PIN_GROUP(scifa1_data_c),
4201 SH_PFC_PIN_GROUP(scifa1_clk_c),
4202 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4203 SH_PFC_PIN_GROUP(scifa1_data_d),
4204 SH_PFC_PIN_GROUP(scifa1_clk_d),
4205 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4206 SH_PFC_PIN_GROUP(scifa2_data),
4207 SH_PFC_PIN_GROUP(scifa2_clk),
4208 SH_PFC_PIN_GROUP(scifa2_ctrl),
4209 SH_PFC_PIN_GROUP(scifa2_data_b),
4210 SH_PFC_PIN_GROUP(scifa2_data_c),
4211 SH_PFC_PIN_GROUP(scifa2_clk_c),
4212 SH_PFC_PIN_GROUP(scifb0_data),
4213 SH_PFC_PIN_GROUP(scifb0_clk),
4214 SH_PFC_PIN_GROUP(scifb0_ctrl),
4215 SH_PFC_PIN_GROUP(scifb0_data_b),
4216 SH_PFC_PIN_GROUP(scifb0_clk_b),
4217 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4218 SH_PFC_PIN_GROUP(scifb0_data_c),
4219 SH_PFC_PIN_GROUP(scifb1_data),
4220 SH_PFC_PIN_GROUP(scifb1_clk),
4221 SH_PFC_PIN_GROUP(scifb1_ctrl),
4222 SH_PFC_PIN_GROUP(scifb1_data_b),
4223 SH_PFC_PIN_GROUP(scifb1_clk_b),
4224 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4225 SH_PFC_PIN_GROUP(scifb1_data_c),
4226 SH_PFC_PIN_GROUP(scifb1_data_d),
4227 SH_PFC_PIN_GROUP(scifb1_data_e),
4228 SH_PFC_PIN_GROUP(scifb1_clk_e),
4229 SH_PFC_PIN_GROUP(scifb1_data_f),
4230 SH_PFC_PIN_GROUP(scifb1_data_g),
4231 SH_PFC_PIN_GROUP(scifb1_clk_g),
4232 SH_PFC_PIN_GROUP(scifb2_data),
4233 SH_PFC_PIN_GROUP(scifb2_clk),
4234 SH_PFC_PIN_GROUP(scifb2_ctrl),
4235 SH_PFC_PIN_GROUP(scifb2_data_b),
4236 SH_PFC_PIN_GROUP(scifb2_clk_b),
4237 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4238 SH_PFC_PIN_GROUP(scifb2_data_c),
4239 SH_PFC_PIN_GROUP(scif_clk),
4240 SH_PFC_PIN_GROUP(scif_clk_b),
4241 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4242 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4243 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4244 SH_PFC_PIN_GROUP(sdhi0_cd),
4245 SH_PFC_PIN_GROUP(sdhi0_wp),
4246 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4247 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4248 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4249 SH_PFC_PIN_GROUP(sdhi1_cd),
4250 SH_PFC_PIN_GROUP(sdhi1_wp),
4251 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4252 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4253 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4254 SH_PFC_PIN_GROUP(sdhi2_cd),
4255 SH_PFC_PIN_GROUP(sdhi2_wp),
4256 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4257 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4258 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4259 SH_PFC_PIN_GROUP(sdhi3_cd),
4260 SH_PFC_PIN_GROUP(sdhi3_wp),
4261 SH_PFC_PIN_GROUP(ssi0_data),
4262 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4263 SH_PFC_PIN_GROUP(ssi1_data),
4264 SH_PFC_PIN_GROUP(ssi1_ctrl),
4265 SH_PFC_PIN_GROUP(ssi2_data),
4266 SH_PFC_PIN_GROUP(ssi2_ctrl),
4267 SH_PFC_PIN_GROUP(ssi3_data),
4268 SH_PFC_PIN_GROUP(ssi34_ctrl),
4269 SH_PFC_PIN_GROUP(ssi4_data),
4270 SH_PFC_PIN_GROUP(ssi4_ctrl),
4271 SH_PFC_PIN_GROUP(ssi5),
4272 SH_PFC_PIN_GROUP(ssi5_b),
4273 SH_PFC_PIN_GROUP(ssi5_c),
4274 SH_PFC_PIN_GROUP(ssi6),
4275 SH_PFC_PIN_GROUP(ssi6_b),
4276 SH_PFC_PIN_GROUP(ssi7_data),
4277 SH_PFC_PIN_GROUP(ssi7_b_data),
4278 SH_PFC_PIN_GROUP(ssi7_c_data),
4279 SH_PFC_PIN_GROUP(ssi78_ctrl),
4280 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4281 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4282 SH_PFC_PIN_GROUP(ssi8_data),
4283 SH_PFC_PIN_GROUP(ssi8_b_data),
4284 SH_PFC_PIN_GROUP(ssi8_c_data),
4285 SH_PFC_PIN_GROUP(ssi9_data),
4286 SH_PFC_PIN_GROUP(ssi9_ctrl),
4287 SH_PFC_PIN_GROUP(tpu0_to0),
4288 SH_PFC_PIN_GROUP(tpu0_to1),
4289 SH_PFC_PIN_GROUP(tpu0_to2),
4290 SH_PFC_PIN_GROUP(tpu0_to3),
4291 SH_PFC_PIN_GROUP(usb0),
4292 SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1),
4293 SH_PFC_PIN_GROUP(usb1),
4294 SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1),
4295 SH_PFC_PIN_GROUP(usb2),
4296 BUS_DATA_PIN_GROUP(vin0_data, 24),
4297 BUS_DATA_PIN_GROUP(vin0_data, 20),
4298 SH_PFC_PIN_GROUP(vin0_data18),
4299 BUS_DATA_PIN_GROUP(vin0_data, 16),
4300 BUS_DATA_PIN_GROUP(vin0_data, 12),
4301 BUS_DATA_PIN_GROUP(vin0_data, 10),
4302 BUS_DATA_PIN_GROUP(vin0_data, 8),
4303 BUS_DATA_PIN_GROUP(vin0_data, 4),
4304 SH_PFC_PIN_GROUP(vin0_sync),
4305 SH_PFC_PIN_GROUP(vin0_field),
4306 SH_PFC_PIN_GROUP(vin0_clkenb),
4307 SH_PFC_PIN_GROUP(vin0_clk),
4308 BUS_DATA_PIN_GROUP(vin1_data, 24),
4309 BUS_DATA_PIN_GROUP(vin1_data, 20),
4310 SH_PFC_PIN_GROUP(vin1_data18),
4311 BUS_DATA_PIN_GROUP(vin1_data, 16),
4312 BUS_DATA_PIN_GROUP(vin1_data, 12),
4313 BUS_DATA_PIN_GROUP(vin1_data, 10),
4314 BUS_DATA_PIN_GROUP(vin1_data, 8),
4315 BUS_DATA_PIN_GROUP(vin1_data, 4),
4316 BUS_DATA_PIN_GROUP(vin1_data, 24, _b),
4317 BUS_DATA_PIN_GROUP(vin1_data, 20, _b),
4318 SH_PFC_PIN_GROUP(vin1_data18_b),
4319 BUS_DATA_PIN_GROUP(vin1_data, 16, _b),
4320 BUS_DATA_PIN_GROUP(vin1_data, 12, _b),
4321 BUS_DATA_PIN_GROUP(vin1_data, 10, _b),
4322 BUS_DATA_PIN_GROUP(vin1_data, 8, _b),
4323 BUS_DATA_PIN_GROUP(vin1_data, 4, _b),
4324 SH_PFC_PIN_GROUP(vin1_sync),
4325 SH_PFC_PIN_GROUP(vin1_sync_b),
4326 SH_PFC_PIN_GROUP(vin1_field),
4327 SH_PFC_PIN_GROUP(vin1_field_b),
4328 SH_PFC_PIN_GROUP(vin1_clkenb),
4329 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4330 SH_PFC_PIN_GROUP(vin1_clk),
4331 SH_PFC_PIN_GROUP(vin1_clk_b),
4332 BUS_DATA_PIN_GROUP(vin2_data, 24),
4333 SH_PFC_PIN_GROUP(vin2_data18),
4334 BUS_DATA_PIN_GROUP(vin2_data, 16),
4335 BUS_DATA_PIN_GROUP(vin2_data, 8),
4336 BUS_DATA_PIN_GROUP(vin2_data, 4),
4337 SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8),
4338 SH_PFC_PIN_GROUP(vin2_sync),
4339 SH_PFC_PIN_GROUP(vin2_field),
4340 SH_PFC_PIN_GROUP(vin2_clkenb),
4341 SH_PFC_PIN_GROUP(vin2_clk),
4342 SH_PFC_PIN_GROUP(vin3_data8),
4343 SH_PFC_PIN_GROUP(vin3_sync),
4344 SH_PFC_PIN_GROUP(vin3_field),
4345 SH_PFC_PIN_GROUP(vin3_clkenb),
4346 SH_PFC_PIN_GROUP(vin3_clk),
4347 },
4348 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4349 .automotive = {
4350 SH_PFC_PIN_GROUP(mlb_3pin),
4351 }
4352 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4353 };
4354
4355 static const char * const audio_clk_groups[] = {
4356 "audio_clk_a",
4357 "audio_clk_b",
4358 "audio_clk_c",
4359 "audio_clkout",
4360 "audio_clkout_b",
4361 "audio_clkout_c",
4362 "audio_clkout_d",
4363 };
4364
4365 static const char * const avb_groups[] = {
4366 "avb_link",
4367 "avb_magic",
4368 "avb_phy_int",
4369 "avb_mdio",
4370 "avb_mii",
4371 "avb_gmii",
4372 };
4373
4374 static const char * const can0_groups[] = {
4375 "can0_data",
4376 "can0_data_b",
4377 "can0_data_c",
4378 "can0_data_d",
4379 };
4380
4381 static const char * const can1_groups[] = {
4382 "can1_data",
4383 "can1_data_b",
4384 };
4385
4386 static const char * const can_clk_groups[] = {
4387 "can_clk",
4388 "can_clk_b",
4389 };
4390
4391 static const char * const du_groups[] = {
4392 "du_rgb666",
4393 "du_rgb888",
4394 "du_clk_out_0",
4395 "du_clk_out_1",
4396 "du_sync_0",
4397 "du_sync_1",
4398 "du_cde",
4399 };
4400
4401 static const char * const du0_groups[] = {
4402 "du0_clk_in",
4403 };
4404
4405 static const char * const du1_groups[] = {
4406 "du1_clk_in",
4407 };
4408
4409 static const char * const du2_groups[] = {
4410 "du2_clk_in",
4411 };
4412
4413 static const char * const eth_groups[] = {
4414 "eth_link",
4415 "eth_magic",
4416 "eth_mdio",
4417 "eth_rmii",
4418 };
4419
4420 static const char * const hscif0_groups[] = {
4421 "hscif0_data",
4422 "hscif0_clk",
4423 "hscif0_ctrl",
4424 "hscif0_data_b",
4425 "hscif0_ctrl_b",
4426 "hscif0_data_c",
4427 "hscif0_ctrl_c",
4428 "hscif0_data_d",
4429 "hscif0_ctrl_d",
4430 "hscif0_data_e",
4431 "hscif0_ctrl_e",
4432 "hscif0_data_f",
4433 "hscif0_ctrl_f",
4434 };
4435
4436 static const char * const hscif1_groups[] = {
4437 "hscif1_data",
4438 "hscif1_clk",
4439 "hscif1_ctrl",
4440 "hscif1_data_b",
4441 "hscif1_clk_b",
4442 "hscif1_ctrl_b",
4443 };
4444
4445 static const char * const i2c0_groups[] = {
4446 "i2c0",
4447 };
4448
4449 static const char * const i2c1_groups[] = {
4450 "i2c1",
4451 "i2c1_b",
4452 "i2c1_c",
4453 };
4454
4455 static const char * const i2c2_groups[] = {
4456 "i2c2",
4457 "i2c2_b",
4458 "i2c2_c",
4459 "i2c2_d",
4460 "i2c2_e",
4461 };
4462
4463 static const char * const i2c3_groups[] = {
4464 "i2c3",
4465 };
4466
4467 static const char * const iic0_groups[] = {
4468 "iic0",
4469 };
4470
4471 static const char * const iic1_groups[] = {
4472 "iic1",
4473 "iic1_b",
4474 "iic1_c",
4475 };
4476
4477 static const char * const iic2_groups[] = {
4478 "iic2",
4479 "iic2_b",
4480 "iic2_c",
4481 "iic2_d",
4482 "iic2_e",
4483 };
4484
4485 static const char * const iic3_groups[] = {
4486 "iic3",
4487 };
4488
4489 static const char * const intc_groups[] = {
4490 "intc_irq0",
4491 "intc_irq1",
4492 "intc_irq2",
4493 "intc_irq3",
4494 };
4495
4496 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4497 static const char * const mlb_groups[] = {
4498 "mlb_3pin",
4499 };
4500 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4501
4502 static const char * const mmc0_groups[] = {
4503 "mmc0_data1",
4504 "mmc0_data4",
4505 "mmc0_data8",
4506 "mmc0_ctrl",
4507 };
4508
4509 static const char * const mmc1_groups[] = {
4510 "mmc1_data1",
4511 "mmc1_data4",
4512 "mmc1_data8",
4513 "mmc1_ctrl",
4514 };
4515
4516 static const char * const msiof0_groups[] = {
4517 "msiof0_clk",
4518 "msiof0_sync",
4519 "msiof0_ss1",
4520 "msiof0_ss2",
4521 "msiof0_rx",
4522 "msiof0_tx",
4523 "msiof0_clk_b",
4524 "msiof0_ss1_b",
4525 "msiof0_ss2_b",
4526 "msiof0_rx_b",
4527 "msiof0_tx_b",
4528 };
4529
4530 static const char * const msiof1_groups[] = {
4531 "msiof1_clk",
4532 "msiof1_sync",
4533 "msiof1_ss1",
4534 "msiof1_ss2",
4535 "msiof1_rx",
4536 "msiof1_tx",
4537 "msiof1_clk_b",
4538 "msiof1_ss1_b",
4539 "msiof1_ss2_b",
4540 "msiof1_rx_b",
4541 "msiof1_tx_b",
4542 };
4543
4544 static const char * const msiof2_groups[] = {
4545 "msiof2_clk",
4546 "msiof2_sync",
4547 "msiof2_ss1",
4548 "msiof2_ss2",
4549 "msiof2_rx",
4550 "msiof2_tx",
4551 };
4552
4553 static const char * const msiof3_groups[] = {
4554 "msiof3_clk",
4555 "msiof3_sync",
4556 "msiof3_ss1",
4557 "msiof3_ss2",
4558 "msiof3_rx",
4559 "msiof3_tx",
4560 "msiof3_clk_b",
4561 "msiof3_sync_b",
4562 "msiof3_rx_b",
4563 "msiof3_tx_b",
4564 };
4565
4566 static const char * const pwm0_groups[] = {
4567 "pwm0",
4568 "pwm0_b",
4569 };
4570
4571 static const char * const pwm1_groups[] = {
4572 "pwm1",
4573 "pwm1_b",
4574 };
4575
4576 static const char * const pwm2_groups[] = {
4577 "pwm2",
4578 };
4579
4580 static const char * const pwm3_groups[] = {
4581 "pwm3",
4582 };
4583
4584 static const char * const pwm4_groups[] = {
4585 "pwm4",
4586 };
4587
4588 static const char * const pwm5_groups[] = {
4589 "pwm5",
4590 };
4591
4592 static const char * const pwm6_groups[] = {
4593 "pwm6",
4594 };
4595
4596 static const char * const qspi_groups[] = {
4597 "qspi_ctrl",
4598 "qspi_data2",
4599 "qspi_data4",
4600 };
4601
4602 static const char * const scif0_groups[] = {
4603 "scif0_data",
4604 "scif0_clk",
4605 "scif0_ctrl",
4606 "scif0_data_b",
4607 };
4608
4609 static const char * const scif1_groups[] = {
4610 "scif1_data",
4611 "scif1_clk",
4612 "scif1_ctrl",
4613 "scif1_data_b",
4614 "scif1_data_c",
4615 "scif1_data_d",
4616 "scif1_clk_d",
4617 "scif1_data_e",
4618 "scif1_clk_e",
4619 };
4620
4621 static const char * const scif2_groups[] = {
4622 "scif2_data",
4623 "scif2_clk",
4624 "scif2_data_b",
4625 };
4626
4627 static const char * const scifa0_groups[] = {
4628 "scifa0_data",
4629 "scifa0_clk",
4630 "scifa0_ctrl",
4631 "scifa0_data_b",
4632 "scifa0_clk_b",
4633 "scifa0_ctrl_b",
4634 };
4635
4636 static const char * const scifa1_groups[] = {
4637 "scifa1_data",
4638 "scifa1_clk",
4639 "scifa1_ctrl",
4640 "scifa1_data_b",
4641 "scifa1_clk_b",
4642 "scifa1_ctrl_b",
4643 "scifa1_data_c",
4644 "scifa1_clk_c",
4645 "scifa1_ctrl_c",
4646 "scifa1_data_d",
4647 "scifa1_clk_d",
4648 "scifa1_ctrl_d",
4649 };
4650
4651 static const char * const scifa2_groups[] = {
4652 "scifa2_data",
4653 "scifa2_clk",
4654 "scifa2_ctrl",
4655 "scifa2_data_b",
4656 "scifa2_data_c",
4657 "scifa2_clk_c",
4658 };
4659
4660 static const char * const scifb0_groups[] = {
4661 "scifb0_data",
4662 "scifb0_clk",
4663 "scifb0_ctrl",
4664 "scifb0_data_b",
4665 "scifb0_clk_b",
4666 "scifb0_ctrl_b",
4667 "scifb0_data_c",
4668 };
4669
4670 static const char * const scifb1_groups[] = {
4671 "scifb1_data",
4672 "scifb1_clk",
4673 "scifb1_ctrl",
4674 "scifb1_data_b",
4675 "scifb1_clk_b",
4676 "scifb1_ctrl_b",
4677 "scifb1_data_c",
4678 "scifb1_data_d",
4679 "scifb1_data_e",
4680 "scifb1_clk_e",
4681 "scifb1_data_f",
4682 "scifb1_data_g",
4683 "scifb1_clk_g",
4684 };
4685
4686 static const char * const scifb2_groups[] = {
4687 "scifb2_data",
4688 "scifb2_clk",
4689 "scifb2_ctrl",
4690 "scifb2_data_b",
4691 "scifb2_clk_b",
4692 "scifb2_ctrl_b",
4693 "scifb2_data_c",
4694 };
4695
4696 static const char * const scif_clk_groups[] = {
4697 "scif_clk",
4698 "scif_clk_b",
4699 };
4700
4701 static const char * const sdhi0_groups[] = {
4702 "sdhi0_data1",
4703 "sdhi0_data4",
4704 "sdhi0_ctrl",
4705 "sdhi0_cd",
4706 "sdhi0_wp",
4707 };
4708
4709 static const char * const sdhi1_groups[] = {
4710 "sdhi1_data1",
4711 "sdhi1_data4",
4712 "sdhi1_ctrl",
4713 "sdhi1_cd",
4714 "sdhi1_wp",
4715 };
4716
4717 static const char * const sdhi2_groups[] = {
4718 "sdhi2_data1",
4719 "sdhi2_data4",
4720 "sdhi2_ctrl",
4721 "sdhi2_cd",
4722 "sdhi2_wp",
4723 };
4724
4725 static const char * const sdhi3_groups[] = {
4726 "sdhi3_data1",
4727 "sdhi3_data4",
4728 "sdhi3_ctrl",
4729 "sdhi3_cd",
4730 "sdhi3_wp",
4731 };
4732
4733 static const char * const ssi_groups[] = {
4734 "ssi0_data",
4735 "ssi0129_ctrl",
4736 "ssi1_data",
4737 "ssi1_ctrl",
4738 "ssi2_data",
4739 "ssi2_ctrl",
4740 "ssi3_data",
4741 "ssi34_ctrl",
4742 "ssi4_data",
4743 "ssi4_ctrl",
4744 "ssi5",
4745 "ssi5_b",
4746 "ssi5_c",
4747 "ssi6",
4748 "ssi6_b",
4749 "ssi7_data",
4750 "ssi7_b_data",
4751 "ssi7_c_data",
4752 "ssi78_ctrl",
4753 "ssi78_b_ctrl",
4754 "ssi78_c_ctrl",
4755 "ssi8_data",
4756 "ssi8_b_data",
4757 "ssi8_c_data",
4758 "ssi9_data",
4759 "ssi9_ctrl",
4760 };
4761
4762 static const char * const tpu0_groups[] = {
4763 "tpu0_to0",
4764 "tpu0_to1",
4765 "tpu0_to2",
4766 "tpu0_to3",
4767 };
4768
4769 static const char * const usb0_groups[] = {
4770 "usb0",
4771 "usb0_ovc_vbus",
4772 };
4773
4774 static const char * const usb1_groups[] = {
4775 "usb1",
4776 "usb1_pwen",
4777 };
4778
4779 static const char * const usb2_groups[] = {
4780 "usb2",
4781 };
4782
4783 static const char * const vin0_groups[] = {
4784 "vin0_data24",
4785 "vin0_data20",
4786 "vin0_data18",
4787 "vin0_data16",
4788 "vin0_data12",
4789 "vin0_data10",
4790 "vin0_data8",
4791 "vin0_data4",
4792 "vin0_sync",
4793 "vin0_field",
4794 "vin0_clkenb",
4795 "vin0_clk",
4796 };
4797
4798 static const char * const vin1_groups[] = {
4799 "vin1_data24",
4800 "vin1_data20",
4801 "vin1_data18",
4802 "vin1_data16",
4803 "vin1_data12",
4804 "vin1_data10",
4805 "vin1_data8",
4806 "vin1_data4",
4807 "vin1_data24_b",
4808 "vin1_data20_b",
4809 "vin1_data18_b",
4810 "vin1_data16_b",
4811 "vin1_data12_b",
4812 "vin1_data10_b",
4813 "vin1_data8_b",
4814 "vin1_data4_b",
4815 "vin1_sync",
4816 "vin1_sync_b",
4817 "vin1_field",
4818 "vin1_field_b",
4819 "vin1_clkenb",
4820 "vin1_clkenb_b",
4821 "vin1_clk",
4822 "vin1_clk_b",
4823 };
4824
4825 static const char * const vin2_groups[] = {
4826 "vin2_data24",
4827 "vin2_data18",
4828 "vin2_data16",
4829 "vin2_data8",
4830 "vin2_data4",
4831 "vin2_g8",
4832 "vin2_sync",
4833 "vin2_field",
4834 "vin2_clkenb",
4835 "vin2_clk",
4836 };
4837
4838 static const char * const vin3_groups[] = {
4839 "vin3_data8",
4840 "vin3_sync",
4841 "vin3_field",
4842 "vin3_clkenb",
4843 "vin3_clk",
4844 };
4845
4846 static const struct {
4847 struct sh_pfc_function common[58];
4848 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4849 struct sh_pfc_function automotive[1];
4850 #endif
4851 } pinmux_functions = {
4852 .common = {
4853 SH_PFC_FUNCTION(audio_clk),
4854 SH_PFC_FUNCTION(avb),
4855 SH_PFC_FUNCTION(can0),
4856 SH_PFC_FUNCTION(can1),
4857 SH_PFC_FUNCTION(can_clk),
4858 SH_PFC_FUNCTION(du),
4859 SH_PFC_FUNCTION(du0),
4860 SH_PFC_FUNCTION(du1),
4861 SH_PFC_FUNCTION(du2),
4862 SH_PFC_FUNCTION(eth),
4863 SH_PFC_FUNCTION(hscif0),
4864 SH_PFC_FUNCTION(hscif1),
4865 SH_PFC_FUNCTION(i2c0),
4866 SH_PFC_FUNCTION(i2c1),
4867 SH_PFC_FUNCTION(i2c2),
4868 SH_PFC_FUNCTION(i2c3),
4869 SH_PFC_FUNCTION(iic0),
4870 SH_PFC_FUNCTION(iic1),
4871 SH_PFC_FUNCTION(iic2),
4872 SH_PFC_FUNCTION(iic3),
4873 SH_PFC_FUNCTION(intc),
4874 SH_PFC_FUNCTION(mmc0),
4875 SH_PFC_FUNCTION(mmc1),
4876 SH_PFC_FUNCTION(msiof0),
4877 SH_PFC_FUNCTION(msiof1),
4878 SH_PFC_FUNCTION(msiof2),
4879 SH_PFC_FUNCTION(msiof3),
4880 SH_PFC_FUNCTION(pwm0),
4881 SH_PFC_FUNCTION(pwm1),
4882 SH_PFC_FUNCTION(pwm2),
4883 SH_PFC_FUNCTION(pwm3),
4884 SH_PFC_FUNCTION(pwm4),
4885 SH_PFC_FUNCTION(pwm5),
4886 SH_PFC_FUNCTION(pwm6),
4887 SH_PFC_FUNCTION(qspi),
4888 SH_PFC_FUNCTION(scif0),
4889 SH_PFC_FUNCTION(scif1),
4890 SH_PFC_FUNCTION(scif2),
4891 SH_PFC_FUNCTION(scifa0),
4892 SH_PFC_FUNCTION(scifa1),
4893 SH_PFC_FUNCTION(scifa2),
4894 SH_PFC_FUNCTION(scifb0),
4895 SH_PFC_FUNCTION(scifb1),
4896 SH_PFC_FUNCTION(scifb2),
4897 SH_PFC_FUNCTION(scif_clk),
4898 SH_PFC_FUNCTION(sdhi0),
4899 SH_PFC_FUNCTION(sdhi1),
4900 SH_PFC_FUNCTION(sdhi2),
4901 SH_PFC_FUNCTION(sdhi3),
4902 SH_PFC_FUNCTION(ssi),
4903 SH_PFC_FUNCTION(tpu0),
4904 SH_PFC_FUNCTION(usb0),
4905 SH_PFC_FUNCTION(usb1),
4906 SH_PFC_FUNCTION(usb2),
4907 SH_PFC_FUNCTION(vin0),
4908 SH_PFC_FUNCTION(vin1),
4909 SH_PFC_FUNCTION(vin2),
4910 SH_PFC_FUNCTION(vin3),
4911 },
4912 #ifdef CONFIG_PINCTRL_PFC_R8A7790
4913 .automotive = {
4914 SH_PFC_FUNCTION(mlb),
4915 }
4916 #endif /* CONFIG_PINCTRL_PFC_R8A7790 */
4917 };
4918
4919 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4920 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
4921 GP_0_31_FN, FN_IP3_17_15,
4922 GP_0_30_FN, FN_IP3_14_12,
4923 GP_0_29_FN, FN_IP3_11_8,
4924 GP_0_28_FN, FN_IP3_7_4,
4925 GP_0_27_FN, FN_IP3_3_0,
4926 GP_0_26_FN, FN_IP2_28_26,
4927 GP_0_25_FN, FN_IP2_25_22,
4928 GP_0_24_FN, FN_IP2_21_18,
4929 GP_0_23_FN, FN_IP2_17_15,
4930 GP_0_22_FN, FN_IP2_14_12,
4931 GP_0_21_FN, FN_IP2_11_9,
4932 GP_0_20_FN, FN_IP2_8_6,
4933 GP_0_19_FN, FN_IP2_5_3,
4934 GP_0_18_FN, FN_IP2_2_0,
4935 GP_0_17_FN, FN_IP1_29_28,
4936 GP_0_16_FN, FN_IP1_27_26,
4937 GP_0_15_FN, FN_IP1_25_22,
4938 GP_0_14_FN, FN_IP1_21_18,
4939 GP_0_13_FN, FN_IP1_17_15,
4940 GP_0_12_FN, FN_IP1_14_12,
4941 GP_0_11_FN, FN_IP1_11_8,
4942 GP_0_10_FN, FN_IP1_7_4,
4943 GP_0_9_FN, FN_IP1_3_0,
4944 GP_0_8_FN, FN_IP0_30_27,
4945 GP_0_7_FN, FN_IP0_26_23,
4946 GP_0_6_FN, FN_IP0_22_20,
4947 GP_0_5_FN, FN_IP0_19_16,
4948 GP_0_4_FN, FN_IP0_15_12,
4949 GP_0_3_FN, FN_IP0_11_9,
4950 GP_0_2_FN, FN_IP0_8_6,
4951 GP_0_1_FN, FN_IP0_5_3,
4952 GP_0_0_FN, FN_IP0_2_0 ))
4953 },
4954 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
4955 0, 0,
4956 0, 0,
4957 GP_1_29_FN, FN_IP6_13_11,
4958 GP_1_28_FN, FN_IP6_10_9,
4959 GP_1_27_FN, FN_IP6_8_6,
4960 GP_1_26_FN, FN_IP6_5_3,
4961 GP_1_25_FN, FN_IP6_2_0,
4962 GP_1_24_FN, FN_IP5_29_27,
4963 GP_1_23_FN, FN_IP5_26_24,
4964 GP_1_22_FN, FN_IP5_23_21,
4965 GP_1_21_FN, FN_IP5_20_18,
4966 GP_1_20_FN, FN_IP5_17_15,
4967 GP_1_19_FN, FN_IP5_14_13,
4968 GP_1_18_FN, FN_IP5_12_10,
4969 GP_1_17_FN, FN_IP5_9_6,
4970 GP_1_16_FN, FN_IP5_5_3,
4971 GP_1_15_FN, FN_IP5_2_0,
4972 GP_1_14_FN, FN_IP4_29_27,
4973 GP_1_13_FN, FN_IP4_26_24,
4974 GP_1_12_FN, FN_IP4_23_21,
4975 GP_1_11_FN, FN_IP4_20_18,
4976 GP_1_10_FN, FN_IP4_17_15,
4977 GP_1_9_FN, FN_IP4_14_12,
4978 GP_1_8_FN, FN_IP4_11_9,
4979 GP_1_7_FN, FN_IP4_8_6,
4980 GP_1_6_FN, FN_IP4_5_3,
4981 GP_1_5_FN, FN_IP4_2_0,
4982 GP_1_4_FN, FN_IP3_31_29,
4983 GP_1_3_FN, FN_IP3_28_26,
4984 GP_1_2_FN, FN_IP3_25_23,
4985 GP_1_1_FN, FN_IP3_22_20,
4986 GP_1_0_FN, FN_IP3_19_18, ))
4987 },
4988 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
4989 0, 0,
4990 0, 0,
4991 GP_2_29_FN, FN_IP7_15_13,
4992 GP_2_28_FN, FN_IP7_12_10,
4993 GP_2_27_FN, FN_IP7_9_8,
4994 GP_2_26_FN, FN_IP7_7_6,
4995 GP_2_25_FN, FN_IP7_5_3,
4996 GP_2_24_FN, FN_IP7_2_0,
4997 GP_2_23_FN, FN_IP6_31_29,
4998 GP_2_22_FN, FN_IP6_28_26,
4999 GP_2_21_FN, FN_IP6_25_23,
5000 GP_2_20_FN, FN_IP6_22_20,
5001 GP_2_19_FN, FN_IP6_19_17,
5002 GP_2_18_FN, FN_IP6_16_14,
5003 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
5004 GP_2_16_FN, FN_IP8_27,
5005 GP_2_15_FN, FN_IP8_26,
5006 GP_2_14_FN, FN_IP8_25_24,
5007 GP_2_13_FN, FN_IP8_23_22,
5008 GP_2_12_FN, FN_IP8_21_20,
5009 GP_2_11_FN, FN_IP8_19_18,
5010 GP_2_10_FN, FN_IP8_17_16,
5011 GP_2_9_FN, FN_IP8_15_14,
5012 GP_2_8_FN, FN_IP8_13_12,
5013 GP_2_7_FN, FN_IP8_11_10,
5014 GP_2_6_FN, FN_IP8_9_8,
5015 GP_2_5_FN, FN_IP8_7_6,
5016 GP_2_4_FN, FN_IP8_5_4,
5017 GP_2_3_FN, FN_IP8_3_2,
5018 GP_2_2_FN, FN_IP8_1_0,
5019 GP_2_1_FN, FN_IP7_30_29,
5020 GP_2_0_FN, FN_IP7_28_27 ))
5021 },
5022 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5023 GP_3_31_FN, FN_IP11_21_18,
5024 GP_3_30_FN, FN_IP11_17_15,
5025 GP_3_29_FN, FN_IP11_14_13,
5026 GP_3_28_FN, FN_IP11_12_11,
5027 GP_3_27_FN, FN_IP11_10_9,
5028 GP_3_26_FN, FN_IP11_8_7,
5029 GP_3_25_FN, FN_IP11_6_5,
5030 GP_3_24_FN, FN_IP11_4,
5031 GP_3_23_FN, FN_IP11_3_0,
5032 GP_3_22_FN, FN_IP10_29_26,
5033 GP_3_21_FN, FN_IP10_25_23,
5034 GP_3_20_FN, FN_IP10_22_19,
5035 GP_3_19_FN, FN_IP10_18_15,
5036 GP_3_18_FN, FN_IP10_14_11,
5037 GP_3_17_FN, FN_IP10_10_7,
5038 GP_3_16_FN, FN_IP10_6_4,
5039 GP_3_15_FN, FN_IP10_3_0,
5040 GP_3_14_FN, FN_IP9_31_28,
5041 GP_3_13_FN, FN_IP9_27_26,
5042 GP_3_12_FN, FN_IP9_25_24,
5043 GP_3_11_FN, FN_IP9_23_22,
5044 GP_3_10_FN, FN_IP9_21_20,
5045 GP_3_9_FN, FN_IP9_19_18,
5046 GP_3_8_FN, FN_IP9_17_16,
5047 GP_3_7_FN, FN_IP9_15_12,
5048 GP_3_6_FN, FN_IP9_11_8,
5049 GP_3_5_FN, FN_IP9_7_6,
5050 GP_3_4_FN, FN_IP9_5_4,
5051 GP_3_3_FN, FN_IP9_3_2,
5052 GP_3_2_FN, FN_IP9_1_0,
5053 GP_3_1_FN, FN_IP8_30_29,
5054 GP_3_0_FN, FN_IP8_28 ))
5055 },
5056 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5057 GP_4_31_FN, FN_IP14_18_16,
5058 GP_4_30_FN, FN_IP14_15_12,
5059 GP_4_29_FN, FN_IP14_11_9,
5060 GP_4_28_FN, FN_IP14_8_6,
5061 GP_4_27_FN, FN_IP14_5_3,
5062 GP_4_26_FN, FN_IP14_2_0,
5063 GP_4_25_FN, FN_IP13_30_29,
5064 GP_4_24_FN, FN_IP13_28_26,
5065 GP_4_23_FN, FN_IP13_25_23,
5066 GP_4_22_FN, FN_IP13_22_19,
5067 GP_4_21_FN, FN_IP13_18_16,
5068 GP_4_20_FN, FN_IP13_15_13,
5069 GP_4_19_FN, FN_IP13_12_10,
5070 GP_4_18_FN, FN_IP13_9_7,
5071 GP_4_17_FN, FN_IP13_6_3,
5072 GP_4_16_FN, FN_IP13_2_0,
5073 GP_4_15_FN, FN_IP12_30_28,
5074 GP_4_14_FN, FN_IP12_27_25,
5075 GP_4_13_FN, FN_IP12_24_23,
5076 GP_4_12_FN, FN_IP12_22_20,
5077 GP_4_11_FN, FN_IP12_19_17,
5078 GP_4_10_FN, FN_IP12_16_14,
5079 GP_4_9_FN, FN_IP12_13_11,
5080 GP_4_8_FN, FN_IP12_10_8,
5081 GP_4_7_FN, FN_IP12_7_6,
5082 GP_4_6_FN, FN_IP12_5_4,
5083 GP_4_5_FN, FN_IP12_3_2,
5084 GP_4_4_FN, FN_IP12_1_0,
5085 GP_4_3_FN, FN_IP11_31_30,
5086 GP_4_2_FN, FN_IP11_29_27,
5087 GP_4_1_FN, FN_IP11_26_24,
5088 GP_4_0_FN, FN_IP11_23_22 ))
5089 },
5090 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5091 GP_5_31_FN, FN_IP7_24_22,
5092 GP_5_30_FN, FN_IP7_21_19,
5093 GP_5_29_FN, FN_IP7_18_16,
5094 GP_5_28_FN, FN_DU_DOTCLKIN2,
5095 GP_5_27_FN, FN_IP7_26_25,
5096 GP_5_26_FN, FN_DU_DOTCLKIN0,
5097 GP_5_25_FN, FN_AVS2,
5098 GP_5_24_FN, FN_AVS1,
5099 GP_5_23_FN, FN_USB2_OVC,
5100 GP_5_22_FN, FN_USB2_PWEN,
5101 GP_5_21_FN, FN_IP16_7,
5102 GP_5_20_FN, FN_IP16_6,
5103 GP_5_19_FN, FN_USB0_OVC_VBUS,
5104 GP_5_18_FN, FN_USB0_PWEN,
5105 GP_5_17_FN, FN_IP16_5_3,
5106 GP_5_16_FN, FN_IP16_2_0,
5107 GP_5_15_FN, FN_IP15_29_28,
5108 GP_5_14_FN, FN_IP15_27_26,
5109 GP_5_13_FN, FN_IP15_25_23,
5110 GP_5_12_FN, FN_IP15_22_20,
5111 GP_5_11_FN, FN_IP15_19_18,
5112 GP_5_10_FN, FN_IP15_17_16,
5113 GP_5_9_FN, FN_IP15_15_14,
5114 GP_5_8_FN, FN_IP15_13_12,
5115 GP_5_7_FN, FN_IP15_11_9,
5116 GP_5_6_FN, FN_IP15_8_6,
5117 GP_5_5_FN, FN_IP15_5_3,
5118 GP_5_4_FN, FN_IP15_2_0,
5119 GP_5_3_FN, FN_IP14_30_28,
5120 GP_5_2_FN, FN_IP14_27_25,
5121 GP_5_1_FN, FN_IP14_24_22,
5122 GP_5_0_FN, FN_IP14_21_19 ))
5123 },
5124 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5125 GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
5126 GROUP(
5127 /* IP0_31 [1] RESERVED */
5128 /* IP0_30_27 [4] */
5129 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
5130 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
5131 0, 0, 0, 0, 0, 0, 0, 0, 0,
5132 /* IP0_26_23 [4] */
5133 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
5134 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
5135 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
5136 /* IP0_22_20 [3] */
5137 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
5138 FN_I2C2_SCL_C, 0, 0,
5139 /* IP0_19_16 [4] */
5140 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
5141 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
5142 0, 0, 0, 0, 0, 0, 0, 0, 0,
5143 /* IP0_15_12 [4] */
5144 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
5145 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
5146 0, 0, 0, 0, 0, 0, 0, 0, 0,
5147 /* IP0_11_9 [3] */
5148 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
5149 0, 0, 0,
5150 /* IP0_8_6 [3] */
5151 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
5152 0, 0, 0,
5153 /* IP0_5_3 [3] */
5154 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
5155 0, 0, 0,
5156 /* IP0_2_0 [3] */
5157 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
5158 0, 0, 0, ))
5159 },
5160 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5161 GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
5162 GROUP(
5163 /* IP1_31_30 [2] RESERVED */
5164 /* IP1_29_28 [2] */
5165 FN_A1, FN_PWM4, 0, 0,
5166 /* IP1_27_26 [2] */
5167 FN_A0, FN_PWM3, 0, 0,
5168 /* IP1_25_22 [4] */
5169 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5170 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5171 0, 0, 0, 0, 0, 0, 0, 0, 0,
5172 /* IP1_21_18 [4] */
5173 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5174 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5175 0, 0, 0, 0, 0, 0, 0, 0, 0,
5176 /* IP1_17_15 [3] */
5177 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5178 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5179 0, 0, 0,
5180 /* IP1_14_12 [3] */
5181 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5182 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5183 0, 0,
5184 /* IP1_11_8 [4] */
5185 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5186 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5187 0, 0, 0, 0, 0, 0, 0, 0, 0,
5188 /* IP1_7_4 [4] */
5189 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5190 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5191 0, 0, 0, 0, 0, 0, 0, 0, 0,
5192 /* IP1_3_0 [4] */
5193 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5194 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5195 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
5196 },
5197 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5198 GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
5199 GROUP(
5200 /* IP2_31_29 [3] RESERVED */
5201 /* IP2_28_26 [3] */
5202 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5203 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5204 /* IP2_25_22 [4] */
5205 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5206 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5207 0, 0, 0, 0, 0, 0, 0, 0,
5208 /* IP2_21_18 [4] */
5209 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5210 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5211 0, 0, 0, 0, 0, 0, 0, 0,
5212 /* IP2_17_15 [3] */
5213 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5214 0, 0, 0, 0,
5215 /* IP2_14_12 [3] */
5216 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5217 /* IP2_11_9 [3] */
5218 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5219 /* IP2_8_6 [3] */
5220 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5221 /* IP2_5_3 [3] */
5222 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5223 /* IP2_2_0 [3] */
5224 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
5225 },
5226 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5227 GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
5228 GROUP(
5229 /* IP3_31_29 [3] */
5230 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5231 0, 0, 0,
5232 /* IP3_28_26 [3] */
5233 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5234 0, 0, 0, 0,
5235 /* IP3_25_23 [3] */
5236 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5237 /* IP3_22_20 [3] */
5238 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5239 /* IP3_19_18 [2] */
5240 FN_A16, FN_ATAWR1_N, 0, 0,
5241 /* IP3_17_15 [3] */
5242 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5243 0, 0, 0, 0,
5244 /* IP3_14_12 [3] */
5245 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5246 0, 0, 0, 0,
5247 /* IP3_11_8 [4] */
5248 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5249 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5250 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5251 /* IP3_7_4 [4] */
5252 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5253 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5254 0, 0, 0, 0, 0, 0, 0, 0, 0,
5255 /* IP3_3_0 [4] */
5256 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5257 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5258 0, 0, 0, 0, 0, 0, 0, 0, ))
5259 },
5260 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5261 GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
5262 GROUP(
5263 /* IP4_31_30 [2] RESERVED */
5264 /* IP4_29_27 [3] */
5265 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5266 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5267 /* IP4_26_24 [3] */
5268 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5269 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5270 /* IP4_23_21 [3] */
5271 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5272 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5273 /* IP4_20_18 [3] */
5274 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5275 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5276 /* IP4_17_15 [3] */
5277 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5278 0, 0, 0,
5279 /* IP4_14_12 [3] */
5280 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5281 FN_VI2_FIELD_B, 0, 0,
5282 /* IP4_11_9 [3] */
5283 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5284 FN_VI2_CLKENB_B, 0, 0,
5285 /* IP4_8_6 [3] */
5286 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5287 /* IP4_5_3 [3] */
5288 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5289 /* IP4_2_0 [3] */
5290 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5291 ))
5292 },
5293 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5294 GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
5295 GROUP(
5296 /* IP5_31_30 [2] RESERVED */
5297 /* IP5_29_27 [3] */
5298 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5299 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5300 /* IP5_26_24 [3] */
5301 FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B,
5302 FN_HRX0_B, FN_MSIOF0_SCK_B, 0,
5303 /* IP5_23_21 [3] */
5304 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5305 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5306 /* IP5_20_18 [3] */
5307 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5308 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5309 /* IP5_17_15 [3] */
5310 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5311 0, 0, 0,
5312 /* IP5_14_13 [2] */
5313 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5314 /* IP5_12_10 [3] */
5315 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5316 0, 0,
5317 /* IP5_9_6 [4] */
5318 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5319 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5320 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5321 /* IP5_5_3 [3] */
5322 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5323 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5324 FN_INTC_EN0_N, FN_I2C1_SCL,
5325 /* IP5_2_0 [3] */
5326 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5327 FN_VI2_R3, 0, 0, ))
5328 },
5329 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5330 GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
5331 GROUP(
5332 /* IP6_31_29 [3] */
5333 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5334 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5335 /* IP6_28_26 [3] */
5336 FN_ETH_LINK, 0, FN_HTX0_E,
5337 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5338 /* IP6_25_23 [3] */
5339 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5340 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5341 /* IP6_22_20 [3] */
5342 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5343 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5344 /* IP6_19_17 [3] */
5345 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5346 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5347 /* IP6_16_14 [3] */
5348 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5349 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5350 FN_I2C2_SCL_E, 0,
5351 /* IP6_13_11 [3] */
5352 FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B,
5353 FN_MSIOF0_RXD_B, 0, 0,
5354 /* IP6_10_9 [2] */
5355 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5356 /* IP6_8_6 [3] */
5357 FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0,
5358 /* IP6_5_3 [3] */
5359 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5360 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5361 /* IP6_2_0 [3] */
5362 FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N,
5363 FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
5364 },
5365 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5366 GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
5367 GROUP(
5368 /* IP7_31 [1] RESERVED */
5369 /* IP7_30_29 [2] */
5370 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5371 /* IP7_28_27 [2] */
5372 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5373 /* IP7_26_25 [2] */
5374 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5375 /* IP7_24_22 [3] */
5376 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5377 0, 0, 0,
5378 /* IP7_21_19 [3] */
5379 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5380 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5381 /* IP7_18_16 [3] */
5382 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5383 FN_GLO_SS_C, 0, 0, 0,
5384 /* IP7_15_13 [3] */
5385 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5386 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5387 /* IP7_12_10 [3] */
5388 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5389 FN_GLO_SCLK_C, 0, 0, 0,
5390 /* IP7_9_8 [2] */
5391 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5392 /* IP7_7_6 [2] */
5393 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5394 /* IP7_5_3 [3] */
5395 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5396 /* IP7_2_0 [3] */
5397 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5398 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
5399 },
5400 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5401 GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
5402 2, 2, 2, 2, 2, 2),
5403 GROUP(
5404 /* IP8_31 [1] RESERVED */
5405 /* IP8_30_29 [2] */
5406 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5407 /* IP8_28 [1] */
5408 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5409 /* IP8_27 [1] */
5410 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5411 /* IP8_26 [1] */
5412 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5413 /* IP8_25_24 [2] */
5414 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5415 FN_AVB_MAGIC, 0,
5416 /* IP8_23_22 [2] */
5417 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5418 /* IP8_21_20 [2] */
5419 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5420 /* IP8_19_18 [2] */
5421 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5422 /* IP8_17_16 [2] */
5423 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5424 /* IP8_15_14 [2] */
5425 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5426 /* IP8_13_12 [2] */
5427 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5428 /* IP8_11_10 [2] */
5429 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5430 /* IP8_9_8 [2] */
5431 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5432 /* IP8_7_6 [2] */
5433 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5434 /* IP8_5_4 [2] */
5435 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5436 /* IP8_3_2 [2] */
5437 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5438 /* IP8_1_0 [2] */
5439 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
5440 },
5441 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5442 GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
5443 GROUP(
5444 /* IP9_31_28 [4] */
5445 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5446 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5447 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5448 /* IP9_27_26 [2] */
5449 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5450 /* IP9_25_24 [2] */
5451 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5452 /* IP9_23_22 [2] */
5453 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5454 /* IP9_21_20 [2] */
5455 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5456 /* IP9_19_18 [2] */
5457 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5458 /* IP9_17_16 [2] */
5459 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5460 /* IP9_15_12 [4] */
5461 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5462 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5463 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5464 /* IP9_11_8 [4] */
5465 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5466 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5467 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5468 /* IP9_7_6 [2] */
5469 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5470 /* IP9_5_4 [2] */
5471 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5472 /* IP9_3_2 [2] */
5473 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5474 /* IP9_1_0 [2] */
5475 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
5476 },
5477 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5478 GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4),
5479 GROUP(
5480 /* IP10_31_30 [2] RESERVED */
5481 /* IP10_29_26 [4] */
5482 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5483 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5484 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5485 /* IP10_25_23 [3] */
5486 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5487 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5488 /* IP10_22_19 [4] */
5489 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5490 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5491 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5492 /* IP10_18_15 [4] */
5493 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5494 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5495 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5496 0, 0, 0, 0, 0, 0,
5497 /* IP10_14_11 [4] */
5498 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5499 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5500 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5501 0, 0, 0, 0, 0, 0, 0,
5502 /* IP10_10_7 [4] */
5503 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5504 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5505 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5506 0, 0, 0, 0, 0, 0, 0,
5507 /* IP10_6_4 [3] */
5508 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5509 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5510 FN_VI3_DATA0_B, 0,
5511 /* IP10_3_0 [4] */
5512 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5513 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5514 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
5515 },
5516 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5517 GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
5518 GROUP(
5519 /* IP11_31_30 [2] */
5520 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5521 /* IP11_29_27 [3] */
5522 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5523 0, 0, 0,
5524 /* IP11_26_24 [3] */
5525 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5526 0, 0, 0,
5527 /* IP11_23_22 [2] */
5528 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5529 /* IP11_21_18 [4] */
5530 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5531 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5532 /* IP11_17_15 [3] */
5533 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5534 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5535 /* IP11_14_13 [2] */
5536 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5537 /* IP11_12_11 [2] */
5538 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5539 /* IP11_10_9 [2] */
5540 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5541 /* IP11_8_7 [2] */
5542 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5543 /* IP11_6_5 [2] */
5544 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5545 /* IP11_4 [1] */
5546 FN_SD3_CLK, FN_MMC1_CLK,
5547 /* IP11_3_0 [4] */
5548 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5549 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5550 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
5551 },
5552 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5553 GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5554 GROUP(
5555 /* IP12_31 [1] RESERVED */
5556 /* IP12_30_28 [3] */
5557 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5558 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5559 FN_CAN_DEBUGOUT4, 0, 0,
5560 /* IP12_27_25 [3] */
5561 FN_SSI_SCK5, FN_SCIFB1_SCK,
5562 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5563 FN_CAN_DEBUGOUT3, 0, 0,
5564 /* IP12_24_23 [2] */
5565 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5566 FN_CAN_DEBUGOUT2,
5567 /* IP12_22_20 [3] */
5568 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5569 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5570 /* IP12_19_17 [3] */
5571 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5572 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5573 /* IP12_16_14 [3] */
5574 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5575 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5576 /* IP12_13_11 [3] */
5577 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5578 FN_CAN_STEP0, 0, 0, 0,
5579 /* IP12_10_8 [3] */
5580 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5581 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5582 /* IP12_7_6 [2] */
5583 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5584 /* IP12_5_4 [2] */
5585 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5586 /* IP12_3_2 [2] */
5587 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5588 /* IP12_1_0 [2] */
5589 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
5590 },
5591 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5592 GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
5593 GROUP(
5594 /* IP13_31 [1] RESERVED */
5595 /* IP13_30_29 [2] */
5596 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5597 /* IP13_28_26 [3] */
5598 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5599 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5600 /* IP13_25_23 [3] */
5601 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5602 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5603 /* IP13_22_19 [4] */
5604 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5605 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5606 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5607 /* IP13_18_16 [3] */
5608 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5609 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5610 /* IP13_15_13 [3] */
5611 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5612 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5613 /* IP13_12_10 [3] */
5614 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5615 FN_CAN_DEBUGOUT8, 0, 0,
5616 /* IP13_9_7 [3] */
5617 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5618 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5619 /* IP13_6_3 [4] */
5620 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5621 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5622 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5623 /* IP13_2_0 [3] */
5624 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5625 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
5626 },
5627 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5628 GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
5629 GROUP(
5630 /* IP14_30 [1] RESERVED */
5631 /* IP14_30_28 [3] */
5632 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5633 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5634 FN_HRTS0_N_C, 0,
5635 /* IP14_27_25 [3] */
5636 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5637 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5638 /* IP14_24_22 [3] */
5639 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5640 FN_LCDOUT9, 0, 0, 0,
5641 /* IP14_21_19 [3] */
5642 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5643 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5644 /* IP14_18_16 [3] */
5645 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5646 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5647 /* IP14_15_12 [4] */
5648 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5649 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5650 0, 0, 0, 0, 0, 0, 0,
5651 /* IP14_11_9 [3] */
5652 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5653 0, 0, 0,
5654 /* IP14_8_6 [3] */
5655 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5656 0, 0, 0,
5657 /* IP14_5_3 [3] */
5658 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5659 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5660 /* IP14_2_0 [3] */
5661 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5662 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5663 FN_REMOCON, 0, ))
5664 },
5665 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5666 GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
5667 GROUP(
5668 /* IP15_31_30 [2] RESERVED */
5669 /* IP15_29_28 [2] */
5670 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5671 /* IP15_27_26 [2] */
5672 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5673 /* IP15_25_23 [3] */
5674 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5675 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5676 /* IP15_22_20 [3] */
5677 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5678 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5679 /* IP15_19_18 [2] */
5680 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5681 /* IP15_17_16 [2] */
5682 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5683 /* IP15_15_14 [2] */
5684 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5685 /* IP15_13_12 [2] */
5686 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5687 /* IP15_11_9 [3] */
5688 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5689 0, 0, 0,
5690 /* IP15_8_6 [3] */
5691 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5692 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5693 /* IP15_5_3 [3] */
5694 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5695 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5696 /* IP15_2_0 [3] */
5697 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5698 FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
5699 },
5700 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5701 GROUP(-24, 1, 1, 3, 3),
5702 GROUP(
5703 /* IP16_31_8 [24] RESERVED */
5704 /* IP16_7 [1] */
5705 FN_USB1_OVC, FN_TCLK1_B,
5706 /* IP16_6 [1] */
5707 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5708 /* IP16_5_3 [3] */
5709 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5710 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5711 /* IP16_2_0 [3] */
5712 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5713 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
5714 },
5715 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5716 GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
5717 1, 1, 1, 2, -1, 1, 2, 1, 1),
5718 GROUP(
5719 /* SEL_SCIF1 [3] */
5720 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5721 FN_SEL_SCIF1_4, 0, 0, 0,
5722 /* SEL_SCIFB [2] */
5723 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5724 /* SEL_SCIFB2 [2] */
5725 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5726 /* SEL_SCIFB1 [3] */
5727 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5728 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5729 FN_SEL_SCIFB1_6, 0,
5730 /* SEL_SCIFA1 [2] */
5731 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5732 FN_SEL_SCIFA1_3,
5733 /* SEL_SCIF0 [1] */
5734 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5735 /* SEL_SCIFA [1] */
5736 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5737 /* SEL_SOF1 [1] */
5738 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5739 /* SEL_SSI7 [2] */
5740 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5741 /* SEL_SSI6 [1] */
5742 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5743 /* SEL_SSI5 [2] */
5744 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5745 /* SEL_VI3 [1] */
5746 FN_SEL_VI3_0, FN_SEL_VI3_1,
5747 /* SEL_VI2 [1] */
5748 FN_SEL_VI2_0, FN_SEL_VI2_1,
5749 /* SEL_VI1 [1] */
5750 FN_SEL_VI1_0, FN_SEL_VI1_1,
5751 /* SEL_VI0 [1] */
5752 FN_SEL_VI0_0, FN_SEL_VI0_1,
5753 /* SEL_TSIF1 [2] */
5754 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5755 /* RESERVED [1] */
5756 /* SEL_LBS [1] */
5757 FN_SEL_LBS_0, FN_SEL_LBS_1,
5758 /* SEL_TSIF0 [2] */
5759 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5760 /* SEL_SOF3 [1] */
5761 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5762 /* SEL_SOF0 [1] */
5763 FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
5764 },
5765 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5766 GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1,
5767 3, 3, 2, -3, 2, 2),
5768 GROUP(
5769 /* RESERVED [3] */
5770 /* SEL_TMU1 [1] */
5771 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5772 /* SEL_HSCIF1 [1] */
5773 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5774 /* SEL_SCIFCLK [1] */
5775 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5776 /* SEL_CAN0 [2] */
5777 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5778 /* SEL_CANCLK [1] */
5779 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5780 /* SEL_SCIFA2 [2] */
5781 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5782 /* SEL_CAN1 [1] */
5783 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5784 /* RESERVED [2] */
5785 /* SEL_SCIF2 [1] */
5786 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5787 /* SEL_ADI [1] */
5788 FN_SEL_ADI_0, FN_SEL_ADI_1,
5789 /* SEL_SSP [1] */
5790 FN_SEL_SSP_0, FN_SEL_SSP_1,
5791 /* SEL_FM [3] */
5792 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5793 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5794 /* SEL_HSCIF0 [3] */
5795 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5796 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5797 /* SEL_GPS [2] */
5798 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5799 /* RESERVED [3] */
5800 /* SEL_SIM [2] */
5801 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5802 /* SEL_SSI8 [2] */
5803 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
5804 },
5805 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5806 GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2),
5807 GROUP(
5808 /* SEL_IICDVFS [1] */
5809 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5810 /* SEL_IIC0 [1] */
5811 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5812 /* RESERVED [12] */
5813 /* SEL_IEB [2] */
5814 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5815 /* RESERVED [6] */
5816 /* SEL_IIC2 [3] */
5817 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5818 FN_SEL_IIC2_4, 0, 0, 0,
5819 /* SEL_IIC1 [2] */
5820 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5821 /* SEL_I2C2 [3] */
5822 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5823 FN_SEL_I2C2_4, 0, 0, 0,
5824 /* SEL_I2C1 [2] */
5825 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
5826 },
5827 { /* sentinel */ }
5828 };
5829
r8a7790_pin_to_pocctrl(unsigned int pin,u32 * pocctrl)5830 static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5831 {
5832 if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
5833 return -EINVAL;
5834
5835 *pocctrl = 0xe606008c;
5836
5837 return 31 - (pin & 0x1f);
5838 }
5839
5840 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5841 { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) {
5842 [ 0] = RCAR_GP_PIN(0, 16), /* A0 */
5843 [ 1] = RCAR_GP_PIN(0, 17), /* A1 */
5844 [ 2] = RCAR_GP_PIN(0, 18), /* A2 */
5845 [ 3] = RCAR_GP_PIN(0, 19), /* A3 */
5846 [ 4] = RCAR_GP_PIN(0, 20), /* A4 */
5847 [ 5] = RCAR_GP_PIN(0, 21), /* A5 */
5848 [ 6] = RCAR_GP_PIN(0, 22), /* A6 */
5849 [ 7] = RCAR_GP_PIN(0, 23), /* A7 */
5850 [ 8] = RCAR_GP_PIN(0, 24), /* A8 */
5851 [ 9] = RCAR_GP_PIN(0, 25), /* A9 */
5852 [10] = RCAR_GP_PIN(0, 26), /* A10 */
5853 [11] = RCAR_GP_PIN(0, 27), /* A11 */
5854 [12] = RCAR_GP_PIN(0, 28), /* A12 */
5855 [13] = RCAR_GP_PIN(0, 29), /* A13 */
5856 [14] = RCAR_GP_PIN(0, 30), /* A14 */
5857 [15] = RCAR_GP_PIN(0, 31), /* A15 */
5858 [16] = RCAR_GP_PIN(1, 0), /* A16 */
5859 [17] = RCAR_GP_PIN(1, 1), /* A17 */
5860 [18] = RCAR_GP_PIN(1, 2), /* A18 */
5861 [19] = RCAR_GP_PIN(1, 3), /* A19 */
5862 [20] = RCAR_GP_PIN(1, 4), /* A20 */
5863 [21] = RCAR_GP_PIN(1, 5), /* A21 */
5864 [22] = RCAR_GP_PIN(1, 6), /* A22 */
5865 [23] = RCAR_GP_PIN(1, 7), /* A23 */
5866 [24] = RCAR_GP_PIN(1, 8), /* A24 */
5867 [25] = RCAR_GP_PIN(1, 9), /* A25 */
5868 [26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */
5869 [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */
5870 [28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */
5871 [29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */
5872 [30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */
5873 [31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */
5874 } },
5875 { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) {
5876 /* PUPR1 pull-up pins */
5877 [ 0] = RCAR_GP_PIN(1, 18), /* BS# */
5878 [ 1] = RCAR_GP_PIN(1, 19), /* RD# */
5879 [ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */
5880 [ 3] = RCAR_GP_PIN(1, 21), /* WE0# */
5881 [ 4] = RCAR_GP_PIN(1, 22), /* WE1# */
5882 [ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */
5883 [ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */
5884 [ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */
5885 [ 8] = RCAR_GP_PIN(1, 10), /* CS0# */
5886 [ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */
5887 [10] = PIN_TRST_N, /* TRST# */
5888 [11] = PIN_TCK, /* TCK */
5889 [12] = PIN_TMS, /* TMS */
5890 [13] = PIN_TDI, /* TDI */
5891 [14] = SH_PFC_PIN_NONE,
5892 [15] = SH_PFC_PIN_NONE,
5893 [16] = RCAR_GP_PIN(0, 0), /* D0 */
5894 [17] = RCAR_GP_PIN(0, 1), /* D1 */
5895 [18] = RCAR_GP_PIN(0, 2), /* D2 */
5896 [19] = RCAR_GP_PIN(0, 3), /* D3 */
5897 [20] = RCAR_GP_PIN(0, 4), /* D4 */
5898 [21] = RCAR_GP_PIN(0, 5), /* D5 */
5899 [22] = RCAR_GP_PIN(0, 6), /* D6 */
5900 [23] = RCAR_GP_PIN(0, 7), /* D7 */
5901 [24] = RCAR_GP_PIN(0, 8), /* D8 */
5902 [25] = RCAR_GP_PIN(0, 9), /* D9 */
5903 [26] = RCAR_GP_PIN(0, 10), /* D10 */
5904 [27] = RCAR_GP_PIN(0, 11), /* D11 */
5905 [28] = RCAR_GP_PIN(0, 12), /* D12 */
5906 [29] = RCAR_GP_PIN(0, 13), /* D13 */
5907 [30] = RCAR_GP_PIN(0, 14), /* D14 */
5908 [31] = RCAR_GP_PIN(0, 15), /* D15 */
5909 } },
5910 { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) {
5911 /* PUPR1 pull-down pins */
5912 [ 0] = SH_PFC_PIN_NONE,
5913 [ 1] = SH_PFC_PIN_NONE,
5914 [ 2] = SH_PFC_PIN_NONE,
5915 [ 3] = SH_PFC_PIN_NONE,
5916 [ 4] = SH_PFC_PIN_NONE,
5917 [ 5] = SH_PFC_PIN_NONE,
5918 [ 6] = SH_PFC_PIN_NONE,
5919 [ 7] = SH_PFC_PIN_NONE,
5920 [ 8] = SH_PFC_PIN_NONE,
5921 [ 9] = SH_PFC_PIN_NONE,
5922 [10] = SH_PFC_PIN_NONE,
5923 [11] = SH_PFC_PIN_NONE,
5924 [12] = SH_PFC_PIN_NONE,
5925 [13] = SH_PFC_PIN_NONE,
5926 [14] = SH_PFC_PIN_NONE,
5927 [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */
5928 [16] = SH_PFC_PIN_NONE,
5929 [17] = SH_PFC_PIN_NONE,
5930 [18] = SH_PFC_PIN_NONE,
5931 [19] = SH_PFC_PIN_NONE,
5932 [20] = SH_PFC_PIN_NONE,
5933 [21] = SH_PFC_PIN_NONE,
5934 [22] = SH_PFC_PIN_NONE,
5935 [23] = SH_PFC_PIN_NONE,
5936 [24] = SH_PFC_PIN_NONE,
5937 [25] = SH_PFC_PIN_NONE,
5938 [26] = SH_PFC_PIN_NONE,
5939 [27] = SH_PFC_PIN_NONE,
5940 [28] = SH_PFC_PIN_NONE,
5941 [29] = SH_PFC_PIN_NONE,
5942 [30] = SH_PFC_PIN_NONE,
5943 [31] = SH_PFC_PIN_NONE,
5944 } },
5945 { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) {
5946 [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */
5947 [ 1] = SH_PFC_PIN_NONE,
5948 [ 2] = SH_PFC_PIN_NONE,
5949 [ 3] = SH_PFC_PIN_NONE,
5950 [ 4] = SH_PFC_PIN_NONE,
5951 [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */
5952 [ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */
5953 [ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */
5954 [ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */
5955 [ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */
5956 [10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */
5957 [11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */
5958 [12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */
5959 [13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */
5960 [14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */
5961 [15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */
5962 [16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */
5963 [17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */
5964 [18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */
5965 [19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */
5966 [20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */
5967 [21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */
5968 [22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */
5969 [23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */
5970 [24] = SH_PFC_PIN_NONE,
5971 [25] = SH_PFC_PIN_NONE,
5972 [26] = SH_PFC_PIN_NONE,
5973 [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */
5974 [28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */
5975 [29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */
5976 [30] = SH_PFC_PIN_NONE,
5977 [31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */
5978 } },
5979 { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) {
5980 [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5981 [ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5982 [ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5983 [ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5984 [ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5985 [ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5986 [ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */
5987 [ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */
5988 [ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */
5989 [ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */
5990 [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */
5991 [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */
5992 [12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */
5993 [13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */
5994 [14] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5995 [15] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5996 [16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */
5997 [17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */
5998 [18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */
5999 [19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */
6000 [20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */
6001 [21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */
6002 [22] = RCAR_GP_PIN(3, 22), /* SD2_CD */
6003 [23] = RCAR_GP_PIN(3, 23), /* SD2_WP */
6004 [24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */
6005 [25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */
6006 [26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */
6007 [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */
6008 [28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */
6009 [29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */
6010 [30] = RCAR_GP_PIN(3, 30), /* SD3_CD */
6011 [31] = RCAR_GP_PIN(3, 31), /* SD3_WP */
6012 } },
6013 { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) {
6014 [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */
6015 [ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */
6016 [ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */
6017 [ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */
6018 [ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */
6019 [ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */
6020 [ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */
6021 [ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */
6022 [ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */
6023 [ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */
6024 [10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */
6025 [11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */
6026 [12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */
6027 [13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */
6028 [14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */
6029 [15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */
6030 [16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */
6031 [17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */
6032 [18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */
6033 [19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */
6034 [20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */
6035 [21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */
6036 [22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */
6037 [23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */
6038 [24] = RCAR_GP_PIN(1, 24), /* DREQ0 */
6039 [25] = RCAR_GP_PIN(1, 25), /* DACK0 */
6040 [26] = RCAR_GP_PIN(1, 26), /* DREQ1 */
6041 [27] = RCAR_GP_PIN(1, 27), /* DACK1 */
6042 [28] = RCAR_GP_PIN(1, 28), /* DREQ2 */
6043 [29] = RCAR_GP_PIN(1, 29), /* DACK2 */
6044 [30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */
6045 [31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */
6046 } },
6047 { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) {
6048 [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */
6049 [ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */
6050 [ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */
6051 [ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */
6052 [ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */
6053 [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */
6054 [ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */
6055 [ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */
6056 [ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */
6057 [ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */
6058 [10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */
6059 [11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */
6060 [12] = RCAR_GP_PIN(5, 7), /* HSCK0 */
6061 [13] = RCAR_GP_PIN(5, 8), /* HRX0 */
6062 [14] = RCAR_GP_PIN(5, 9), /* HTX0 */
6063 [15] = RCAR_GP_PIN(5, 10), /* HCTS0# */
6064 [16] = RCAR_GP_PIN(5, 11), /* HRTS0# */
6065 [17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */
6066 [18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
6067 [19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
6068 [20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */
6069 [21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */
6070 [22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */
6071 [23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */
6072 [24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */
6073 [25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */
6074 [26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */
6075 [27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */
6076 [28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */
6077 [29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */
6078 [30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */
6079 [31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */
6080 } },
6081 { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) {
6082 [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */
6083 [ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */
6084 [ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */
6085 [ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */
6086 [ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */
6087 [ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */
6088 [ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */
6089 [ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */
6090 [ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */
6091 [ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */
6092 [10] = SH_PFC_PIN_NONE,
6093 [11] = SH_PFC_PIN_NONE,
6094 [12] = SH_PFC_PIN_NONE,
6095 [13] = SH_PFC_PIN_NONE,
6096 [14] = SH_PFC_PIN_NONE,
6097 [15] = SH_PFC_PIN_NONE,
6098 [16] = SH_PFC_PIN_NONE,
6099 [17] = SH_PFC_PIN_NONE,
6100 [18] = SH_PFC_PIN_NONE,
6101 [19] = SH_PFC_PIN_NONE,
6102 [20] = SH_PFC_PIN_NONE,
6103 [21] = SH_PFC_PIN_NONE,
6104 [22] = SH_PFC_PIN_NONE,
6105 [23] = SH_PFC_PIN_NONE,
6106 [24] = SH_PFC_PIN_NONE,
6107 [25] = SH_PFC_PIN_NONE,
6108 [26] = SH_PFC_PIN_NONE,
6109 [27] = SH_PFC_PIN_NONE,
6110 [28] = SH_PFC_PIN_NONE,
6111 [29] = SH_PFC_PIN_NONE,
6112 [30] = SH_PFC_PIN_NONE,
6113 [31] = SH_PFC_PIN_NONE,
6114 } },
6115 { /* sentinel */ }
6116 };
6117
6118 static const struct soc_device_attribute r8a7790_tdsel[] = {
6119 { .soc_id = "r8a7790", .revision = "ES1.0" },
6120 { /* sentinel */ }
6121 };
6122
r8a7790_pinmux_soc_init(struct sh_pfc * pfc)6123 static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
6124 {
6125 /* Initialize TDSEL on old revisions */
6126 if (soc_device_match(r8a7790_tdsel))
6127 sh_pfc_write(pfc, 0xe6060088, 0x00155554);
6128
6129 return 0;
6130 }
6131
6132 static const struct sh_pfc_soc_operations r8a7790_pfc_ops = {
6133 .init = r8a7790_pinmux_soc_init,
6134 .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
6135 .get_bias = rcar_pinmux_get_bias,
6136 .set_bias = rcar_pinmux_set_bias,
6137 };
6138
6139 #ifdef CONFIG_PINCTRL_PFC_R8A7742
6140 const struct sh_pfc_soc_info r8a7742_pinmux_info = {
6141 .name = "r8a77420_pfc",
6142 .ops = &r8a7790_pfc_ops,
6143 .unlock_reg = 0xe6060000, /* PMMR */
6144
6145 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6146
6147 .pins = pinmux_pins,
6148 .nr_pins = ARRAY_SIZE(pinmux_pins),
6149 .groups = pinmux_groups.common,
6150 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6151 .functions = pinmux_functions.common,
6152 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6153
6154 .cfg_regs = pinmux_config_regs,
6155 .bias_regs = pinmux_bias_regs,
6156
6157 .pinmux_data = pinmux_data,
6158 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6159 };
6160 #endif
6161
6162 #ifdef CONFIG_PINCTRL_PFC_R8A7790
6163 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
6164 .name = "r8a77900_pfc",
6165 .ops = &r8a7790_pfc_ops,
6166 .unlock_reg = 0xe6060000, /* PMMR */
6167
6168 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6169
6170 .pins = pinmux_pins,
6171 .nr_pins = ARRAY_SIZE(pinmux_pins),
6172 .groups = pinmux_groups.common,
6173 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6174 ARRAY_SIZE(pinmux_groups.automotive),
6175 .functions = pinmux_functions.common,
6176 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6177 ARRAY_SIZE(pinmux_functions.automotive),
6178
6179 .cfg_regs = pinmux_config_regs,
6180 .bias_regs = pinmux_bias_regs,
6181
6182 .pinmux_data = pinmux_data,
6183 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6184 };
6185 #endif
6186