Home
last modified time | relevance | path

Searched refs:sdma_rlc_reg_offset (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_arcturus.c73 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
115 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
119 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
121 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
128 uint32_t sdma_rlc_reg_offset; in kgd_arcturus_hqd_sdma_load() local
135 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_arcturus_hqd_sdma_load()
138 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_arcturus_hqd_sdma_load()
143 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_arcturus_hqd_sdma_load()
153 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_arcturus_hqd_sdma_load()
158 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_arcturus_hqd_sdma_load()
[all …]
Damdgpu_amdkfd_gc_9_4_3.c63 uint32_t sdma_rlc_reg_offset; in kgd_gfx_v9_4_3_hqd_sdma_load() local
70 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_gfx_v9_4_3_hqd_sdma_load()
73 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_CNTL, in kgd_gfx_v9_4_3_hqd_sdma_load()
78 data = RREG32(sdma_rlc_reg_offset + regSDMA_RLC0_CONTEXT_STATUS); in kgd_gfx_v9_4_3_hqd_sdma_load()
88 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL_OFFSET, in kgd_gfx_v9_4_3_hqd_sdma_load()
93 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_DOORBELL, data); in kgd_gfx_v9_4_3_hqd_sdma_load()
94 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR, in kgd_gfx_v9_4_3_hqd_sdma_load()
96 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_RPTR_HI, in kgd_gfx_v9_4_3_hqd_sdma_load()
99 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_MINOR_PTR_UPDATE, 1); in kgd_gfx_v9_4_3_hqd_sdma_load()
101 WREG32(sdma_rlc_reg_offset + regSDMA_RLC0_RB_WPTR, in kgd_gfx_v9_4_3_hqd_sdma_load()
[all …]
Damdgpu_amdkfd_gfx_v10_3.c134 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
160 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
164 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
166 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
363 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v10_3() local
370 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in hqd_sdma_load_v10_3()
373 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in hqd_sdma_load_v10_3()
378 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in hqd_sdma_load_v10_3()
388 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in hqd_sdma_load_v10_3()
393 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in hqd_sdma_load_v10_3()
[all …]
Damdgpu_amdkfd_gfx_v11.c130 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
145 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
149 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
151 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
348 uint32_t sdma_rlc_reg_offset; in hqd_sdma_load_v11() local
355 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in hqd_sdma_load_v11()
358 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, in hqd_sdma_load_v11()
363 data = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_CONTEXT_STATUS); in hqd_sdma_load_v11()
373 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL_OFFSET, in hqd_sdma_load_v11()
378 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_DOORBELL, data); in hqd_sdma_load_v11()
[all …]
Damdgpu_amdkfd_gfx_v7.c244 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
248 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load()
250 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
255 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
267 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
268 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
272 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
274 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
277 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load()
279 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); in kgd_hqd_sdma_load()
[all …]
Damdgpu_amdkfd_gfx_v8.c268 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
272 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); in kgd_hqd_sdma_load()
273 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
278 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
290 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
291 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
295 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
297 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
300 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load()
302 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load()
[all …]
Damdgpu_amdkfd_gfx_v10.c377 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
384 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_hqd_sdma_load()
387 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
392 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
402 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_hqd_sdma_load()
407 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
410 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, in kgd_hqd_sdma_load()
413 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); in kgd_hqd_sdma_load()
415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
[all …]
Damdgpu_amdkfd_gfx_v9.c185 uint32_t sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset() local
203 sdma_rlc_reg_offset = sdma_engine_reg_base in get_sdma_rlc_reg_offset()
207 queue_id, sdma_rlc_reg_offset); in get_sdma_rlc_reg_offset()
209 return sdma_rlc_reg_offset; in get_sdma_rlc_reg_offset()
390 uint32_t sdma_rlc_reg_offset; in kgd_hqd_sdma_load() local
397 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, in kgd_hqd_sdma_load()
400 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
405 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); in kgd_hqd_sdma_load()
415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, in kgd_hqd_sdma_load()
420 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
[all …]