| /drivers/clk/mediatek/ |
| D | clk-mt8183-ipu_conn.c | 15 .set_ofs = 0x4,
21 .set_ofs = 0x10,
27 .set_ofs = 0x18,
33 .set_ofs = 0x1c,
39 .set_ofs = 0x20,
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| D | clk-mt8186-vdec.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x190,
28 .set_ofs = 0x200,
34 .set_ofs = 0x8,
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| D | clk-mt8195-vdo1.c | 14 .set_ofs = 0x104,
20 .set_ofs = 0x124,
26 .set_ofs = 0x134,
32 .set_ofs = 0x144,
38 .set_ofs = 0x400,
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| D | clk-mt8188-vdo1.c | 17 .set_ofs = 0x104,
23 .set_ofs = 0x114,
29 .set_ofs = 0x124,
35 .set_ofs = 0x134,
41 .set_ofs = 0x144,
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| D | clk-gate.c | 20 int set_ofs; member
55 regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); in mtk_cg_set_bit()
157 struct regmap *regmap, int set_ofs, in mtk_clk_register_gate() argument
177 cg->set_ofs = set_ofs; in mtk_clk_register_gate()
233 gate->regs->set_ofs, in mtk_clk_register_gates()
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| D | clk-mt8365.c | 574 .set_ofs = 0,
580 .set_ofs = 0x104,
586 .set_ofs = 0x320,
626 .set_ofs = 0x80,
632 .set_ofs = 0x88,
638 .set_ofs = 0xa4,
644 .set_ofs = 0xc0,
650 .set_ofs = 0xd0,
755 .set_ofs = 0x20c,
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| D | clk-mt8188-infra_ao.c | 16 .set_ofs = 0x80,
22 .set_ofs = 0x88,
28 .set_ofs = 0xa4,
34 .set_ofs = 0xc0,
40 .set_ofs = 0xe0,
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| D | clk-mt7622-aud.c | 32 .set_ofs = 0x0,
38 .set_ofs = 0x10,
44 .set_ofs = 0x14,
50 .set_ofs = 0x634,
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| D | clk-mt2701-aud.c | 31 .set_ofs = 0x0,
37 .set_ofs = 0x10,
43 .set_ofs = 0x14,
49 .set_ofs = 0x634,
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| D | clk-mt8195-infra_ao.c | 15 .set_ofs = 0x80,
21 .set_ofs = 0x88,
27 .set_ofs = 0xa4,
33 .set_ofs = 0xc0,
39 .set_ofs = 0xe0,
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| D | clk-mt8188-vdec.c | 15 .set_ofs = 0x0,
21 .set_ofs = 0x200,
27 .set_ofs = 0x8,
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| D | clk-mt8192-vdec.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x200,
28 .set_ofs = 0x8,
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| D | clk-mt8195-vdec.c | 14 .set_ofs = 0x0,
20 .set_ofs = 0x200,
26 .set_ofs = 0x8,
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| D | clk-mt7986-eth.c | 18 .set_ofs = 0xe4,
34 .set_ofs = 0xe4,
50 .set_ofs = 0x30,
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| D | clk-mt7981-eth.c | 20 .set_ofs = 0xE4,
42 .set_ofs = 0xE4,
64 .set_ofs = 0x30,
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| D | clk-mt8188-wpe.c | 17 .set_ofs = 0x0,
23 .set_ofs = 0x58,
29 .set_ofs = 0x5c,
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| D | clk-mt8195-vpp0.c | 14 .set_ofs = 0x24,
20 .set_ofs = 0x30,
26 .set_ofs = 0x3c,
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| D | clk-mt8188-vdo0.c | 17 .set_ofs = 0x104,
23 .set_ofs = 0x114,
29 .set_ofs = 0x124,
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| D | clk-mt8192-mm.c | 15 .set_ofs = 0x104,
21 .set_ofs = 0x114,
27 .set_ofs = 0x1a4,
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| D | clk-mt8188-vpp0.c | 15 .set_ofs = 0x24,
21 .set_ofs = 0x30,
27 .set_ofs = 0x3c,
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| D | clk-mt8192-aud.c | 16 .set_ofs = 0x0,
22 .set_ofs = 0x4,
28 .set_ofs = 0x8,
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| D | clk-mt8192.c | 714 .set_ofs = 0x80,
720 .set_ofs = 0x88,
726 .set_ofs = 0xa4,
732 .set_ofs = 0xc0,
738 .set_ofs = 0xd0,
744 .set_ofs = 0xe0,
916 .set_ofs = 0x20c,
929 .set_ofs = 0x150,
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| D | clk-mt8195-vdo0.c | 14 .set_ofs = 0x104,
20 .set_ofs = 0x114,
26 .set_ofs = 0x124,
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| D | clk-mt2712-mm.c | 16 .set_ofs = 0x104,
22 .set_ofs = 0x114,
28 .set_ofs = 0x224,
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| D | clk-mt8195-wpe.c | 14 .set_ofs = 0x0,
20 .set_ofs = 0x58,
26 .set_ofs = 0x5c,
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