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/drivers/pinctrl/renesas/
Dsh_pfc.h441 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ argument
442 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
443 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) argument
445 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ argument
446 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
447 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg)
448 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) argument
450 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ argument
451 PORT_GP_CFG_2(bank, fn, sfx, cfg), \
452 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
[all …]
Dpfc-r8a73a4.c13 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
15 PORT_10(0, fn, pfx, sfx), \
16 PORT_10(10, fn, pfx##1, sfx), \
17 PORT_10(20, fn, pfx##2, sfx), \
18 PORT_1(30, fn, pfx##30, sfx), \
20 PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
21 PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
22 PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
23 PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
24 PORT_1(40, fn, pfx##40, sfx), \
[all …]
Dpfc-r8a779a0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_15(0, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_1(0, 15, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(0, 16, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
22 PORT_GP_CFG_1(0, 17, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
23 PORT_GP_CFG_1(0, 18, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
24 PORT_GP_CFG_1(0, 19, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
25 PORT_GP_CFG_1(0, 20, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(0, 21, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(0, 22, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
[all …]
Dpfc-sh73a0.c18 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
19 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
20 PORT_10(100, fn, pfx##10, sfx), \
21 PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
22 PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
23 PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
24 PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
25 PORT_1(118, fn, pfx##118, sfx), \
26 PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
27 PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
[all …]
Dpfc-emev2.c11 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
12 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
13 PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
14 PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
15 PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
16 PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
17 PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
18 PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
19 PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
244 #define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0) argument
[all …]
Dpfc-r8a77470.c13 #define CPU_ALL_GP(fn, sfx) \ argument
14 PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
[all …]
Dpfc-r8a7794.c17 #define CPU_ALL_GP(fn, sfx) \ argument
18 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_1(5, 7, fn, sfx), \
25 PORT_GP_1(5, 8, fn, sfx), \
26 PORT_GP_1(5, 9, fn, sfx), \
[all …]
Dpfc-r8a7779.c14 #define CPU_ALL_GP(fn, sfx) \ argument
15 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_1(2, 0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_1(2, 1, fn, sfx), \
19 PORT_GP_1(2, 2, fn, sfx), \
20 PORT_GP_1(2, 3, fn, sfx), \
21 PORT_GP_1(2, 4, fn, sfx), \
22 PORT_GP_1(2, 5, fn, sfx), \
23 PORT_GP_1(2, 6, fn, sfx), \
[all …]
Dpfc-r8a779g0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_19(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(1, 23, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(1, 24, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(1, 25, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(1, 26, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(1, 27, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(1, 28, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_20(2, fn, sfx, CFG_FLAGS), \
[all …]
Dpfc-r8a7791.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
[all …]
Dpfc-r8a7792.c13 #define CPU_ALL_GP(fn, sfx) \ argument
14 PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
15 PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
16 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
17 PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
18 PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
19 PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
20 PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
21 PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
22 PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
[all …]
Dpfc-r8a77990.c21 #define CPU_ALL_GP(fn, sfx) \ argument
22 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
25 …PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRE…
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 …PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_DRIVE_STRE…
[all …]
Dpfc-r8a7740.c14 #define CPU_ALL_PORT(fn, pfx, sfx) \ argument
15 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
16 PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
17 PORT_10(200, fn, pfx##20, sfx), \
18 PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
Dpfc-sh7734.c13 #define CPU_ALL_GP(fn, sfx) \ argument
14 PORT_GP_32(0, fn, sfx), \
15 PORT_GP_32(1, fn, sfx), \
16 PORT_GP_32(2, fn, sfx), \
17 PORT_GP_32(3, fn, sfx), \
18 PORT_GP_32(4, fn, sfx), \
19 PORT_GP_12(5, fn, sfx)
22 #define _GP_DATA(bank, pin, name, sfx, cfg) \ argument
25 #define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT argument
26 #define _GP_INDT(bank, pin, name, sfx, cfg) name##_DATA argument
Dpfc-r8a779f0.c18 #define CPU_ALL_GP(fn, sfx) \ argument
19 PORT_GP_CFG_21(0, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
20 PORT_GP_CFG_25(1, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_17(2, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_19(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
Dpfc-r8a77970.c21 #define CPU_ALL_GP(fn, sfx) \ argument
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
Dpfc-r8a77995.c20 #define CPU_ALL_GP(fn, sfx) \ argument
21 PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
22 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
Dpfc-r8a77980.c21 #define CPU_ALL_GP(fn, sfx) \ argument
22 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
Dpfc-r8a77951.c16 #define CPU_ALL_GP(fn, sfx) \ argument
17 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
18 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
19 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
20 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
[all …]
Dpfc-r8a7796.c21 #define CPU_ALL_GP(fn, sfx) \ argument
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
[all …]
Dpfc-r8a77965.c22 #define CPU_ALL_GP(fn, sfx) \ argument
23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
[all …]
Dpfc-r8a7778.c21 #define CPU_ALL_GP(fn, sfx) \ argument
22 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
23 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
24 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
Dpfc-r8a7790.c23 #define CPU_ALL_GP(fn, sfx) \ argument
24 PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
25 PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
26 PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
27 PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \
28 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
29 PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)