1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
4 *
5 * (C) Copyright 2014, 2015 Linaro Ltd.
6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
7 *
8 * CPPC describes a few methods for controlling CPU performance using
9 * information from a per CPU table called CPC. This table is described in
10 * the ACPI v5.0+ specification. The table consists of a list of
11 * registers which may be memory mapped or hardware registers and also may
12 * include some static integer values.
13 *
14 * CPU performance is on an abstract continuous scale as against a discretized
15 * P-state scale which is tied to CPU frequency only. In brief, the basic
16 * operation involves:
17 *
18 * - OS makes a CPU performance request. (Can provide min and max bounds)
19 *
20 * - Platform (such as BMC) is free to optimize request within requested bounds
21 * depending on power/thermal budgets etc.
22 *
23 * - Platform conveys its decision back to OS
24 *
25 * The communication between OS and platform occurs through another medium
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
27 * mechanism which includes doorbell semantics to indicate register updates.
28 * See drivers/mailbox/pcc.c for details on PCC.
29 *
30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
31 * above specifications.
32 */
33
34 #define pr_fmt(fmt) "ACPI CPPC: " fmt
35
36 #include <linux/delay.h>
37 #include <linux/iopoll.h>
38 #include <linux/ktime.h>
39 #include <linux/rwsem.h>
40 #include <linux/wait.h>
41 #include <linux/topology.h>
42
43 #include <acpi/cppc_acpi.h>
44
45 struct cppc_pcc_data {
46 struct pcc_mbox_chan *pcc_channel;
47 void __iomem *pcc_comm_addr;
48 bool pcc_channel_acquired;
49 unsigned int deadline_us;
50 unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
51
52 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */
53 bool platform_owns_pcc; /* Ownership of PCC subspace */
54 unsigned int pcc_write_cnt; /* Running count of PCC write commands */
55
56 /*
57 * Lock to provide controlled access to the PCC channel.
58 *
59 * For performance critical usecases(currently cppc_set_perf)
60 * We need to take read_lock and check if channel belongs to OSPM
61 * before reading or writing to PCC subspace
62 * We need to take write_lock before transferring the channel
63 * ownership to the platform via a Doorbell
64 * This allows us to batch a number of CPPC requests if they happen
65 * to originate in about the same time
66 *
67 * For non-performance critical usecases(init)
68 * Take write_lock for all purposes which gives exclusive access
69 */
70 struct rw_semaphore pcc_lock;
71
72 /* Wait queue for CPUs whose requests were batched */
73 wait_queue_head_t pcc_write_wait_q;
74 ktime_t last_cmd_cmpl_time;
75 ktime_t last_mpar_reset;
76 int mpar_count;
77 int refcount;
78 };
79
80 /* Array to represent the PCC channel per subspace ID */
81 static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
82 /* The cpu_pcc_subspace_idx contains per CPU subspace ID */
83 static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
84
85 /*
86 * The cpc_desc structure contains the ACPI register details
87 * as described in the per CPU _CPC tables. The details
88 * include the type of register (e.g. PCC, System IO, FFH etc.)
89 * and destination addresses which lets us READ/WRITE CPU performance
90 * information using the appropriate I/O methods.
91 */
92 static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
93
94 /* pcc mapped address + header size + offset within PCC subspace */
95 #define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
96 0x8 + (offs))
97
98 /* Check if a CPC register is in PCC */
99 #define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
100 (cpc)->cpc_entry.reg.space_id == \
101 ACPI_ADR_SPACE_PLATFORM_COMM)
102
103 /* Check if a CPC register is in SystemMemory */
104 #define CPC_IN_SYSTEM_MEMORY(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
105 (cpc)->cpc_entry.reg.space_id == \
106 ACPI_ADR_SPACE_SYSTEM_MEMORY)
107
108 /* Check if a CPC register is in SystemIo */
109 #define CPC_IN_SYSTEM_IO(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
110 (cpc)->cpc_entry.reg.space_id == \
111 ACPI_ADR_SPACE_SYSTEM_IO)
112
113 /* Evaluates to True if reg is a NULL register descriptor */
114 #define IS_NULL_REG(reg) ((reg)->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY && \
115 (reg)->address == 0 && \
116 (reg)->bit_width == 0 && \
117 (reg)->bit_offset == 0 && \
118 (reg)->access_width == 0)
119
120 /* Evaluates to True if an optional cpc field is supported */
121 #define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ? \
122 !!(cpc)->cpc_entry.int_value : \
123 !IS_NULL_REG(&(cpc)->cpc_entry.reg))
124 /*
125 * Arbitrary Retries in case the remote processor is slow to respond
126 * to PCC commands. Keeping it high enough to cover emulators where
127 * the processors run painfully slow.
128 */
129 #define NUM_RETRIES 500ULL
130
131 #define OVER_16BTS_MASK ~0xFFFFULL
132
133 #define define_one_cppc_ro(_name) \
134 static struct kobj_attribute _name = \
135 __ATTR(_name, 0444, show_##_name, NULL)
136
137 #define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
138
139 #define show_cppc_data(access_fn, struct_name, member_name) \
140 static ssize_t show_##member_name(struct kobject *kobj, \
141 struct kobj_attribute *attr, char *buf) \
142 { \
143 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
144 struct struct_name st_name = {0}; \
145 int ret; \
146 \
147 ret = access_fn(cpc_ptr->cpu_id, &st_name); \
148 if (ret) \
149 return ret; \
150 \
151 return sysfs_emit(buf, "%llu\n", \
152 (u64)st_name.member_name); \
153 } \
154 define_one_cppc_ro(member_name)
155
156 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
157 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
158 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
159 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
160 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
161 show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
162
163 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
164 show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
165
166 /* Check for valid access_width, otherwise, fallback to using bit_width */
167 #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_width - 1)) : (reg)->bit_width)
168
169 /* Shift and apply the mask for CPC reads/writes */
170 #define MASK_VAL(reg, val) (((val) >> (reg)->bit_offset) & \
171 GENMASK(((reg)->bit_width) - 1, 0))
172
show_feedback_ctrs(struct kobject * kobj,struct kobj_attribute * attr,char * buf)173 static ssize_t show_feedback_ctrs(struct kobject *kobj,
174 struct kobj_attribute *attr, char *buf)
175 {
176 struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
177 struct cppc_perf_fb_ctrs fb_ctrs = {0};
178 int ret;
179
180 ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
181 if (ret)
182 return ret;
183
184 return sysfs_emit(buf, "ref:%llu del:%llu\n",
185 fb_ctrs.reference, fb_ctrs.delivered);
186 }
187 define_one_cppc_ro(feedback_ctrs);
188
189 static struct attribute *cppc_attrs[] = {
190 &feedback_ctrs.attr,
191 &reference_perf.attr,
192 &wraparound_time.attr,
193 &highest_perf.attr,
194 &lowest_perf.attr,
195 &lowest_nonlinear_perf.attr,
196 &nominal_perf.attr,
197 &nominal_freq.attr,
198 &lowest_freq.attr,
199 NULL
200 };
201 ATTRIBUTE_GROUPS(cppc);
202
203 static const struct kobj_type cppc_ktype = {
204 .sysfs_ops = &kobj_sysfs_ops,
205 .default_groups = cppc_groups,
206 };
207
check_pcc_chan(int pcc_ss_id,bool chk_err_bit)208 static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
209 {
210 int ret, status;
211 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
212 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
213 pcc_ss_data->pcc_comm_addr;
214
215 if (!pcc_ss_data->platform_owns_pcc)
216 return 0;
217
218 /*
219 * Poll PCC status register every 3us(delay_us) for maximum of
220 * deadline_us(timeout_us) until PCC command complete bit is set(cond)
221 */
222 ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
223 status & PCC_CMD_COMPLETE_MASK, 3,
224 pcc_ss_data->deadline_us);
225
226 if (likely(!ret)) {
227 pcc_ss_data->platform_owns_pcc = false;
228 if (chk_err_bit && (status & PCC_ERROR_MASK))
229 ret = -EIO;
230 }
231
232 if (unlikely(ret))
233 pr_err("PCC check channel failed for ss: %d. ret=%d\n",
234 pcc_ss_id, ret);
235
236 return ret;
237 }
238
239 /*
240 * This function transfers the ownership of the PCC to the platform
241 * So it must be called while holding write_lock(pcc_lock)
242 */
send_pcc_cmd(int pcc_ss_id,u16 cmd)243 static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
244 {
245 int ret = -EIO, i;
246 struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
247 struct acpi_pcct_shared_memory __iomem *generic_comm_base =
248 pcc_ss_data->pcc_comm_addr;
249 unsigned int time_delta;
250
251 /*
252 * For CMD_WRITE we know for a fact the caller should have checked
253 * the channel before writing to PCC space
254 */
255 if (cmd == CMD_READ) {
256 /*
257 * If there are pending cpc_writes, then we stole the channel
258 * before write completion, so first send a WRITE command to
259 * platform
260 */
261 if (pcc_ss_data->pending_pcc_write_cmd)
262 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
263
264 ret = check_pcc_chan(pcc_ss_id, false);
265 if (ret)
266 goto end;
267 } else /* CMD_WRITE */
268 pcc_ss_data->pending_pcc_write_cmd = FALSE;
269
270 /*
271 * Handle the Minimum Request Turnaround Time(MRTT)
272 * "The minimum amount of time that OSPM must wait after the completion
273 * of a command before issuing the next command, in microseconds"
274 */
275 if (pcc_ss_data->pcc_mrtt) {
276 time_delta = ktime_us_delta(ktime_get(),
277 pcc_ss_data->last_cmd_cmpl_time);
278 if (pcc_ss_data->pcc_mrtt > time_delta)
279 udelay(pcc_ss_data->pcc_mrtt - time_delta);
280 }
281
282 /*
283 * Handle the non-zero Maximum Periodic Access Rate(MPAR)
284 * "The maximum number of periodic requests that the subspace channel can
285 * support, reported in commands per minute. 0 indicates no limitation."
286 *
287 * This parameter should be ideally zero or large enough so that it can
288 * handle maximum number of requests that all the cores in the system can
289 * collectively generate. If it is not, we will follow the spec and just
290 * not send the request to the platform after hitting the MPAR limit in
291 * any 60s window
292 */
293 if (pcc_ss_data->pcc_mpar) {
294 if (pcc_ss_data->mpar_count == 0) {
295 time_delta = ktime_ms_delta(ktime_get(),
296 pcc_ss_data->last_mpar_reset);
297 if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
298 pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
299 pcc_ss_id);
300 ret = -EIO;
301 goto end;
302 }
303 pcc_ss_data->last_mpar_reset = ktime_get();
304 pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
305 }
306 pcc_ss_data->mpar_count--;
307 }
308
309 /* Write to the shared comm region. */
310 writew_relaxed(cmd, &generic_comm_base->command);
311
312 /* Flip CMD COMPLETE bit */
313 writew_relaxed(0, &generic_comm_base->status);
314
315 pcc_ss_data->platform_owns_pcc = true;
316
317 /* Ring doorbell */
318 ret = mbox_send_message(pcc_ss_data->pcc_channel->mchan, &cmd);
319 if (ret < 0) {
320 pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
321 pcc_ss_id, cmd, ret);
322 goto end;
323 }
324
325 /* wait for completion and check for PCC error bit */
326 ret = check_pcc_chan(pcc_ss_id, true);
327
328 if (pcc_ss_data->pcc_mrtt)
329 pcc_ss_data->last_cmd_cmpl_time = ktime_get();
330
331 if (pcc_ss_data->pcc_channel->mchan->mbox->txdone_irq)
332 mbox_chan_txdone(pcc_ss_data->pcc_channel->mchan, ret);
333 else
334 mbox_client_txdone(pcc_ss_data->pcc_channel->mchan, ret);
335
336 end:
337 if (cmd == CMD_WRITE) {
338 if (unlikely(ret)) {
339 for_each_possible_cpu(i) {
340 struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
341
342 if (!desc)
343 continue;
344
345 if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
346 desc->write_cmd_status = ret;
347 }
348 }
349 pcc_ss_data->pcc_write_cnt++;
350 wake_up_all(&pcc_ss_data->pcc_write_wait_q);
351 }
352
353 return ret;
354 }
355
cppc_chan_tx_done(struct mbox_client * cl,void * msg,int ret)356 static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
357 {
358 if (ret < 0)
359 pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
360 *(u16 *)msg, ret);
361 else
362 pr_debug("TX completed. CMD sent:%x, ret:%d\n",
363 *(u16 *)msg, ret);
364 }
365
366 static struct mbox_client cppc_mbox_cl = {
367 .tx_done = cppc_chan_tx_done,
368 .knows_txdone = true,
369 };
370
acpi_get_psd(struct cpc_desc * cpc_ptr,acpi_handle handle)371 static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
372 {
373 int result = -EFAULT;
374 acpi_status status = AE_OK;
375 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
376 struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
377 struct acpi_buffer state = {0, NULL};
378 union acpi_object *psd = NULL;
379 struct acpi_psd_package *pdomain;
380
381 status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
382 &buffer, ACPI_TYPE_PACKAGE);
383 if (status == AE_NOT_FOUND) /* _PSD is optional */
384 return 0;
385 if (ACPI_FAILURE(status))
386 return -ENODEV;
387
388 psd = buffer.pointer;
389 if (!psd || psd->package.count != 1) {
390 pr_debug("Invalid _PSD data\n");
391 goto end;
392 }
393
394 pdomain = &(cpc_ptr->domain_info);
395
396 state.length = sizeof(struct acpi_psd_package);
397 state.pointer = pdomain;
398
399 status = acpi_extract_package(&(psd->package.elements[0]),
400 &format, &state);
401 if (ACPI_FAILURE(status)) {
402 pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
403 goto end;
404 }
405
406 if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
407 pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
408 goto end;
409 }
410
411 if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
412 pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
413 goto end;
414 }
415
416 if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
417 pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
418 pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
419 pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
420 goto end;
421 }
422
423 result = 0;
424 end:
425 kfree(buffer.pointer);
426 return result;
427 }
428
acpi_cpc_valid(void)429 bool acpi_cpc_valid(void)
430 {
431 struct cpc_desc *cpc_ptr;
432 int cpu;
433
434 if (acpi_disabled)
435 return false;
436
437 for_each_present_cpu(cpu) {
438 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
439 if (!cpc_ptr)
440 return false;
441 }
442
443 return true;
444 }
445 EXPORT_SYMBOL_GPL(acpi_cpc_valid);
446
cppc_allow_fast_switch(void)447 bool cppc_allow_fast_switch(void)
448 {
449 struct cpc_register_resource *desired_reg;
450 struct cpc_desc *cpc_ptr;
451 int cpu;
452
453 for_each_possible_cpu(cpu) {
454 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
455 desired_reg = &cpc_ptr->cpc_regs[DESIRED_PERF];
456 if (!CPC_IN_SYSTEM_MEMORY(desired_reg) &&
457 !CPC_IN_SYSTEM_IO(desired_reg))
458 return false;
459 }
460
461 return true;
462 }
463 EXPORT_SYMBOL_GPL(cppc_allow_fast_switch);
464
465 /**
466 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
467 * @cpu: Find all CPUs that share a domain with cpu.
468 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
469 *
470 * Return: 0 for success or negative value for err.
471 */
acpi_get_psd_map(unsigned int cpu,struct cppc_cpudata * cpu_data)472 int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
473 {
474 struct cpc_desc *cpc_ptr, *match_cpc_ptr;
475 struct acpi_psd_package *match_pdomain;
476 struct acpi_psd_package *pdomain;
477 int count_target, i;
478
479 /*
480 * Now that we have _PSD data from all CPUs, let's setup P-state
481 * domain info.
482 */
483 cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
484 if (!cpc_ptr)
485 return -EFAULT;
486
487 pdomain = &(cpc_ptr->domain_info);
488 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
489 if (pdomain->num_processors <= 1)
490 return 0;
491
492 /* Validate the Domain info */
493 count_target = pdomain->num_processors;
494 if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
495 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
496 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
497 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
498 else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
499 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
500
501 for_each_possible_cpu(i) {
502 if (i == cpu)
503 continue;
504
505 match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
506 if (!match_cpc_ptr)
507 goto err_fault;
508
509 match_pdomain = &(match_cpc_ptr->domain_info);
510 if (match_pdomain->domain != pdomain->domain)
511 continue;
512
513 /* Here i and cpu are in the same domain */
514 if (match_pdomain->num_processors != count_target)
515 goto err_fault;
516
517 if (pdomain->coord_type != match_pdomain->coord_type)
518 goto err_fault;
519
520 cpumask_set_cpu(i, cpu_data->shared_cpu_map);
521 }
522
523 return 0;
524
525 err_fault:
526 /* Assume no coordination on any error parsing domain info */
527 cpumask_clear(cpu_data->shared_cpu_map);
528 cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
529 cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
530
531 return -EFAULT;
532 }
533 EXPORT_SYMBOL_GPL(acpi_get_psd_map);
534
register_pcc_channel(int pcc_ss_idx)535 static int register_pcc_channel(int pcc_ss_idx)
536 {
537 struct pcc_mbox_chan *pcc_chan;
538 u64 usecs_lat;
539
540 if (pcc_ss_idx >= 0) {
541 pcc_chan = pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
542
543 if (IS_ERR(pcc_chan)) {
544 pr_err("Failed to find PCC channel for subspace %d\n",
545 pcc_ss_idx);
546 return -ENODEV;
547 }
548
549 pcc_data[pcc_ss_idx]->pcc_channel = pcc_chan;
550 /*
551 * cppc_ss->latency is just a Nominal value. In reality
552 * the remote processor could be much slower to reply.
553 * So add an arbitrary amount of wait on top of Nominal.
554 */
555 usecs_lat = NUM_RETRIES * pcc_chan->latency;
556 pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
557 pcc_data[pcc_ss_idx]->pcc_mrtt = pcc_chan->min_turnaround_time;
558 pcc_data[pcc_ss_idx]->pcc_mpar = pcc_chan->max_access_rate;
559 pcc_data[pcc_ss_idx]->pcc_nominal = pcc_chan->latency;
560
561 pcc_data[pcc_ss_idx]->pcc_comm_addr =
562 acpi_os_ioremap(pcc_chan->shmem_base_addr,
563 pcc_chan->shmem_size);
564 if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
565 pr_err("Failed to ioremap PCC comm region mem for %d\n",
566 pcc_ss_idx);
567 return -ENOMEM;
568 }
569
570 /* Set flag so that we don't come here for each CPU. */
571 pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
572 }
573
574 return 0;
575 }
576
577 /**
578 * cpc_ffh_supported() - check if FFH reading supported
579 *
580 * Check if the architecture has support for functional fixed hardware
581 * read/write capability.
582 *
583 * Return: true for supported, false for not supported
584 */
cpc_ffh_supported(void)585 bool __weak cpc_ffh_supported(void)
586 {
587 return false;
588 }
589
590 /**
591 * cpc_supported_by_cpu() - check if CPPC is supported by CPU
592 *
593 * Check if the architectural support for CPPC is present even
594 * if the _OSC hasn't prescribed it
595 *
596 * Return: true for supported, false for not supported
597 */
cpc_supported_by_cpu(void)598 bool __weak cpc_supported_by_cpu(void)
599 {
600 return false;
601 }
602
603 /**
604 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
605 * @pcc_ss_id: PCC Subspace index as in the PCC client ACPI package.
606 *
607 * Check and allocate the cppc_pcc_data memory.
608 * In some processor configurations it is possible that same subspace
609 * is shared between multiple CPUs. This is seen especially in CPUs
610 * with hardware multi-threading support.
611 *
612 * Return: 0 for success, errno for failure
613 */
pcc_data_alloc(int pcc_ss_id)614 static int pcc_data_alloc(int pcc_ss_id)
615 {
616 if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
617 return -EINVAL;
618
619 if (pcc_data[pcc_ss_id]) {
620 pcc_data[pcc_ss_id]->refcount++;
621 } else {
622 pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
623 GFP_KERNEL);
624 if (!pcc_data[pcc_ss_id])
625 return -ENOMEM;
626 pcc_data[pcc_ss_id]->refcount++;
627 }
628
629 return 0;
630 }
631
632 /*
633 * An example CPC table looks like the following.
634 *
635 * Name (_CPC, Package() {
636 * 17, // NumEntries
637 * 1, // Revision
638 * ResourceTemplate() {Register(PCC, 32, 0, 0x120, 2)}, // Highest Performance
639 * ResourceTemplate() {Register(PCC, 32, 0, 0x124, 2)}, // Nominal Performance
640 * ResourceTemplate() {Register(PCC, 32, 0, 0x128, 2)}, // Lowest Nonlinear Performance
641 * ResourceTemplate() {Register(PCC, 32, 0, 0x12C, 2)}, // Lowest Performance
642 * ResourceTemplate() {Register(PCC, 32, 0, 0x130, 2)}, // Guaranteed Performance Register
643 * ResourceTemplate() {Register(PCC, 32, 0, 0x110, 2)}, // Desired Performance Register
644 * ResourceTemplate() {Register(SystemMemory, 0, 0, 0, 0)},
645 * ...
646 * ...
647 * ...
648 * }
649 * Each Register() encodes how to access that specific register.
650 * e.g. a sample PCC entry has the following encoding:
651 *
652 * Register (
653 * PCC, // AddressSpaceKeyword
654 * 8, // RegisterBitWidth
655 * 8, // RegisterBitOffset
656 * 0x30, // RegisterAddress
657 * 9, // AccessSize (subspace ID)
658 * )
659 */
660
661 #ifndef arch_init_invariance_cppc
arch_init_invariance_cppc(void)662 static inline void arch_init_invariance_cppc(void) { }
663 #endif
664
665 /**
666 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
667 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
668 *
669 * Return: 0 for success or negative value for err.
670 */
acpi_cppc_processor_probe(struct acpi_processor * pr)671 int acpi_cppc_processor_probe(struct acpi_processor *pr)
672 {
673 struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
674 union acpi_object *out_obj, *cpc_obj;
675 struct cpc_desc *cpc_ptr;
676 struct cpc_reg *gas_t;
677 struct device *cpu_dev;
678 acpi_handle handle = pr->handle;
679 unsigned int num_ent, i, cpc_rev;
680 int pcc_subspace_id = -1;
681 acpi_status status;
682 int ret = -ENODATA;
683
684 if (!osc_sb_cppc2_support_acked) {
685 pr_debug("CPPC v2 _OSC not acked\n");
686 if (!cpc_supported_by_cpu())
687 return -ENODEV;
688 }
689
690 /* Parse the ACPI _CPC table for this CPU. */
691 status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
692 ACPI_TYPE_PACKAGE);
693 if (ACPI_FAILURE(status)) {
694 ret = -ENODEV;
695 goto out_buf_free;
696 }
697
698 out_obj = (union acpi_object *) output.pointer;
699
700 cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
701 if (!cpc_ptr) {
702 ret = -ENOMEM;
703 goto out_buf_free;
704 }
705
706 /* First entry is NumEntries. */
707 cpc_obj = &out_obj->package.elements[0];
708 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
709 num_ent = cpc_obj->integer.value;
710 if (num_ent <= 1) {
711 pr_debug("Unexpected _CPC NumEntries value (%d) for CPU:%d\n",
712 num_ent, pr->id);
713 goto out_free;
714 }
715 } else {
716 pr_debug("Unexpected _CPC NumEntries entry type (%d) for CPU:%d\n",
717 cpc_obj->type, pr->id);
718 goto out_free;
719 }
720
721 /* Second entry should be revision. */
722 cpc_obj = &out_obj->package.elements[1];
723 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
724 cpc_rev = cpc_obj->integer.value;
725 } else {
726 pr_debug("Unexpected _CPC Revision entry type (%d) for CPU:%d\n",
727 cpc_obj->type, pr->id);
728 goto out_free;
729 }
730
731 if (cpc_rev < CPPC_V2_REV) {
732 pr_debug("Unsupported _CPC Revision (%d) for CPU:%d\n", cpc_rev,
733 pr->id);
734 goto out_free;
735 }
736
737 /*
738 * Disregard _CPC if the number of entries in the return pachage is not
739 * as expected, but support future revisions being proper supersets of
740 * the v3 and only causing more entries to be returned by _CPC.
741 */
742 if ((cpc_rev == CPPC_V2_REV && num_ent != CPPC_V2_NUM_ENT) ||
743 (cpc_rev == CPPC_V3_REV && num_ent != CPPC_V3_NUM_ENT) ||
744 (cpc_rev > CPPC_V3_REV && num_ent <= CPPC_V3_NUM_ENT)) {
745 pr_debug("Unexpected number of _CPC return package entries (%d) for CPU:%d\n",
746 num_ent, pr->id);
747 goto out_free;
748 }
749 if (cpc_rev > CPPC_V3_REV) {
750 num_ent = CPPC_V3_NUM_ENT;
751 cpc_rev = CPPC_V3_REV;
752 }
753
754 cpc_ptr->num_entries = num_ent;
755 cpc_ptr->version = cpc_rev;
756
757 /* Iterate through remaining entries in _CPC */
758 for (i = 2; i < num_ent; i++) {
759 cpc_obj = &out_obj->package.elements[i];
760
761 if (cpc_obj->type == ACPI_TYPE_INTEGER) {
762 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
763 cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
764 } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
765 gas_t = (struct cpc_reg *)
766 cpc_obj->buffer.pointer;
767
768 /*
769 * The PCC Subspace index is encoded inside
770 * the CPC table entries. The same PCC index
771 * will be used for all the PCC entries,
772 * so extract it only once.
773 */
774 if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
775 if (pcc_subspace_id < 0) {
776 pcc_subspace_id = gas_t->access_width;
777 if (pcc_data_alloc(pcc_subspace_id))
778 goto out_free;
779 } else if (pcc_subspace_id != gas_t->access_width) {
780 pr_debug("Mismatched PCC ids in _CPC for CPU:%d\n",
781 pr->id);
782 goto out_free;
783 }
784 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
785 if (gas_t->address) {
786 void __iomem *addr;
787 size_t access_width;
788
789 if (!osc_cpc_flexible_adr_space_confirmed) {
790 pr_debug("Flexible address space capability not supported\n");
791 if (!cpc_supported_by_cpu())
792 goto out_free;
793 }
794
795 access_width = GET_BIT_WIDTH(gas_t) / 8;
796 addr = ioremap(gas_t->address, access_width);
797 if (!addr)
798 goto out_free;
799 cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
800 }
801 } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
802 if (gas_t->access_width < 1 || gas_t->access_width > 3) {
803 /*
804 * 1 = 8-bit, 2 = 16-bit, and 3 = 32-bit.
805 * SystemIO doesn't implement 64-bit
806 * registers.
807 */
808 pr_debug("Invalid access width %d for SystemIO register in _CPC\n",
809 gas_t->access_width);
810 goto out_free;
811 }
812 if (gas_t->address & OVER_16BTS_MASK) {
813 /* SystemIO registers use 16-bit integer addresses */
814 pr_debug("Invalid IO port %llu for SystemIO register in _CPC\n",
815 gas_t->address);
816 goto out_free;
817 }
818 if (!osc_cpc_flexible_adr_space_confirmed) {
819 pr_debug("Flexible address space capability not supported\n");
820 if (!cpc_supported_by_cpu())
821 goto out_free;
822 }
823 } else {
824 if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
825 /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
826 pr_debug("Unsupported register type (%d) in _CPC\n",
827 gas_t->space_id);
828 goto out_free;
829 }
830 }
831
832 cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
833 memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
834 } else {
835 pr_debug("Invalid entry type (%d) in _CPC for CPU:%d\n",
836 i, pr->id);
837 goto out_free;
838 }
839 }
840 per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
841
842 /*
843 * Initialize the remaining cpc_regs as unsupported.
844 * Example: In case FW exposes CPPC v2, the below loop will initialize
845 * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
846 */
847 for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
848 cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
849 cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
850 }
851
852
853 /* Store CPU Logical ID */
854 cpc_ptr->cpu_id = pr->id;
855
856 /* Parse PSD data for this CPU */
857 ret = acpi_get_psd(cpc_ptr, handle);
858 if (ret)
859 goto out_free;
860
861 /* Register PCC channel once for all PCC subspace ID. */
862 if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
863 ret = register_pcc_channel(pcc_subspace_id);
864 if (ret)
865 goto out_free;
866
867 init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
868 init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
869 }
870
871 /* Everything looks okay */
872 pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
873
874 /* Add per logical CPU nodes for reading its feedback counters. */
875 cpu_dev = get_cpu_device(pr->id);
876 if (!cpu_dev) {
877 ret = -EINVAL;
878 goto out_free;
879 }
880
881 /* Plug PSD data into this CPU's CPC descriptor. */
882 per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
883
884 ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
885 "acpi_cppc");
886 if (ret) {
887 per_cpu(cpc_desc_ptr, pr->id) = NULL;
888 kobject_put(&cpc_ptr->kobj);
889 goto out_free;
890 }
891
892 arch_init_invariance_cppc();
893
894 kfree(output.pointer);
895 return 0;
896
897 out_free:
898 /* Free all the mapped sys mem areas for this CPU */
899 for (i = 2; i < cpc_ptr->num_entries; i++) {
900 void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
901
902 if (addr)
903 iounmap(addr);
904 }
905 kfree(cpc_ptr);
906
907 out_buf_free:
908 kfree(output.pointer);
909 return ret;
910 }
911 EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
912
913 /**
914 * acpi_cppc_processor_exit - Cleanup CPC structs.
915 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
916 *
917 * Return: Void
918 */
acpi_cppc_processor_exit(struct acpi_processor * pr)919 void acpi_cppc_processor_exit(struct acpi_processor *pr)
920 {
921 struct cpc_desc *cpc_ptr;
922 unsigned int i;
923 void __iomem *addr;
924 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
925
926 if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
927 if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
928 pcc_data[pcc_ss_id]->refcount--;
929 if (!pcc_data[pcc_ss_id]->refcount) {
930 pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
931 kfree(pcc_data[pcc_ss_id]);
932 pcc_data[pcc_ss_id] = NULL;
933 }
934 }
935 }
936
937 cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
938 if (!cpc_ptr)
939 return;
940
941 /* Free all the mapped sys mem areas for this CPU */
942 for (i = 2; i < cpc_ptr->num_entries; i++) {
943 addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
944 if (addr)
945 iounmap(addr);
946 }
947
948 kobject_put(&cpc_ptr->kobj);
949 kfree(cpc_ptr);
950 }
951 EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
952
953 /**
954 * cpc_read_ffh() - Read FFH register
955 * @cpunum: CPU number to read
956 * @reg: cppc register information
957 * @val: place holder for return value
958 *
959 * Read bit_width bits from a specified address and bit_offset
960 *
961 * Return: 0 for success and error code
962 */
cpc_read_ffh(int cpunum,struct cpc_reg * reg,u64 * val)963 int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
964 {
965 return -ENOTSUPP;
966 }
967
968 /**
969 * cpc_write_ffh() - Write FFH register
970 * @cpunum: CPU number to write
971 * @reg: cppc register information
972 * @val: value to write
973 *
974 * Write value of bit_width bits to a specified address and bit_offset
975 *
976 * Return: 0 for success and error code
977 */
cpc_write_ffh(int cpunum,struct cpc_reg * reg,u64 val)978 int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
979 {
980 return -ENOTSUPP;
981 }
982
983 /*
984 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
985 * as fast as possible. We have already mapped the PCC subspace during init, so
986 * we can directly write to it.
987 */
988
cpc_read(int cpu,struct cpc_register_resource * reg_res,u64 * val)989 static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
990 {
991 void __iomem *vaddr = NULL;
992 int size;
993 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
994 struct cpc_reg *reg = ®_res->cpc_entry.reg;
995
996 if (reg_res->type == ACPI_TYPE_INTEGER) {
997 *val = reg_res->cpc_entry.int_value;
998 return 0;
999 }
1000
1001 *val = 0;
1002 size = GET_BIT_WIDTH(reg);
1003
1004 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1005 u32 val_u32;
1006 acpi_status status;
1007
1008 status = acpi_os_read_port((acpi_io_address)reg->address,
1009 &val_u32, size);
1010 if (ACPI_FAILURE(status)) {
1011 pr_debug("Error: Failed to read SystemIO port %llx\n",
1012 reg->address);
1013 return -EFAULT;
1014 }
1015
1016 *val = val_u32;
1017 return 0;
1018 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1019 /*
1020 * For registers in PCC space, the register size is determined
1021 * by the bit width field; the access size is used to indicate
1022 * the PCC subspace id.
1023 */
1024 size = reg->bit_width;
1025 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1026 }
1027 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1028 vaddr = reg_res->sys_mem_vaddr;
1029 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1030 return cpc_read_ffh(cpu, reg, val);
1031 else
1032 return acpi_os_read_memory((acpi_physical_address)reg->address,
1033 val, size);
1034
1035 switch (size) {
1036 case 8:
1037 *val = readb_relaxed(vaddr);
1038 break;
1039 case 16:
1040 *val = readw_relaxed(vaddr);
1041 break;
1042 case 32:
1043 *val = readl_relaxed(vaddr);
1044 break;
1045 case 64:
1046 *val = readq_relaxed(vaddr);
1047 break;
1048 default:
1049 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1050 pr_debug("Error: Cannot read %u bit width from system memory: 0x%llx\n",
1051 size, reg->address);
1052 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1053 pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
1054 size, pcc_ss_id);
1055 }
1056 return -EFAULT;
1057 }
1058
1059 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1060 *val = MASK_VAL(reg, *val);
1061
1062 return 0;
1063 }
1064
cpc_write(int cpu,struct cpc_register_resource * reg_res,u64 val)1065 static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
1066 {
1067 int ret_val = 0;
1068 int size;
1069 void __iomem *vaddr = NULL;
1070 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1071 struct cpc_reg *reg = ®_res->cpc_entry.reg;
1072
1073 size = GET_BIT_WIDTH(reg);
1074
1075 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
1076 acpi_status status;
1077
1078 status = acpi_os_write_port((acpi_io_address)reg->address,
1079 (u32)val, size);
1080 if (ACPI_FAILURE(status)) {
1081 pr_debug("Error: Failed to write SystemIO port %llx\n",
1082 reg->address);
1083 return -EFAULT;
1084 }
1085
1086 return 0;
1087 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0) {
1088 /*
1089 * For registers in PCC space, the register size is determined
1090 * by the bit width field; the access size is used to indicate
1091 * the PCC subspace id.
1092 */
1093 size = reg->bit_width;
1094 vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
1095 }
1096 else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1097 vaddr = reg_res->sys_mem_vaddr;
1098 else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
1099 return cpc_write_ffh(cpu, reg, val);
1100 else
1101 return acpi_os_write_memory((acpi_physical_address)reg->address,
1102 val, size);
1103
1104 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
1105 val = MASK_VAL(reg, val);
1106
1107 switch (size) {
1108 case 8:
1109 writeb_relaxed(val, vaddr);
1110 break;
1111 case 16:
1112 writew_relaxed(val, vaddr);
1113 break;
1114 case 32:
1115 writel_relaxed(val, vaddr);
1116 break;
1117 case 64:
1118 writeq_relaxed(val, vaddr);
1119 break;
1120 default:
1121 if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
1122 pr_debug("Error: Cannot write %u bit width to system memory: 0x%llx\n",
1123 size, reg->address);
1124 } else if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
1125 pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1126 size, pcc_ss_id);
1127 }
1128 ret_val = -EFAULT;
1129 break;
1130 }
1131
1132 return ret_val;
1133 }
1134
cppc_get_perf(int cpunum,enum cppc_regs reg_idx,u64 * perf)1135 static int cppc_get_perf(int cpunum, enum cppc_regs reg_idx, u64 *perf)
1136 {
1137 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1138 struct cpc_register_resource *reg;
1139
1140 if (!cpc_desc) {
1141 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1142 return -ENODEV;
1143 }
1144
1145 reg = &cpc_desc->cpc_regs[reg_idx];
1146
1147 if (CPC_IN_PCC(reg)) {
1148 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1149 struct cppc_pcc_data *pcc_ss_data = NULL;
1150 int ret = 0;
1151
1152 if (pcc_ss_id < 0)
1153 return -EIO;
1154
1155 pcc_ss_data = pcc_data[pcc_ss_id];
1156
1157 down_write(&pcc_ss_data->pcc_lock);
1158
1159 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1160 cpc_read(cpunum, reg, perf);
1161 else
1162 ret = -EIO;
1163
1164 up_write(&pcc_ss_data->pcc_lock);
1165
1166 return ret;
1167 }
1168
1169 cpc_read(cpunum, reg, perf);
1170
1171 return 0;
1172 }
1173
1174 /**
1175 * cppc_get_desired_perf - Get the desired performance register value.
1176 * @cpunum: CPU from which to get desired performance.
1177 * @desired_perf: Return address.
1178 *
1179 * Return: 0 for success, -EIO otherwise.
1180 */
cppc_get_desired_perf(int cpunum,u64 * desired_perf)1181 int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1182 {
1183 return cppc_get_perf(cpunum, DESIRED_PERF, desired_perf);
1184 }
1185 EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1186
1187 /**
1188 * cppc_get_nominal_perf - Get the nominal performance register value.
1189 * @cpunum: CPU from which to get nominal performance.
1190 * @nominal_perf: Return address.
1191 *
1192 * Return: 0 for success, -EIO otherwise.
1193 */
cppc_get_nominal_perf(int cpunum,u64 * nominal_perf)1194 int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf)
1195 {
1196 return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf);
1197 }
1198
1199 /**
1200 * cppc_get_epp_perf - Get the epp register value.
1201 * @cpunum: CPU from which to get epp preference value.
1202 * @epp_perf: Return address.
1203 *
1204 * Return: 0 for success, -EIO otherwise.
1205 */
cppc_get_epp_perf(int cpunum,u64 * epp_perf)1206 int cppc_get_epp_perf(int cpunum, u64 *epp_perf)
1207 {
1208 return cppc_get_perf(cpunum, ENERGY_PERF, epp_perf);
1209 }
1210 EXPORT_SYMBOL_GPL(cppc_get_epp_perf);
1211
1212 /**
1213 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1214 * @cpunum: CPU from which to get capabilities info.
1215 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1216 *
1217 * Return: 0 for success with perf_caps populated else -ERRNO.
1218 */
cppc_get_perf_caps(int cpunum,struct cppc_perf_caps * perf_caps)1219 int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1220 {
1221 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1222 struct cpc_register_resource *highest_reg, *lowest_reg,
1223 *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1224 *low_freq_reg = NULL, *nom_freq_reg = NULL;
1225 u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1226 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1227 struct cppc_pcc_data *pcc_ss_data = NULL;
1228 int ret = 0, regs_in_pcc = 0;
1229
1230 if (!cpc_desc) {
1231 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1232 return -ENODEV;
1233 }
1234
1235 highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1236 lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1237 lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1238 nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1239 low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1240 nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1241 guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1242
1243 /* Are any of the regs PCC ?*/
1244 if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1245 CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1246 CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1247 if (pcc_ss_id < 0) {
1248 pr_debug("Invalid pcc_ss_id\n");
1249 return -ENODEV;
1250 }
1251 pcc_ss_data = pcc_data[pcc_ss_id];
1252 regs_in_pcc = 1;
1253 down_write(&pcc_ss_data->pcc_lock);
1254 /* Ring doorbell once to update PCC subspace */
1255 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1256 ret = -EIO;
1257 goto out_err;
1258 }
1259 }
1260
1261 cpc_read(cpunum, highest_reg, &high);
1262 perf_caps->highest_perf = high;
1263
1264 cpc_read(cpunum, lowest_reg, &low);
1265 perf_caps->lowest_perf = low;
1266
1267 cpc_read(cpunum, nominal_reg, &nom);
1268 perf_caps->nominal_perf = nom;
1269
1270 if (guaranteed_reg->type != ACPI_TYPE_BUFFER ||
1271 IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1272 perf_caps->guaranteed_perf = 0;
1273 } else {
1274 cpc_read(cpunum, guaranteed_reg, &guaranteed);
1275 perf_caps->guaranteed_perf = guaranteed;
1276 }
1277
1278 cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1279 perf_caps->lowest_nonlinear_perf = min_nonlinear;
1280
1281 if (!high || !low || !nom || !min_nonlinear)
1282 ret = -EFAULT;
1283
1284 /* Read optional lowest and nominal frequencies if present */
1285 if (CPC_SUPPORTED(low_freq_reg))
1286 cpc_read(cpunum, low_freq_reg, &low_f);
1287
1288 if (CPC_SUPPORTED(nom_freq_reg))
1289 cpc_read(cpunum, nom_freq_reg, &nom_f);
1290
1291 perf_caps->lowest_freq = low_f;
1292 perf_caps->nominal_freq = nom_f;
1293
1294
1295 out_err:
1296 if (regs_in_pcc)
1297 up_write(&pcc_ss_data->pcc_lock);
1298 return ret;
1299 }
1300 EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1301
1302 /**
1303 * cppc_perf_ctrs_in_pcc - Check if any perf counters are in a PCC region.
1304 *
1305 * CPPC has flexibility about how CPU performance counters are accessed.
1306 * One of the choices is PCC regions, which can have a high access latency. This
1307 * routine allows callers of cppc_get_perf_ctrs() to know this ahead of time.
1308 *
1309 * Return: true if any of the counters are in PCC regions, false otherwise
1310 */
cppc_perf_ctrs_in_pcc(void)1311 bool cppc_perf_ctrs_in_pcc(void)
1312 {
1313 int cpu;
1314
1315 for_each_present_cpu(cpu) {
1316 struct cpc_register_resource *ref_perf_reg;
1317 struct cpc_desc *cpc_desc;
1318
1319 cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1320
1321 if (CPC_IN_PCC(&cpc_desc->cpc_regs[DELIVERED_CTR]) ||
1322 CPC_IN_PCC(&cpc_desc->cpc_regs[REFERENCE_CTR]) ||
1323 CPC_IN_PCC(&cpc_desc->cpc_regs[CTR_WRAP_TIME]))
1324 return true;
1325
1326
1327 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1328
1329 /*
1330 * If reference perf register is not supported then we should
1331 * use the nominal perf value
1332 */
1333 if (!CPC_SUPPORTED(ref_perf_reg))
1334 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1335
1336 if (CPC_IN_PCC(ref_perf_reg))
1337 return true;
1338 }
1339
1340 return false;
1341 }
1342 EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc);
1343
1344 /**
1345 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1346 * @cpunum: CPU from which to read counters.
1347 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1348 *
1349 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1350 */
cppc_get_perf_ctrs(int cpunum,struct cppc_perf_fb_ctrs * perf_fb_ctrs)1351 int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1352 {
1353 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1354 struct cpc_register_resource *delivered_reg, *reference_reg,
1355 *ref_perf_reg, *ctr_wrap_reg;
1356 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1357 struct cppc_pcc_data *pcc_ss_data = NULL;
1358 u64 delivered, reference, ref_perf, ctr_wrap_time;
1359 int ret = 0, regs_in_pcc = 0;
1360
1361 if (!cpc_desc) {
1362 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1363 return -ENODEV;
1364 }
1365
1366 delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1367 reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1368 ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1369 ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1370
1371 /*
1372 * If reference perf register is not supported then we should
1373 * use the nominal perf value
1374 */
1375 if (!CPC_SUPPORTED(ref_perf_reg))
1376 ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1377
1378 /* Are any of the regs PCC ?*/
1379 if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1380 CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1381 if (pcc_ss_id < 0) {
1382 pr_debug("Invalid pcc_ss_id\n");
1383 return -ENODEV;
1384 }
1385 pcc_ss_data = pcc_data[pcc_ss_id];
1386 down_write(&pcc_ss_data->pcc_lock);
1387 regs_in_pcc = 1;
1388 /* Ring doorbell once to update PCC subspace */
1389 if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1390 ret = -EIO;
1391 goto out_err;
1392 }
1393 }
1394
1395 cpc_read(cpunum, delivered_reg, &delivered);
1396 cpc_read(cpunum, reference_reg, &reference);
1397 cpc_read(cpunum, ref_perf_reg, &ref_perf);
1398
1399 /*
1400 * Per spec, if ctr_wrap_time optional register is unsupported, then the
1401 * performance counters are assumed to never wrap during the lifetime of
1402 * platform
1403 */
1404 ctr_wrap_time = (u64)(~((u64)0));
1405 if (CPC_SUPPORTED(ctr_wrap_reg))
1406 cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1407
1408 if (!delivered || !reference || !ref_perf) {
1409 ret = -EFAULT;
1410 goto out_err;
1411 }
1412
1413 perf_fb_ctrs->delivered = delivered;
1414 perf_fb_ctrs->reference = reference;
1415 perf_fb_ctrs->reference_perf = ref_perf;
1416 perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1417 out_err:
1418 if (regs_in_pcc)
1419 up_write(&pcc_ss_data->pcc_lock);
1420 return ret;
1421 }
1422 EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1423
1424 /*
1425 * Set Energy Performance Preference Register value through
1426 * Performance Controls Interface
1427 */
cppc_set_epp_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls,bool enable)1428 int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool enable)
1429 {
1430 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1431 struct cpc_register_resource *epp_set_reg;
1432 struct cpc_register_resource *auto_sel_reg;
1433 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1434 struct cppc_pcc_data *pcc_ss_data = NULL;
1435 int ret;
1436
1437 if (!cpc_desc) {
1438 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1439 return -ENODEV;
1440 }
1441
1442 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1443 epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
1444
1445 if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) {
1446 if (pcc_ss_id < 0) {
1447 pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu);
1448 return -ENODEV;
1449 }
1450
1451 if (CPC_SUPPORTED(auto_sel_reg)) {
1452 ret = cpc_write(cpu, auto_sel_reg, enable);
1453 if (ret)
1454 return ret;
1455 }
1456
1457 if (CPC_SUPPORTED(epp_set_reg)) {
1458 ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
1459 if (ret)
1460 return ret;
1461 }
1462
1463 pcc_ss_data = pcc_data[pcc_ss_id];
1464
1465 down_write(&pcc_ss_data->pcc_lock);
1466 /* after writing CPC, transfer the ownership of PCC to platform */
1467 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1468 up_write(&pcc_ss_data->pcc_lock);
1469 } else {
1470 ret = -ENOTSUPP;
1471 pr_debug("_CPC in PCC is not supported\n");
1472 }
1473
1474 return ret;
1475 }
1476 EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
1477
1478 /**
1479 * cppc_get_auto_sel_caps - Read autonomous selection register.
1480 * @cpunum : CPU from which to read register.
1481 * @perf_caps : struct where autonomous selection register value is updated.
1482 */
cppc_get_auto_sel_caps(int cpunum,struct cppc_perf_caps * perf_caps)1483 int cppc_get_auto_sel_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1484 {
1485 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1486 struct cpc_register_resource *auto_sel_reg;
1487 u64 auto_sel;
1488
1489 if (!cpc_desc) {
1490 pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1491 return -ENODEV;
1492 }
1493
1494 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1495
1496 if (!CPC_SUPPORTED(auto_sel_reg))
1497 pr_warn_once("Autonomous mode is not unsupported!\n");
1498
1499 if (CPC_IN_PCC(auto_sel_reg)) {
1500 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1501 struct cppc_pcc_data *pcc_ss_data = NULL;
1502 int ret = 0;
1503
1504 if (pcc_ss_id < 0)
1505 return -ENODEV;
1506
1507 pcc_ss_data = pcc_data[pcc_ss_id];
1508
1509 down_write(&pcc_ss_data->pcc_lock);
1510
1511 if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
1512 cpc_read(cpunum, auto_sel_reg, &auto_sel);
1513 perf_caps->auto_sel = (bool)auto_sel;
1514 } else {
1515 ret = -EIO;
1516 }
1517
1518 up_write(&pcc_ss_data->pcc_lock);
1519
1520 return ret;
1521 }
1522
1523 return 0;
1524 }
1525 EXPORT_SYMBOL_GPL(cppc_get_auto_sel_caps);
1526
1527 /**
1528 * cppc_set_auto_sel - Write autonomous selection register.
1529 * @cpu : CPU to which to write register.
1530 * @enable : the desired value of autonomous selection resiter to be updated.
1531 */
cppc_set_auto_sel(int cpu,bool enable)1532 int cppc_set_auto_sel(int cpu, bool enable)
1533 {
1534 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1535 struct cpc_register_resource *auto_sel_reg;
1536 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1537 struct cppc_pcc_data *pcc_ss_data = NULL;
1538 int ret = -EINVAL;
1539
1540 if (!cpc_desc) {
1541 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1542 return -ENODEV;
1543 }
1544
1545 auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
1546
1547 if (CPC_IN_PCC(auto_sel_reg)) {
1548 if (pcc_ss_id < 0) {
1549 pr_debug("Invalid pcc_ss_id\n");
1550 return -ENODEV;
1551 }
1552
1553 if (CPC_SUPPORTED(auto_sel_reg)) {
1554 ret = cpc_write(cpu, auto_sel_reg, enable);
1555 if (ret)
1556 return ret;
1557 }
1558
1559 pcc_ss_data = pcc_data[pcc_ss_id];
1560
1561 down_write(&pcc_ss_data->pcc_lock);
1562 /* after writing CPC, transfer the ownership of PCC to platform */
1563 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1564 up_write(&pcc_ss_data->pcc_lock);
1565 } else {
1566 ret = -ENOTSUPP;
1567 pr_debug("_CPC in PCC is not supported\n");
1568 }
1569
1570 return ret;
1571 }
1572 EXPORT_SYMBOL_GPL(cppc_set_auto_sel);
1573
1574 /**
1575 * cppc_set_enable - Set to enable CPPC on the processor by writing the
1576 * Continuous Performance Control package EnableRegister field.
1577 * @cpu: CPU for which to enable CPPC register.
1578 * @enable: 0 - disable, 1 - enable CPPC feature on the processor.
1579 *
1580 * Return: 0 for success, -ERRNO or -EIO otherwise.
1581 */
cppc_set_enable(int cpu,bool enable)1582 int cppc_set_enable(int cpu, bool enable)
1583 {
1584 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1585 struct cpc_register_resource *enable_reg;
1586 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1587 struct cppc_pcc_data *pcc_ss_data = NULL;
1588 int ret = -EINVAL;
1589
1590 if (!cpc_desc) {
1591 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1592 return -EINVAL;
1593 }
1594
1595 enable_reg = &cpc_desc->cpc_regs[ENABLE];
1596
1597 if (CPC_IN_PCC(enable_reg)) {
1598
1599 if (pcc_ss_id < 0)
1600 return -EIO;
1601
1602 ret = cpc_write(cpu, enable_reg, enable);
1603 if (ret)
1604 return ret;
1605
1606 pcc_ss_data = pcc_data[pcc_ss_id];
1607
1608 down_write(&pcc_ss_data->pcc_lock);
1609 /* after writing CPC, transfer the ownership of PCC to platfrom */
1610 ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1611 up_write(&pcc_ss_data->pcc_lock);
1612 return ret;
1613 }
1614
1615 return cpc_write(cpu, enable_reg, enable);
1616 }
1617 EXPORT_SYMBOL_GPL(cppc_set_enable);
1618
1619 /**
1620 * cppc_set_perf - Set a CPU's performance controls.
1621 * @cpu: CPU for which to set performance controls.
1622 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1623 *
1624 * Return: 0 for success, -ERRNO otherwise.
1625 */
cppc_set_perf(int cpu,struct cppc_perf_ctrls * perf_ctrls)1626 int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1627 {
1628 struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1629 struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg;
1630 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1631 struct cppc_pcc_data *pcc_ss_data = NULL;
1632 int ret = 0;
1633
1634 if (!cpc_desc) {
1635 pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1636 return -ENODEV;
1637 }
1638
1639 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1640 min_perf_reg = &cpc_desc->cpc_regs[MIN_PERF];
1641 max_perf_reg = &cpc_desc->cpc_regs[MAX_PERF];
1642
1643 /*
1644 * This is Phase-I where we want to write to CPC registers
1645 * -> We want all CPUs to be able to execute this phase in parallel
1646 *
1647 * Since read_lock can be acquired by multiple CPUs simultaneously we
1648 * achieve that goal here
1649 */
1650 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1651 if (pcc_ss_id < 0) {
1652 pr_debug("Invalid pcc_ss_id\n");
1653 return -ENODEV;
1654 }
1655 pcc_ss_data = pcc_data[pcc_ss_id];
1656 down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1657 if (pcc_ss_data->platform_owns_pcc) {
1658 ret = check_pcc_chan(pcc_ss_id, false);
1659 if (ret) {
1660 up_read(&pcc_ss_data->pcc_lock);
1661 return ret;
1662 }
1663 }
1664 /*
1665 * Update the pending_write to make sure a PCC CMD_READ will not
1666 * arrive and steal the channel during the switch to write lock
1667 */
1668 pcc_ss_data->pending_pcc_write_cmd = true;
1669 cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1670 cpc_desc->write_cmd_status = 0;
1671 }
1672
1673 cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1674
1675 /*
1676 * Only write if min_perf and max_perf not zero. Some drivers pass zero
1677 * value to min and max perf, but they don't mean to set the zero value,
1678 * they just don't want to write to those registers.
1679 */
1680 if (perf_ctrls->min_perf)
1681 cpc_write(cpu, min_perf_reg, perf_ctrls->min_perf);
1682 if (perf_ctrls->max_perf)
1683 cpc_write(cpu, max_perf_reg, perf_ctrls->max_perf);
1684
1685 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg))
1686 up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
1687 /*
1688 * This is Phase-II where we transfer the ownership of PCC to Platform
1689 *
1690 * Short Summary: Basically if we think of a group of cppc_set_perf
1691 * requests that happened in short overlapping interval. The last CPU to
1692 * come out of Phase-I will enter Phase-II and ring the doorbell.
1693 *
1694 * We have the following requirements for Phase-II:
1695 * 1. We want to execute Phase-II only when there are no CPUs
1696 * currently executing in Phase-I
1697 * 2. Once we start Phase-II we want to avoid all other CPUs from
1698 * entering Phase-I.
1699 * 3. We want only one CPU among all those who went through Phase-I
1700 * to run phase-II
1701 *
1702 * If write_trylock fails to get the lock and doesn't transfer the
1703 * PCC ownership to the platform, then one of the following will be TRUE
1704 * 1. There is at-least one CPU in Phase-I which will later execute
1705 * write_trylock, so the CPUs in Phase-I will be responsible for
1706 * executing the Phase-II.
1707 * 2. Some other CPU has beaten this CPU to successfully execute the
1708 * write_trylock and has already acquired the write_lock. We know for a
1709 * fact it (other CPU acquiring the write_lock) couldn't have happened
1710 * before this CPU's Phase-I as we held the read_lock.
1711 * 3. Some other CPU executing pcc CMD_READ has stolen the
1712 * down_write, in which case, send_pcc_cmd will check for pending
1713 * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1714 * So this CPU can be certain that its request will be delivered
1715 * So in all cases, this CPU knows that its request will be delivered
1716 * by another CPU and can return
1717 *
1718 * After getting the down_write we still need to check for
1719 * pending_pcc_write_cmd to take care of the following scenario
1720 * The thread running this code could be scheduled out between
1721 * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1722 * could have delivered the request to Platform by triggering the
1723 * doorbell and transferred the ownership of PCC to platform. So this
1724 * avoids triggering an unnecessary doorbell and more importantly before
1725 * triggering the doorbell it makes sure that the PCC channel ownership
1726 * is still with OSPM.
1727 * pending_pcc_write_cmd can also be cleared by a different CPU, if
1728 * there was a pcc CMD_READ waiting on down_write and it steals the lock
1729 * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1730 * case during a CMD_READ and if there are pending writes it delivers
1731 * the write command before servicing the read command
1732 */
1733 if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(min_perf_reg) || CPC_IN_PCC(max_perf_reg)) {
1734 if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1735 /* Update only if there are pending write commands */
1736 if (pcc_ss_data->pending_pcc_write_cmd)
1737 send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1738 up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
1739 } else
1740 /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1741 wait_event(pcc_ss_data->pcc_write_wait_q,
1742 cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1743
1744 /* send_pcc_cmd updates the status in case of failure */
1745 ret = cpc_desc->write_cmd_status;
1746 }
1747 return ret;
1748 }
1749 EXPORT_SYMBOL_GPL(cppc_set_perf);
1750
1751 /**
1752 * cppc_get_transition_latency - returns frequency transition latency in ns
1753 * @cpu_num: CPU number for per_cpu().
1754 *
1755 * ACPI CPPC does not explicitly specify how a platform can specify the
1756 * transition latency for performance change requests. The closest we have
1757 * is the timing information from the PCCT tables which provides the info
1758 * on the number and frequency of PCC commands the platform can handle.
1759 *
1760 * If desired_reg is in the SystemMemory or SystemIo ACPI address space,
1761 * then assume there is no latency.
1762 */
cppc_get_transition_latency(int cpu_num)1763 unsigned int cppc_get_transition_latency(int cpu_num)
1764 {
1765 /*
1766 * Expected transition latency is based on the PCCT timing values
1767 * Below are definition from ACPI spec:
1768 * pcc_nominal- Expected latency to process a command, in microseconds
1769 * pcc_mpar - The maximum number of periodic requests that the subspace
1770 * channel can support, reported in commands per minute. 0
1771 * indicates no limitation.
1772 * pcc_mrtt - The minimum amount of time that OSPM must wait after the
1773 * completion of a command before issuing the next command,
1774 * in microseconds.
1775 */
1776 unsigned int latency_ns = 0;
1777 struct cpc_desc *cpc_desc;
1778 struct cpc_register_resource *desired_reg;
1779 int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1780 struct cppc_pcc_data *pcc_ss_data;
1781
1782 cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1783 if (!cpc_desc)
1784 return CPUFREQ_ETERNAL;
1785
1786 desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1787 if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg))
1788 return 0;
1789 else if (!CPC_IN_PCC(desired_reg))
1790 return CPUFREQ_ETERNAL;
1791
1792 if (pcc_ss_id < 0)
1793 return CPUFREQ_ETERNAL;
1794
1795 pcc_ss_data = pcc_data[pcc_ss_id];
1796 if (pcc_ss_data->pcc_mpar)
1797 latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1798
1799 latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1800 latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1801
1802 return latency_ns;
1803 }
1804 EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1805