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Searched refs:slice_chunk_size (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dsc/
Drc_calc_dpi.c66 to->slice_chunk_size = from->slice_chunk_size; in copy_pps_fields()
115 tmp = (unsigned long long)dsc_cfg.slice_chunk_size * 0x10000000 + (dsc_cfg.slice_width - 1); in dscc_compute_dsc_parameters()
/drivers/gpu/drm/display/
Ddrm_dsc_helper.c153 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); in drm_dsc_pps_payload_pack()
1327 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * in drm_dsc_compute_rc_parameters()
1336 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * in drm_dsc_compute_rc_parameters()
1354 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; in drm_dsc_compute_rc_parameters()
/drivers/gpu/drm/msm/
Dmsm_dsc_helper.h35 return dsc->slice_count * dsc->slice_chunk_size; in msm_dsc_get_bytes_per_line()
/drivers/gpu/drm/i915/display/
Dintel_vdsc_regs.h332 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) argument
Dintel_vdsc.c672 pps_val |= DSC_SLICE_CHUNK_SIZE(vdsc_cfg->slice_chunk_size) | in intel_dsc_pps_configure()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dsc.c303 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); in dsc_log_pps()
539 reg_vals->pps.slice_chunk_size = 0; in dsc_init_reg_values()
644 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); in dsc_write_to_registers()
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_dsc.c81 data = dsc->slice_chunk_size << 16; in dpu_hw_dsc_config()
Ddpu_hw_dsc_1_2.c166 (dsc->slice_chunk_size) & 0xffff); in dpu_hw_dsc_config_1_2()
/drivers/gpu/drm/msm/dsi/
Ddsi_host.c842 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; in dsi_update_dsc_timing()
843 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ in dsi_update_dsc_timing()
876 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing()
985 wc = msm_host->dsc->slice_chunk_size + 1; in dsi_timing_setup()