| /drivers/hte/ |
| D | hte-tegra194.c | 120 u32 slices; member
326 .slices = 3,
335 .slices = 3,
342 .slices = 11,
349 .slices = 17,
689 u32 i, slices, val = 0; in tegra_hte_probe() local
709 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); in tegra_hte_probe()
711 slices = hte_dev->prov_data->slices; in tegra_hte_probe()
713 dev_dbg(dev, "slices:%d\n", slices); in tegra_hte_probe()
714 nlines = slices << 5; in tegra_hte_probe()
[all …]
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| /drivers/phy/lantiq/ |
| D | phy-lantiq-vrx200-pcie.c | 202 static const struct reg_default slices[] = { in ltq_vrx200_pcie_phy_apply_workarounds() local
218 for (i = 0; i < ARRAY_SIZE(slices); i++) { in ltq_vrx200_pcie_phy_apply_workarounds()
220 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
221 slices[i].def, slices[i].def); in ltq_vrx200_pcie_phy_apply_workarounds()
226 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
227 slices[i].def, 0x0); in ltq_vrx200_pcie_phy_apply_workarounds()
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| /drivers/net/dsa/ |
| D | bcm_sf2_cfp.c | 29 u8 slices[UDFS_PER_SLICE]; member
44 .slices = {
69 .slices = {
93 .slices = {
149 if (memcmp(slice_layout->slices, zero_slice, in bcm_sf2_get_slice_number()
165 core_writel(priv, layout->udfs[slice_num].slices[i], in bcm_sf2_cfp_udf_set()
410 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv4_rule_set()
668 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv6_rule_set()
774 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv6_rule_set()
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| /drivers/misc/cxl/ |
| D | pci.c | 1310 CXL_READ_VSEC_NAFUS(dev, vsec, &adapter->slices); in cxl_read_vsec()
1324 adapter->user_irqs = pnv_cxl_get_irq_count(dev) - 1 - 2*adapter->slices; in cxl_read_vsec()
1382 if (!adapter->slices) { in cxl_vsec_looks_ok()
1560 for (slice = 0; slice < adapter->slices; slice++) { in cxl_stop_trace_psl8()
1759 for (slice = 0; slice < adapter->slices; slice++) { in cxl_probe()
1783 for (i = 0; i < adapter->slices; i++) { in cxl_remove()
1844 for (i = 0; i < adapter->slices; i++) { in cxl_pci_error_detected()
1938 for (i = 0; i < adapter->slices; i++) { in cxl_pci_error_detected()
1992 for (i = 0; i < adapter->slices; i++) { in cxl_pci_slot_reset()
2075 for (i = 0; i < adapter->slices; i++) { in cxl_pci_resume()
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| D | of.c | 440 for (afu = 0; afu < adapter->slices; afu++) in cxl_of_remove()
485 adapter->slices = 0; in cxl_of_probe()
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| D | guest.c | 273 for (i = 0; i < adapter->slices; i++) { in guest_reset()
282 for (i = 0; i < adapter->slices; i++) { in guest_reset()
943 adapter->slices++; in cxl_guest_init_afu()
1117 adapter->slices = 0; in cxl_guest_init_adapter()
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| D | main.c | 89 for (slice = 0; slice < adapter->slices; slice++) { in cxl_slbia_core()
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| D | flash.c | 349 for (afu = 0; afu < adapter->slices; afu++) in transfer_image()
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| D | file.c | 57 if (slice > adapter->slices) in __afu_open()
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| D | cxl.h | 697 u8 slices; member
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| /drivers/gpu/drm/i915/gt/ |
| D | intel_sseu.c | 667 u8 slices, subslices; in intel_sseu_make_rpcs() local
684 slices = hweight8(req_sseu->slice_mask); in intel_sseu_make_rpcs()
713 slices == 1 && in intel_sseu_make_rpcs()
718 slices *= 2; in intel_sseu_make_rpcs()
728 u32 mask, val = slices; in intel_sseu_make_rpcs()
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| /drivers/gpu/drm/i915/display/ |
| D | skl_watermark.c | 614 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) in intel_crtc_dbuf_weights()
650 dbuf_slice_mask = new_dbuf_state->slices[pipe]; in skl_crtc_allocate_ddb()
667 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && in skl_crtc_allocate_ddb()
690 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], in skl_crtc_allocate_ddb()
2553 enabled_slices |= dbuf_state->slices[pipe]; in intel_dbuf_enabled_slices()
2597 new_dbuf_state->slices[pipe] = in skl_compute_ddb()
2601 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe]) in skl_compute_ddb()
3008 u8 slices; in skl_wm_get_hw_state() local
3040 slices = skl_compute_dbuf_slices(crtc, dbuf_state->active_pipes, in skl_wm_get_hw_state()
3042 mbus_offset = mbus_ddb_offset(i915, slices); in skl_wm_get_hw_state()
[all …]
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| D | skl_watermark.h | 56 u8 slices[I915_MAX_PIPES]; member
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| /drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_context.c | 1137 __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected, in __check_rpcs() argument
1140 if (slices == expected) in __check_rpcs()
1143 if (slices < 0) { in __check_rpcs()
1145 name, prefix, slices, suffix); in __check_rpcs()
1146 return slices; in __check_rpcs()
1150 name, prefix, slices, expected, suffix); in __check_rpcs()
1153 rpcs, slices, in __check_rpcs()
1169 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish() local
1186 ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!"); in __sseu_finish()
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| /drivers/usb/dwc2/ |
| D | hcd_queue.c | 557 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); in dwc2_ls_pmap_schedule() local
577 DWC2_LS_SCHEDULE_FRAMES, slices, in dwc2_ls_pmap_schedule()
596 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); in dwc2_ls_pmap_unschedule() local
604 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval, in dwc2_ls_pmap_unschedule()
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| /drivers/accel/qaic/ |
| D | qaic.h | 164 struct list_head slices; member
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| D | qaic_data.c | 418 list_add_tail(&slice->slice, &bo->slices); in qaic_map_one_slice()
645 INIT_LIST_HEAD(&bo->slices); in qaic_alloc_init_bo()
891 list_for_each_entry_safe(slice, temp, &bo->slices, slice) in qaic_free_slices_bo()
1208 list_for_each_entry(slice, &bo->slices, slice) { in send_bo_list_to_device()
1876 list_for_each_entry_safe(slice, slice_temp, &bo->slices, slice) in release_dbc()
1879 INIT_LIST_HEAD(&bo->slices); in release_dbc()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_mode_vba_20.c | 1806 unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
1818 slices, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1832 slices / 2.0, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4236 mode_lib->vba.slices = 0; in dml20_ModeSupportAndSystemConfigurationFull()
4239 mode_lib->vba.slices = 0; in dml20_ModeSupportAndSystemConfigurationFull()
4241 mode_lib->vba.slices = dml_ceil( in dml20_ModeSupportAndSystemConfigurationFull()
4245 mode_lib->vba.slices = 8.0; in dml20_ModeSupportAndSystemConfigurationFull()
4247 mode_lib->vba.slices = 4.0; in dml20_ModeSupportAndSystemConfigurationFull()
4249 mode_lib->vba.slices = 2.0; in dml20_ModeSupportAndSystemConfigurationFull()
4251 mode_lib->vba.slices = 1.0; in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
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| D | display_mode_vba_20v2.c | 1842 unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
1854 slices, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1868 slices / 2.0, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4357 mode_lib->vba.slices = 0; in dml20v2_ModeSupportAndSystemConfigurationFull()
4360 mode_lib->vba.slices = 0; in dml20v2_ModeSupportAndSystemConfigurationFull()
4362 mode_lib->vba.slices = dml_ceil( in dml20v2_ModeSupportAndSystemConfigurationFull()
4366 mode_lib->vba.slices = 8.0; in dml20v2_ModeSupportAndSystemConfigurationFull()
4368 mode_lib->vba.slices = 4.0; in dml20v2_ModeSupportAndSystemConfigurationFull()
4370 mode_lib->vba.slices = 2.0; in dml20v2_ModeSupportAndSystemConfigurationFull()
4372 mode_lib->vba.slices = 1.0; in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_mode_vba_21.c | 1798 unsigned int slices = mode_lib->vba.NumberOfDSCSlices[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
1810 slices, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1824 slices / 2.0, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4451 mode_lib->vba.slices = 0; in dml21_ModeSupportAndSystemConfigurationFull()
4454 mode_lib->vba.slices = 0; in dml21_ModeSupportAndSystemConfigurationFull()
4456 mode_lib->vba.slices = dml_ceil( in dml21_ModeSupportAndSystemConfigurationFull()
4460 mode_lib->vba.slices = 8.0; in dml21_ModeSupportAndSystemConfigurationFull()
4462 mode_lib->vba.slices = 4.0; in dml21_ModeSupportAndSystemConfigurationFull()
4464 mode_lib->vba.slices = 2.0; in dml21_ModeSupportAndSystemConfigurationFull()
4466 mode_lib->vba.slices = 1.0; in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_vba.h | 715 unsigned int slices; member
|