| /drivers/gpu/drm/amd/pm/legacy-dpm/ |
| D | si_smc.c | 34 u32 smc_address, u32 limit) in si_set_smc_sram_address() argument
36 if (smc_address & 3) in si_set_smc_sram_address()
38 if ((smc_address + 3) > limit) in si_set_smc_sram_address()
41 WREG32(SMC_IND_INDEX_0, smc_address); in si_set_smc_sram_address()
245 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, in amdgpu_si_read_smc_sram_dword() argument
252 ret = si_set_smc_sram_address(adev, smc_address, limit); in amdgpu_si_read_smc_sram_dword()
260 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, in amdgpu_si_write_smc_sram_dword() argument
267 ret = si_set_smc_sram_address(adev, smc_address, limit); in amdgpu_si_write_smc_sram_dword()
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| D | kv_smc.c | 78 u32 smc_address, u32 limit) in kv_set_smc_sram_address() argument
80 if (smc_address & 3) in kv_set_smc_sram_address()
82 if ((smc_address + 3) > limit) in kv_set_smc_sram_address()
85 WREG32(mmSMC_IND_INDEX_0, smc_address); in kv_set_smc_sram_address()
92 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, in amdgpu_kv_read_smc_sram_dword() argument
97 ret = kv_set_smc_sram_address(adev, smc_address, limit); in amdgpu_kv_read_smc_sram_dword()
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| D | sislands_smc.h | 404 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
406 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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| D | kv_dpm.h | 221 int amdgpu_kv_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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| /drivers/gpu/drm/radeon/ |
| D | ci_smc.c | 34 u32 smc_address, u32 limit) in ci_set_smc_sram_address() argument
36 if (smc_address & 3) in ci_set_smc_sram_address()
38 if ((smc_address + 3) > limit) in ci_set_smc_sram_address()
41 WREG32(SMC_IND_INDEX_0, smc_address); in ci_set_smc_sram_address()
247 u32 smc_address, u32 *value, u32 limit) in ci_read_smc_sram_dword() argument
253 ret = ci_set_smc_sram_address(rdev, smc_address, limit); in ci_read_smc_sram_dword()
262 u32 smc_address, u32 value, u32 limit) in ci_write_smc_sram_dword() argument
268 ret = ci_set_smc_sram_address(rdev, smc_address, limit); in ci_write_smc_sram_dword()
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| D | si_smc.c | 34 u32 smc_address, u32 limit) in si_set_smc_sram_address() argument
36 if (smc_address & 3) in si_set_smc_sram_address()
38 if ((smc_address + 3) > limit) in si_set_smc_sram_address()
41 WREG32(SMC_IND_INDEX_0, smc_address); in si_set_smc_sram_address()
282 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, in si_read_smc_sram_dword() argument
289 ret = si_set_smc_sram_address(rdev, smc_address, limit); in si_read_smc_sram_dword()
297 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, in si_write_smc_sram_dword() argument
304 ret = si_set_smc_sram_address(rdev, smc_address, limit); in si_write_smc_sram_dword()
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| D | kv_smc.c | 75 u32 smc_address, u32 limit) in kv_set_smc_sram_address() argument
77 if (smc_address & 3) in kv_set_smc_sram_address()
79 if ((smc_address + 3) > limit) in kv_set_smc_sram_address()
82 WREG32(SMC_IND_INDEX_0, smc_address); in kv_set_smc_sram_address()
88 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, in kv_read_smc_sram_dword() argument
93 ret = kv_set_smc_sram_address(rdev, smc_address, limit); in kv_read_smc_sram_dword()
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| D | rv770_smc.c | 266 u16 smc_address, u16 limit) in rv770_set_smc_sram_address() argument
270 if (smc_address & 3) in rv770_set_smc_sram_address()
272 if ((smc_address + 3) > limit) in rv770_set_smc_sram_address()
275 addr = smc_address; in rv770_set_smc_sram_address()
592 u16 smc_address, u32 *value, u16 limit) in rv770_read_smc_sram_dword() argument
598 ret = rv770_set_smc_sram_address(rdev, smc_address, limit); in rv770_read_smc_sram_dword()
607 u16 smc_address, u32 value, u16 limit) in rv770_write_smc_sram_dword() argument
613 ret = rv770_set_smc_sram_address(rdev, smc_address, limit); in rv770_write_smc_sram_dword()
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| D | rv770_smc.h | 201 u16 smc_address, u32 *value, u16 limit);
203 u16 smc_address, u32 value, u16 limit);
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| D | ci_dpm.h | 337 u32 smc_address, u32 *value, u32 limit);
339 u32 smc_address, u32 value, u32 limit);
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| D | sislands_smc.h | 409 int si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
411 int si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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| D | kv_dpm.h | 192 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
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| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | smu8_smumgr.c | 110 uint32_t smc_address, uint32_t limit) in smu8_set_smc_sram_address() argument
115 if (0 != (3 & smc_address)) { in smu8_set_smc_sram_address()
120 if (limit <= (smc_address + 3)) { in smu8_set_smc_sram_address()
126 SMN_MP1_SRAM_START_ADDR + smc_address); in smu8_set_smc_sram_address()
132 uint32_t smc_address, uint32_t value, uint32_t limit) in smu8_write_smc_sram_dword() argument
139 result = smu8_set_smc_sram_address(hwmgr, smc_address, limit); in smu8_write_smc_sram_dword()
665 uint32_t smc_address; in smu8_request_smu_load_fw() local
675 smc_address = SMU8_FIRMWARE_HEADER_LOCATION + in smu8_request_smu_load_fw()
678 smu8_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4); in smu8_request_smu_load_fw()
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