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/drivers/crypto/cavium/zip/
Dzip_regs.h129 u64 u_reg64;
132 u64 reserved_49_63 : 15;
133 u64 addr : 49;
135 u64 addr : 49;
136 u64 reserved_49_63 : 15;
148 u64 u_reg64;
151 u64 reserved_112_127 : 16;
152 u64 length : 16;
153 u64 reserved_67_95 : 29;
154 u64 fw : 1;
[all …]
/drivers/crypto/cavium/nitrox/
Dnitrox_csr.h211 u64 value;
214 u64 raz_4_63 : 60;
215 u64 ucode_len : 1;
216 u64 ucode_blk : 3;
218 u64 ucode_blk : 3;
219 u64 ucode_len : 1;
220 u64 raz_4_63 : 60;
230 u64 value;
233 u64 raz_40_63 : 24;
234 u64 exec_0_to_39 : 40;
[all …]
Dnitrox_req.h41 u64 value;
43 u64 raz : 22;
44 u64 arg : 8;
45 u64 ctxc : 2;
46 u64 unca : 1;
47 u64 info : 3;
48 u64 unc : 8;
49 u64 ctxl : 12;
50 u64 uddl : 8;
72 u64 ctx_handle;
[all …]
/drivers/net/ethernet/marvell/octeontx2/af/
Drvu_struct.h158 u64 op : 4; /* W0 */
159 u64 ctype : 4;
160 u64 lf : 9;
161 u64 reserved_17_23 : 7;
162 u64 cindex : 20;
163 u64 reserved_44_62 : 19;
164 u64 doneint : 1;
165 u64 res_addr; /* W1 */
170 u64 op : 4; /* W0 */
171 u64 ctype : 4;
[all …]
Dnpc.h286 u64 rsvd_63_56 : 8;
287 u64 state : 8;
288 u64 dp2_data : 16;
289 u64 dp1_data : 16;
290 u64 dp0_data : 16;
292 u64 dp0_data : 16;
293 u64 dp1_data : 16;
294 u64 dp2_data : 16;
295 u64 state : 8;
296 u64 rsvd_63_56 : 8;
[all …]
/drivers/net/ethernet/cavium/thunder/
Dq_struct.h173 u64 cqe_type:4; /* W0 */
174 u64 stdn_fault:1;
175 u64 rsvd0:1;
176 u64 rq_qs:7;
177 u64 rq_idx:3;
178 u64 rsvd1:12;
179 u64 rss_alg:4;
180 u64 rsvd2:4;
181 u64 rb_cnt:4;
182 u64 vlan_found:1;
[all …]
/drivers/net/ethernet/cavium/liquidio/
Dliquidio_common.h137 u64 corefreq;
143 u64 board_rev_major;
145 u64 board_rev_minor;
158 u64 size64;
162 u64 ptr[4];
307 u64 u64; member
311 u64 cmd:5;
313 u64 more:6; /* How many udd words follow the command */
315 u64 cmdgroup:8;
316 u64 reserved:21;
[all …]
/drivers/crypto/cavium/cpt/
Dcpt_hw_types.h74 u64 u[8];
77 u64 reserved_17_63:47;
78 u64 doneint:1;
79 u64 reserved_0_1:16;
81 u64 reserved_0_15:16;
82 u64 doneint:1;
83 u64 reserved_17_63:47;
85 u64 res_addr;
87 u64 reserved_172_19:20;
88 u64 grp:10;
[all …]
Dcpt_common.h39 #define CPTX_PF_CONSTANTS(a) (0x0ll + ((u64)(a) << 36))
40 #define CPTX_PF_RESET(a) (0x100ll + ((u64)(a) << 36))
41 #define CPTX_PF_DIAG(a) (0x120ll + ((u64)(a) << 36))
42 #define CPTX_PF_BIST_STATUS(a) (0x160ll + ((u64)(a) << 36))
43 #define CPTX_PF_ECC0_CTL(a) (0x200ll + ((u64)(a) << 36))
44 #define CPTX_PF_ECC0_FLIP(a) (0x210ll + ((u64)(a) << 36))
45 #define CPTX_PF_ECC0_INT(a) (0x220ll + ((u64)(a) << 36))
46 #define CPTX_PF_ECC0_INT_W1S(a) (0x230ll + ((u64)(a) << 36))
47 #define CPTX_PF_ECC0_ENA_W1S(a) (0x240ll + ((u64)(a) << 36))
48 #define CPTX_PF_ECC0_ENA_W1C(a) (0x250ll + ((u64)(a) << 36))
[all …]
/drivers/crypto/marvell/octeontx/
Dotx_cpt_hw_types.h63 #define OTX_CPT_PF_MBOX_INTX(b) (0x400ll | (u64)(b) << 3)
64 #define OTX_CPT_PF_MBOX_INT_W1SX(b) (0x420ll | (u64)(b) << 3)
65 #define OTX_CPT_PF_MBOX_ENA_W1CX(b) (0x440ll | (u64)(b) << 3)
66 #define OTX_CPT_PF_MBOX_ENA_W1SX(b) (0x460ll | (u64)(b) << 3)
71 #define OTX_CPT_PF_GX_EN(b) (0x600ll | (u64)(b) << 3)
91 #define OTX_CPT_PF_EXE_DBG_CNTX(b) (0x4001100ll | (u64)(b) << 3)
93 #define OTX_CPT_PF_EXE_EPCI_INBX_CNT(b) (0x4001200ll | (u64)(b) << 3)
94 #define OTX_CPT_PF_EXE_EPCI_OUTBX_CNT(b) (0x4001240ll | (u64)(b) << 3)
95 #define OTX_CPT_PF_ENGX_UCODE_BASE(b) (0x4002000ll | (u64)(b) << 3)
96 #define OTX_CPT_PF_QX_CTL(b) (0x8000000ll | (u64)(b) << 20)
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/
Den_stats.h37 (*(u64 *)((char *)ptr + dsc[i].offset))
75 int (*fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx);
93 int MLX5E_STATS_GRP_OP(grp, fill_stats)(struct mlx5e_priv *priv, u64 *data, int idx)
111 void mlx5e_stats_fill(struct mlx5e_priv *priv, u64 *data, int idx);
135 u64 rx_packets;
136 u64 rx_bytes;
137 u64 tx_packets;
138 u64 tx_bytes;
139 u64 tx_tso_packets;
140 u64 tx_tso_bytes;
[all …]
/drivers/net/ethernet/marvell/octeontx2/nic/
Dotx2_struct.h82 u64 flow_tag : 32;
83 u64 q : 20;
84 u64 reserved_52_57 : 6;
85 u64 node : 2;
86 u64 cqe_type : 4;
91 u64 chan : 12;
92 u64 desc_sizem1 : 5;
93 u64 rsvd_17 : 1;
94 u64 express : 1;
95 u64 wqwd : 1;
[all …]
/drivers/net/ethernet/ibm/ehea/
Dehea_phyp.h49 static inline void hcp_epas_ctor(struct h_epas *epas, u64 paddr_kernel, in hcp_epas_ctor()
50 u64 paddr_user) in hcp_epas_ctor()
61 iounmap((void __iomem *)((u64)epas->kernel.addr & PAGE_MASK)); in hcp_epas_dtor()
68 u64 qp_ctl_reg; /* 00 */
73 u64 qp_aer; /* 06 */
74 u64 qp_tenure; /* 08 */
99 u64 sq_cq_handle; /* 02 */
100 u64 rq_cq_handle; /* 04 */
140 u64 max_mr_size; /* 20 */
141 u64 reserved2; /* 22 */
[all …]
Dehea_hw.h26 u64 qpx_hcr;
27 u64 qpx_c;
28 u64 qpx_herr;
29 u64 qpx_aer;
30 u64 qpx_sqa;
31 u64 qpx_sqc;
32 u64 qpx_rq1a;
33 u64 qpx_rq1c;
34 u64 qpx_st;
35 u64 qpx_aerr;
[all …]
/drivers/net/dsa/sja1105/
Dsja1105_static_config.h174 u64 winstindex;
175 u64 winend;
176 u64 winst;
177 u64 destports;
178 u64 setvalid;
179 u64 txen;
180 u64 resmedia_en;
181 u64 resmedia;
182 u64 vlindex;
183 u64 delta;
[all …]
/drivers/dma/idxd/
Dregisters.h25 u64 block_on_fault:1;
26 u64 overlap_copy:1;
27 u64 cache_control_mem:1;
28 u64 cache_control_cache:1;
29 u64 cmd_cap:1;
30 u64 rsvd:3;
31 u64 dest_readback:1;
32 u64 drain_readback:1;
33 u64 rsvd2:3;
34 u64 evl_support:2;
[all …]
/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_hw_types.h214 u64 u[8];
218 u64 nixtxl:3;
219 u64 doneint:1;
220 u64 nixtx_addr:60;
222 u64 res_addr;
224 u64 tag:32;
225 u64 tt:2;
226 u64 grp:10;
227 u64 reserved_172_175:4;
228 u64 rvu_pf_func:16;
[all …]
/drivers/net/ethernet/brocade/bna/
Dbfa_defs_cna.h18 u64 secs_reset; /*!< Seconds since stats is reset */
19 u64 tx_frames; /*!< Tx frames */
20 u64 tx_words; /*!< Tx words */
21 u64 tx_lip; /*!< Tx LIP */
22 u64 tx_nos; /*!< Tx NOS */
23 u64 tx_ols; /*!< Tx OLS */
24 u64 tx_lr; /*!< Tx LR */
25 u64 tx_lrr; /*!< Tx LRR */
26 u64 rx_frames; /*!< Rx frames */
27 u64 rx_words; /*!< Rx words */
[all …]
/drivers/misc/cxl/
Dhcalls.h18 u64 phys_addr;
19 u64 len;
55 long cxl_h_attach_process(u64 unit_address, struct cxl_process_element_hcall *element,
56 u64 *process_token, u64 *mmio_addr, u64 *mmio_size);
62 long cxl_h_detach_process(u64 unit_address, u64 process_token);
67 long cxl_h_reset_afu(u64 unit_address);
74 long cxl_h_suspend_process(u64 unit_address, u64 process_token);
81 long cxl_h_resume_process(u64 unit_address, u64 process_token);
88 long cxl_h_read_error_state(u64 unit_address, u64 *state);
97 long cxl_h_get_afu_err(u64 unit_address, u64 offset, u64 buf_address, u64 len);
[all …]
/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_mac.h132 u64 stat_pkts64; /* r-10G tr-DT 64 byte frame counter */
133 u64 stat_pkts65to127; /* r-10G 65 to 127 byte frame counter */
134 u64 stat_pkts128to255; /* r-10G 128 to 255 byte frame counter */
135 u64 stat_pkts256to511; /*r-10G 256 to 511 byte frame counter */
136 u64 stat_pkts512to1023;/* r-10G 512 to 1023 byte frame counter */
137 u64 stat_pkts1024to1518; /* r-10G 1024 to 1518 byte frame counter */
138 u64 stat_pkts1519to1522; /* r-10G 1519 to 1522 byte good frame count*/
141 u64 stat_fragments;
143 u64 stat_jabbers;
146 u64 stat_drop_events;
[all …]
/drivers/net/ethernet/neterion/
Ds2io-regs.h22 u64 general_int_status;
40 u64 general_int_mask;
44 u64 sw_reset;
56 u64 adapter_status;
73 u64 adapter_control;
81 u64 serr_source;
95 u64 pci_mode;
112 u64 pic_int_status;
113 u64 pic_int_mask;
121 u64 txpic_int_reg;
[all …]
/drivers/thermal/intel/int340x_thermal/
Dacpi_thermal_rel.h31 u64 weight;
32 u64 ac0_max;
33 u64 ac1_max;
34 u64 ac2_max;
35 u64 ac3_max;
36 u64 ac4_max;
37 u64 ac5_max;
38 u64 ac6_max;
39 u64 ac7_max;
40 u64 ac8_max;
[all …]
/drivers/net/ethernet/intel/igc/
Digc_hw.h206 u64 crcerrs;
207 u64 algnerrc;
208 u64 symerrs;
209 u64 rxerrc;
210 u64 mpc;
211 u64 scc;
212 u64 ecol;
213 u64 mcc;
214 u64 latecol;
215 u64 colc;
[all …]
/drivers/net/ethernet/aquantia/atlantic/
Daq_macsec.h29 u64 ctl_pkts;
30 u64 tagged_miss_pkts;
31 u64 untagged_miss_pkts;
32 u64 notag_pkts;
33 u64 untagged_pkts;
34 u64 bad_tag_pkts;
35 u64 no_sci_pkts;
36 u64 unknown_sci_pkts;
37 u64 ctrl_prt_pass_pkts;
38 u64 unctrl_prt_pass_pkts;
[all …]
/drivers/net/ethernet/cisco/enic/
Dvnic_stats.h12 u64 tx_frames_ok;
13 u64 tx_unicast_frames_ok;
14 u64 tx_multicast_frames_ok;
15 u64 tx_broadcast_frames_ok;
16 u64 tx_bytes_ok;
17 u64 tx_unicast_bytes_ok;
18 u64 tx_multicast_bytes_ok;
19 u64 tx_broadcast_bytes_ok;
20 u64 tx_drops;
21 u64 tx_errors;
[all …]

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