| /drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| D | dcn_calc_auto.c | 40 void scaler_settings_calculation(struct dcn_bw_internal_vars *v) in scaler_settings_calculation() argument
43 for (k = 0; k <= v->number_of_active_planes - 1; k++) { in scaler_settings_calculation()
44 if (v->allow_different_hratio_vratio == dcn_bw_yes) { in scaler_settings_calculation()
45 if (v->source_scan[k] == dcn_bw_hor) { in scaler_settings_calculation()
46 v->h_ratio[k] = v->viewport_width[k] / v->scaler_rec_out_width[k]; in scaler_settings_calculation()
47 v->v_ratio[k] = v->viewport_height[k] / v->scaler_recout_height[k]; in scaler_settings_calculation()
50 v->h_ratio[k] = v->viewport_height[k] / v->scaler_rec_out_width[k]; in scaler_settings_calculation()
51 v->v_ratio[k] = v->viewport_width[k] / v->scaler_recout_height[k]; in scaler_settings_calculation()
55 if (v->source_scan[k] == dcn_bw_hor) { in scaler_settings_calculation()
56 …v->h_ratio[k] =dcn_bw_max2(v->viewport_width[k] / v->scaler_rec_out_width[k], v->viewport_height[k… in scaler_settings_calculation()
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| D | dcn_calcs.c | 401 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
454 const struct dcn_bw_internal_vars *v, in dcn_bw_calc_rq_dlg_ttu() argument
478 total_active_bw += v->read_bandwidth[i]; in dcn_bw_calc_rq_dlg_ttu()
479 total_prefetch_bw += v->prefetch_bandwidth[i]; in dcn_bw_calc_rq_dlg_ttu()
480 total_flip_bytes += v->total_immediate_flip_bytes[i]; in dcn_bw_calc_rq_dlg_ttu()
482 dlg_sys_param->total_flip_bw = v->return_bw - dcn_bw_max2(total_active_bw, total_prefetch_bw); in dcn_bw_calc_rq_dlg_ttu()
486 dlg_sys_param->t_mclk_wm_us = v->dram_clock_change_watermark; in dcn_bw_calc_rq_dlg_ttu()
487 dlg_sys_param->t_sr_wm_us = v->stutter_enter_plus_exit_watermark; in dcn_bw_calc_rq_dlg_ttu()
488 dlg_sys_param->t_urg_wm_us = v->urgent_watermark; in dcn_bw_calc_rq_dlg_ttu()
489 dlg_sys_param->t_extra_us = v->urgent_extra_latency; in dcn_bw_calc_rq_dlg_ttu()
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| /drivers/media/platform/nxp/ |
| D | imx-pxp.h | 19 #define BF_PXP_CTRL_SFTRST(v) \ argument
20 (((v) << 31) & BM_PXP_CTRL_SFTRST)
22 #define BF_PXP_CTRL_CLKGATE(v) \ argument
23 (((v) << 30) & BM_PXP_CTRL_CLKGATE)
25 #define BF_PXP_CTRL_RSVD4(v) \ argument
26 (((v) << 29) & BM_PXP_CTRL_RSVD4)
28 #define BF_PXP_CTRL_EN_REPEAT(v) \ argument
29 (((v) << 28) & BM_PXP_CTRL_EN_REPEAT)
31 #define BF_PXP_CTRL_ENABLE_ROTATE1(v) \ argument
32 (((v) << 27) & BM_PXP_CTRL_ENABLE_ROTATE1)
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_mode_vba_30.c | 397 struct vba_vars_st *v,
1855 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
1858 unsigned int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1865 v->WritebackDISPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1866 v->DISPCLKWithRamping = 0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1867 v->DISPCLKWithoutRamping = 0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1868 v->GlobalDPPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1870 v->IdealSDPPortBandwidthPerState[v->VoltageLevel][v->maxMpcComb] = dml_min3( in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1871 v->ReturnBusWidth * v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1872 v->DRAMSpeedPerState[v->VoltageLevel] * v->NumberOfChannels * v->DRAMChannelWidth, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | display_mode_vba_31.c | 1746 struct vba_vars_st *v = &mode_lib->vba; local
1754 if (!v->IgnoreViewportPositioning) {
1782 dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning);
1828 struct vba_vars_st *v = &mode_lib->vba; local
1863 MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1);
1884 if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {
1898 ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2);
2000 struct vba_vars_st *v = &mode_lib->vba; local
2007 int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
2009 v->WritebackDISPCLK = 0.0;
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| D | display_mode_vba_314.c | 1766 struct vba_vars_st *v = &mode_lib->vba; local
1774 if (!v->IgnoreViewportPositioning) {
1802 dml_print("DML::%s: IgnoreViewportPositioning = %d\n", __func__, v->IgnoreViewportPositioning);
1848 struct vba_vars_st *v = &mode_lib->vba; local
1883 MPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 1);
1904 if (GPUVMEnable == true && v->GPUVMMaxPageTableLevels > 1) {
1918 ExtraDPDEBytesFrame = 128 * (v->GPUVMMaxPageTableLevels - 2);
2020 struct vba_vars_st *v = &mode_lib->vba; local
2027 int PrefetchMode = v->PrefetchModePerState[v->VoltageLevel][v->maxMpcComb];
2029 v->WritebackDISPCLK = 0.0;
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| /drivers/media/platform/verisilicon/ |
| D | rockchip_vpu2_hw_h264_dec.c | 28 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
30 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
31 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
32 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
33 #define VDPU_REG_PIC_FIXED_QUANT(v) ((v) ? BIT(7) : 0) argument
34 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
36 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
37 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
39 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
40 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
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| D | rockchip_vpu2_hw_mpeg2_dec.c | 23 #define VDPU_REG_DEC_E(v) ((v) ? BIT(0) : 0) argument
25 #define VDPU_REG_DEC_ADV_PRE_DIS(v) ((v) ? BIT(11) : 0) argument
26 #define VDPU_REG_DEC_SCMD_DIS(v) ((v) ? BIT(10) : 0) argument
27 #define VDPU_REG_FILTERING_DIS(v) ((v) ? BIT(8) : 0) argument
28 #define VDPU_REG_DEC_LATENCY(v) (((v) << 1) & GENMASK(6, 1)) argument
30 #define VDPU_REG_INIT_QP(v) (((v) << 25) & GENMASK(30, 25)) argument
31 #define VDPU_REG_STREAM_LEN(v) (((v) << 0) & GENMASK(23, 0)) argument
33 #define VDPU_REG_APF_THRESHOLD(v) (((v) << 17) & GENMASK(30, 17)) argument
34 #define VDPU_REG_STARTMB_X(v) (((v) << 8) & GENMASK(16, 8)) argument
35 #define VDPU_REG_STARTMB_Y(v) (((v) << 0) & GENMASK(7, 0)) argument
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| D | hantro_g1_mpeg2_dec.c | 25 #define G1_REG_DEC_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
26 #define G1_REG_DEC_TIMEOUT_E(v) ((v) ? BIT(23) : 0) argument
27 #define G1_REG_DEC_STRSWAP32_E(v) ((v) ? BIT(22) : 0) argument
28 #define G1_REG_DEC_STRENDIAN_E(v) ((v) ? BIT(21) : 0) argument
29 #define G1_REG_DEC_INSWAP32_E(v) ((v) ? BIT(20) : 0) argument
30 #define G1_REG_DEC_OUTSWAP32_E(v) ((v) ? BIT(19) : 0) argument
31 #define G1_REG_DEC_DATA_DISC_E(v) ((v) ? BIT(18) : 0) argument
32 #define G1_REG_DEC_LATENCY(v) (((v) << 11) & GENMASK(16, 11)) argument
33 #define G1_REG_DEC_CLK_GATE_E(v) ((v) ? BIT(10) : 0) argument
34 #define G1_REG_DEC_IN_ENDIAN(v) ((v) ? BIT(9) : 0) argument
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| /drivers/staging/media/sunxi/sun6i-isp/ |
| D | sun6i_isp_reg.h | 21 #define SUN6I_ISP_FE_CFG_SRC0_MODE(v) (((v) << 8) & GENMASK(9, 8)) argument
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16)) argument
33 #define SUN6I_ISP_FE_CTRL_OUTPUT_SPEED_CTRL(v) (((v) << 16) & GENMASK(17, 16)) argument
104 #define SUN6I_ISP_MODE_INPUT_FMT(v) ((v) & GENMASK(2, 0)) argument
105 #define SUN6I_ISP_MODE_INPUT_YUV_SEQ(v) (((v) << 3) & GENMASK(4, 3)) argument
106 #define SUN6I_ISP_MODE_OTF_DPC(v) (((v) << 16) & BIT(16)) argument
107 #define SUN6I_ISP_MODE_SHARP(v) (((v) << 17) & BIT(17)) argument
108 #define SUN6I_ISP_MODE_HIST(v) (((v) << 20) & GENMASK(21, 20)) argument
123 #define SUN6I_ISP_IN_CFG_STRIDE_DIV16(v) ((v) & GENMASK(10, 0)) argument
133 #define SUN6I_ISP_AE_CFG_LOW_BRI_TH(v) ((v) & GENMASK(11, 0)) argument
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| /drivers/iio/adc/ |
| D | stm32-dfsdm.h | 52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) argument
54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) argument
56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) argument
58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) argument
60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) argument
62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) argument
64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) argument
66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) argument
68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) argument
70 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v) argument
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| /drivers/gpu/host1x/hw/ |
| D | hw_host1x01_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x05_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x08_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x02_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x04_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 8; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0xff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x07_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| D | hw_host1x06_uclass.h | 48 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) in host1x_uclass_incr_syncpt_cond_f() argument
50 return (v & 0xff) << 10; in host1x_uclass_incr_syncpt_cond_f()
52 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ argument
53 host1x_uclass_incr_syncpt_cond_f(v)
54 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) in host1x_uclass_incr_syncpt_indx_f() argument
56 return (v & 0x3ff) << 0; in host1x_uclass_incr_syncpt_indx_f()
58 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ argument
59 host1x_uclass_incr_syncpt_indx_f(v)
66 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) in host1x_uclass_wait_syncpt_indx_f() argument
68 return (v & 0xff) << 24; in host1x_uclass_wait_syncpt_indx_f()
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| /drivers/md/ |
| D | dm-verity-target.c | 56 struct dm_verity *v; member
91 static sector_t verity_map_sector(struct dm_verity *v, sector_t bi_sector) in verity_map_sector() argument
93 return v->data_start + dm_target_offset(v->ti, bi_sector); in verity_map_sector()
102 static sector_t verity_position_at_level(struct dm_verity *v, sector_t block, in verity_position_at_level() argument
105 return block >> (level * v->hash_per_block_bits); in verity_position_at_level()
108 static int verity_ahash_update(struct dm_verity *v, struct ahash_request *req, in verity_ahash_update() argument
141 static int verity_ahash_init(struct dm_verity *v, struct ahash_request *req, in verity_ahash_init() argument
146 ahash_request_set_tfm(req, v->ahash_tfm); in verity_ahash_init()
160 if (likely(v->salt_size && (v->version >= 1))) in verity_ahash_init()
161 r = verity_ahash_update(v, req, v->salt, v->salt_size, wait); in verity_ahash_init()
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| D | dm-verity-fec.c | 16 bool verity_fec_is_enabled(struct dm_verity *v) in verity_fec_is_enabled() argument
18 return v->fec && v->fec->dev; in verity_fec_is_enabled()
28 ((char *)io + io->v->ti->per_io_data_size - sizeof(struct dm_verity_fec_io)); in fec_io()
34 static inline u64 fec_interleave(struct dm_verity *v, u64 offset) in fec_interleave() argument
38 mod = do_div(offset, v->fec->rsn); in fec_interleave()
39 return offset + mod * (v->fec->rounds << v->data_dev_block_bits); in fec_interleave()
45 static int fec_decode_rs8(struct dm_verity *v, struct dm_verity_fec_io *fio, in fec_decode_rs8() argument
51 for (i = 0; i < v->fec->roots; i++) in fec_decode_rs8()
54 return decode_rs8(fio->rs, data, par, v->fec->rsn, NULL, neras, in fec_decode_rs8()
62 static u8 *fec_read_parity(struct dm_verity *v, u64 rsb, int index, in fec_read_parity() argument
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| /drivers/gpu/drm/exynos/ |
| D | regs-scaler.h | 206 #define SCALER_SRC_CFG_SET_BYTE_SWAP(v) SCALER_SET(v, 6, 5) argument
208 #define SCALER_SRC_CFG_SET_COLOR_FORMAT(v) SCALER_SET(v, 4, 0) argument
232 #define SCALER_SRC_SPAN_SET_C_SPAN(v) SCALER_SET(v, 29, 16) argument
234 #define SCALER_SRC_SPAN_SET_Y_SPAN(v) SCALER_SET(v, 13, 0) argument
238 #define SCALER_SRC_Y_POS_SET_YH_POS(v) SCALER_SET(v, 31, 16) argument
240 #define SCALER_SRC_Y_POS_SET_YV_POS(v) SCALER_SET(v, 15, 0) argument
244 #define SCALER_SRC_WH_SET_WIDTH(v) SCALER_SET(v, 29, 16) argument
246 #define SCALER_SRC_WH_SET_HEIGHT(v) SCALER_SET(v, 13, 0) argument
250 #define SCALER_SRC_C_POS_SET_CH_POS(v) SCALER_SET(v, 31, 16) argument
252 #define SCALER_SRC_C_POS_SET_CV_POS(v) SCALER_SET(v, 15, 0) argument
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| /drivers/staging/media/sunxi/cedrus/ |
| D | cedrus_regs.h | 13 #define SHIFT_AND_MASK_BITS(v, h, l) \ argument
14 (((unsigned long)(v) << (l)) & GENMASK(h, l))
104 #define VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(v) \ argument
105 ((v) ? BIT(7) : 0)
106 #define VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT(v) \ argument
107 ((v) ? BIT(6) : 0)
108 #define VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS(v) \ argument
109 ((v) ? BIT(5) : 0)
110 #define VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE(v) \ argument
111 ((v) ? BIT(4) : 0)
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| /drivers/vhost/ |
| D | vdpa.c | 68 static void vhost_vdpa_iotlb_unmap(struct vhost_vdpa *v,
79 static struct vhost_vdpa_as *asid_to_as(struct vhost_vdpa *v, u32 asid) in asid_to_as() argument
81 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in asid_to_as()
91 static struct vhost_iotlb *asid_to_iotlb(struct vhost_vdpa *v, u32 asid) in asid_to_iotlb() argument
93 struct vhost_vdpa_as *as = asid_to_as(v, asid); in asid_to_iotlb()
101 static struct vhost_vdpa_as *vhost_vdpa_alloc_as(struct vhost_vdpa *v, u32 asid) in vhost_vdpa_alloc_as() argument
103 struct hlist_head *head = &v->as[asid % VHOST_VDPA_IOTLB_BUCKETS]; in vhost_vdpa_alloc_as()
106 if (asid_to_as(v, asid)) in vhost_vdpa_alloc_as()
109 if (asid >= v->vdpa->nas) in vhost_vdpa_alloc_as()
123 static struct vhost_vdpa_as *vhost_vdpa_find_alloc_as(struct vhost_vdpa *v, in vhost_vdpa_find_alloc_as() argument
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| /drivers/iommu/ |
| D | msm_iommu_hw-8xxx.h | 20 #define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v)) argument
28 #define SET_GLOBAL_FIELD(b, r, F, v) \ argument
29 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
30 #define SET_CONTEXT_FIELD(b, c, r, F, v) \ argument
31 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
35 #define SET_FIELD(addr, mask, shift, v) \ argument
38 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
84 #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) argument
85 #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) argument
86 #define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v)) argument
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | display_mode_vba_32.c | 61 struct vba_vars_st *v = &mode_lib->vba; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation() local
81 v->WritebackDISPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
82 v->GlobalDPPCLK = 0.0; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
87 v->WritebackDISPCLK = dml_max(v->WritebackDISPCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
101 v->DISPCLK_calculated = v->WritebackDISPCLK; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
105 v->DISPCLK_calculated = dml_max(v->DISPCLK_calculated, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
131 &v->PSCL_THROUGHPUT_LUMA[k], &v->PSCL_THROUGHPUT_CHROMA[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
132 &v->DPPCLKUsingSingleDPP[k]); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
136 mode_lib->vba.DISPCLKDPPCLKVCOSpeed, v->DPPCLKUsingSingleDPP, mode_lib->vba.DPPPerPlane, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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