| /drivers/net/wireless/realtek/rtw89/ |
| D | cam.h | 15 static inline void FWCMD_SET_ADDR_IDX(void *cmd, u32 value) in FWCMD_SET_ADDR_IDX() argument
17 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(7, 0)); in FWCMD_SET_ADDR_IDX()
20 static inline void FWCMD_SET_ADDR_OFFSET(void *cmd, u32 value) in FWCMD_SET_ADDR_OFFSET() argument
22 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(15, 8)); in FWCMD_SET_ADDR_OFFSET()
25 static inline void FWCMD_SET_ADDR_LEN(void *cmd, u32 value) in FWCMD_SET_ADDR_LEN() argument
27 le32p_replace_bits((__le32 *)(cmd) + 1, value, GENMASK(23, 16)); in FWCMD_SET_ADDR_LEN()
30 static inline void FWCMD_SET_ADDR_VALID(void *cmd, u32 value) in FWCMD_SET_ADDR_VALID() argument
32 le32p_replace_bits((__le32 *)(cmd) + 2, value, BIT(0)); in FWCMD_SET_ADDR_VALID()
35 static inline void FWCMD_SET_ADDR_NET_TYPE(void *cmd, u32 value) in FWCMD_SET_ADDR_NET_TYPE() argument
37 le32p_replace_bits((__le32 *)(cmd) + 2, value, GENMASK(2, 1)); in FWCMD_SET_ADDR_NET_TYPE()
[all …]
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| /drivers/net/wireless/realtek/rtw88/ |
| D | fw.h | 387 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
388 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
389 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
390 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
391 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
392 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
393 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
394 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
403 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
404 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
[all …]
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| /drivers/media/pci/cx25821/ |
| D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
[all …]
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| /drivers/phy/tegra/ |
| D | xusb-tegra210.c | 468 u32 value; in tegra210_pex_uphy_enable() local
486 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
487 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
489 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
491 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
493 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
494 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
496 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
498 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
500 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
[all …]
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| D | xusb-tegra186.c | 278 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset) in ao_writel() argument
280 writel(value, priv->ao_regs + offset); in ao_writel()
334 u32 value; in tegra186_utmi_enable_phy_sleepwalk() local
339 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
340 value &= ~MASTER_ENABLE; in tegra186_utmi_enable_phy_sleepwalk()
341 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
344 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
345 value |= MASTER_CFG_SEL; in tegra186_utmi_enable_phy_sleepwalk()
346 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index)); in tegra186_utmi_enable_phy_sleepwalk()
349 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL); in tegra186_utmi_enable_phy_sleepwalk()
[all …]
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| D | xusb-tegra124.c | 227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_opp_csc_v.c | 127 uint32_t value = 0; in program_color_matrix_v() local
131 value, in program_color_matrix_v()
137 value, in program_color_matrix_v()
142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
145 uint32_t value = 0; in program_color_matrix_v() local
149 value, in program_color_matrix_v()
155 value, in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
163 uint32_t value = 0; in program_color_matrix_v() local
167 value, in program_color_matrix_v()
[all …]
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| D | dce110_opp_regamma_v.c | 37 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut() local
43 value, in power_on_lut()
49 value, in power_on_lut()
56 value, in power_on_lut()
62 value, in power_on_lut()
68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
71 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
72 if (get_reg_field_value(value, in power_on_lut()
75 get_reg_field_value(value, in power_on_lut()
86 uint32_t value; in set_bypass_input_gamma() local
[all …]
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| D | dce110_timing_generator.c | 95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
101 field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); in dce110_timing_generator_is_in_vertical_blank()
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
135 value, in dce110_timing_generator_enable_crtc()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
143 value = 0; in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
160 value, in dce110_timing_generator_program_blank_color()
[all …]
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| D | dce110_mem_input_v.c | 43 uint32_t value = 0; in set_flip_control() local
45 value = dm_read_reg( in set_flip_control()
49 set_reg_field_value(value, 1, in set_flip_control()
56 value); in set_flip_control()
64 uint32_t value = 0; in program_pri_addr_c() local
70 set_reg_field_value(value, temp, in program_pri_addr_c()
77 value); in program_pri_addr_c()
80 value = 0; in program_pri_addr_c()
84 set_reg_field_value(value, temp, in program_pri_addr_c()
91 value); in program_pri_addr_c()
[all …]
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| D | dce110_timing_generator_v.c | 59 uint32_t value; in dce110_timing_generator_v_enable_crtc() local
61 value = 0; in dce110_timing_generator_v_enable_crtc()
62 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
65 mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
68 value = 0; in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
71 value = 0; in dce110_timing_generator_v_enable_crtc()
72 set_reg_field_value(value, 1, in dce110_timing_generator_v_enable_crtc()
75 mmCRTCV_MASTER_EN, value); in dce110_timing_generator_v_enable_crtc()
82 uint32_t value; in dce110_timing_generator_v_disable_crtc() local
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
[all …]
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| /drivers/gpu/drm/amd/display/include/ |
| D | fixed31_32.h | 58 long long value; member
91 res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; in dc_fixpt_from_int()
109 res.value = -arg.value; in dc_fixpt_neg()
120 if (arg.value < 0) in dc_fixpt_abs()
137 return arg1.value < arg2.value; in dc_fixpt_lt()
146 return arg1.value <= arg2.value; in dc_fixpt_le()
155 return arg1.value == arg2.value; in dc_fixpt_eq()
164 if (arg1.value <= arg2.value) in dc_fixpt_min()
176 if (arg1.value <= arg2.value) in dc_fixpt_max()
212 ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || in dc_fixpt_shl()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 1343 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_16p()
1345 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_16p()
1347 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_16p()
1355 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_64p()
1357 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_64p()
1359 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_64p()
1367 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_16p()
1369 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_4tap_16p()
1371 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_4tap_16p()
1379 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_64p()
[all …]
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| D | dce_audio.c | 52 #define AZ_REG_WRITE(reg_name, value) \ argument
53 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
74 uint32_t value = 0; in read_indirect_azalia_reg() local
81 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); in read_indirect_azalia_reg()
83 return value; in read_indirect_azalia_reg()
291 uint32_t value = 0; in set_high_bit_rate_capable() local
294 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); in set_high_bit_rate_capable()
296 set_reg_field_value(value, capable, in set_high_bit_rate_capable()
300 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); in set_high_bit_rate_capable()
308 uint32_t value = 0; in set_video_latency() local
[all …]
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2_dma.c | 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
31 value |= XGMAC_EAME; in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
43 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
[all …]
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| D | dwmac4_core.c | 27 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init() local
30 value |= GMAC_CORE_INIT; in dwmac4_core_init()
33 value |= GMAC_CONFIG_TE; in dwmac4_core_init()
35 value &= hw->link.speed_mask; in dwmac4_core_init()
38 value |= hw->link.speed1000; in dwmac4_core_init()
41 value |= hw->link.speed100; in dwmac4_core_init()
44 value |= hw->link.speed10; in dwmac4_core_init()
49 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
56 value = GMAC_INT_DEFAULT_ENABLE; in dwmac4_core_init()
59 value |= GMAC_PCS_IRQ_DEFAULT; in dwmac4_core_init()
[all …]
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| D | dwxgmac2_core.c | 70 u32 value; in dwxgmac2_rx_ipc() local
72 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
74 value |= XGMAC_CONFIG_IPC; in dwxgmac2_rx_ipc()
76 value &= ~XGMAC_CONFIG_IPC; in dwxgmac2_rx_ipc()
77 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
86 u32 value; in dwxgmac2_rx_queue_enable() local
88 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue); in dwxgmac2_rx_queue_enable()
90 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue); in dwxgmac2_rx_queue_enable()
92 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue); in dwxgmac2_rx_queue_enable()
93 writel(value, ioaddr + XGMAC_RXQ_CTRL0); in dwxgmac2_rx_queue_enable()
[all …]
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| /drivers/net/wwan/t7xx/ |
| D | t7xx_dpmaif.c | 37 u32 value, ul_intr_enable, dl_intr_enable; in t7xx_dpmaif_init_intr() local
50 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
65 value, (value & ul_intr_enable) != ul_intr_enable, 0, in t7xx_dpmaif_init_intr()
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
75 value |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1; in t7xx_dpmaif_init_intr()
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0); in t7xx_dpmaif_init_intr()
85 u32 value, ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr() local
94 value, (value & ul_int_que_done) == ul_int_que_done, 0, in t7xx_dpmaif_mask_ulq_intr()
99 value); in t7xx_dpmaif_mask_ulq_intr()
105 u32 value, ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr() local
[all …]
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| /drivers/gpu/drm/i915/ |
| D | i915_getparam.c | 22 int value = 0; in i915_getparam_ioctl() local
32 value = pdev->device; in i915_getparam_ioctl()
35 value = pdev->revision; in i915_getparam_ioctl()
38 value = to_gt(i915)->ggtt->num_fences; in i915_getparam_ioctl()
41 value = !!i915->display.overlay; in i915_getparam_ioctl()
44 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
48 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
52 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
56 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
60 value = HAS_LLC(i915); in i915_getparam_ioctl()
[all …]
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| /drivers/infiniband/hw/bnxt_re/ |
| D | hw_counters.c | 159 stats->value[BNXT_RE_TX_ATOMIC_REQ] = s->tx_atomic_req; in bnxt_re_copy_ext_stats()
160 stats->value[BNXT_RE_TX_READ_REQ] = s->tx_read_req; in bnxt_re_copy_ext_stats()
161 stats->value[BNXT_RE_TX_READ_RES] = s->tx_read_res; in bnxt_re_copy_ext_stats()
162 stats->value[BNXT_RE_TX_WRITE_REQ] = s->tx_write_req; in bnxt_re_copy_ext_stats()
163 stats->value[BNXT_RE_TX_SEND_REQ] = s->tx_send_req; in bnxt_re_copy_ext_stats()
164 stats->value[BNXT_RE_TX_ROCE_PKTS] = s->tx_roce_pkts; in bnxt_re_copy_ext_stats()
165 stats->value[BNXT_RE_TX_ROCE_BYTES] = s->tx_roce_bytes; in bnxt_re_copy_ext_stats()
166 stats->value[BNXT_RE_RX_ATOMIC_REQ] = s->rx_atomic_req; in bnxt_re_copy_ext_stats()
167 stats->value[BNXT_RE_RX_READ_REQ] = s->rx_read_req; in bnxt_re_copy_ext_stats()
168 stats->value[BNXT_RE_RX_READ_RESP] = s->rx_read_res; in bnxt_re_copy_ext_stats()
[all …]
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| /drivers/gpu/drm/tegra/ |
| D | sor.c | 486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
490 return value; in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
544 u32 value; in tegra_clk_sor_pad_set_parent() local
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
[all …]
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| /drivers/net/ethernet/sfc/falcon/ |
| D | io.h | 67 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value, in _ef4_writeq() argument
70 __raw_writeq((__force u64)value, efx->membase + reg); in _ef4_writeq()
78 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value, in _ef4_writed() argument
81 __raw_writel((__force u32)value, efx->membase + reg); in _ef4_writed()
89 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo() argument
96 EF4_OWORD_VAL(*value)); in ef4_writeo()
100 _ef4_writeq(efx, value->u64[0], reg + 0); in ef4_writeo()
101 _ef4_writeq(efx, value->u64[1], reg + 8); in ef4_writeo()
103 _ef4_writed(efx, value->u32[0], reg + 0); in ef4_writeo()
104 _ef4_writed(efx, value->u32[1], reg + 4); in ef4_writeo()
[all …]
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| /drivers/net/ethernet/sfc/siena/ |
| D | io.h | 84 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq() argument
87 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
95 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed() argument
98 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
106 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo() argument
113 EFX_OWORD_VAL(*value)); in efx_writeo()
117 _efx_writeq(efx, value->u64[0], reg + 0); in efx_writeo()
118 _efx_writeq(efx, value->u64[1], reg + 8); in efx_writeo()
120 _efx_writed(efx, value->u32[0], reg + 0); in efx_writeo()
121 _efx_writed(efx, value->u32[1], reg + 4); in efx_writeo()
[all …]
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| /drivers/iio/accel/ |
| D | st_accel_core.c | 130 { .hz = 1, .value = 0x01, },
131 { .hz = 10, .value = 0x02, },
132 { .hz = 25, .value = 0x03, },
133 { .hz = 50, .value = 0x04, },
134 { .hz = 100, .value = 0x05, },
135 { .hz = 200, .value = 0x06, },
136 { .hz = 400, .value = 0x07, },
137 { .hz = 1600, .value = 0x08, },
155 .value = 0x00,
160 .value = 0x01,
[all …]
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