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Searched refs:vce (Results 1 – 18 of 18) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vce.c161 r = amdgpu_ucode_request(adev, &adev->vce.fw, fw_name); in amdgpu_vce_sw_init()
165 amdgpu_ucode_release(&adev->vce.fw); in amdgpu_vce_sw_init()
169 hdr = (const struct common_firmware_header *)adev->vce.fw->data; in amdgpu_vce_sw_init()
177 adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | in amdgpu_vce_sw_init()
183 &adev->vce.vcpu_bo, in amdgpu_vce_sw_init()
184 &adev->vce.gpu_addr, &adev->vce.cpu_addr); in amdgpu_vce_sw_init()
191 atomic_set(&adev->vce.handles[i], 0); in amdgpu_vce_sw_init()
192 adev->vce.filp[i] = NULL; in amdgpu_vce_sw_init()
195 INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler); in amdgpu_vce_sw_init()
196 mutex_init(&adev->vce.idle_mutex); in amdgpu_vce_sw_init()
[all …]
Dvce_v3_0.c83 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_rptr()
84 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_rptr()
86 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_rptr()
115 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_get_wptr()
116 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_get_wptr()
118 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_get_wptr()
146 if (adev->vce.harvest_config == 0 || in vce_v3_0_ring_set_wptr()
147 adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE1) in vce_v3_0_ring_set_wptr()
149 else if (adev->vce.harvest_config == AMDGPU_VCE_HARVEST_VCE0) in vce_v3_0_ring_set_wptr()
272 if (adev->vce.harvest_config & (1 << idx)) in vce_v3_0_start()
[all …]
Dvce_v4_0.c179 WDOORBELL32(adev->vce.ring[0].doorbell_index, 0); in vce_v4_0_mmsch_start()
180 *adev->vce.ring[0].wptr_cpu_addr = 0; in vce_v4_0_mmsch_start()
181 adev->vce.ring[0].wptr = 0; in vce_v4_0_mmsch_start()
182 adev->vce.ring[0].wptr_old = 0; in vce_v4_0_mmsch_start()
233 ring = &adev->vce.ring[0]; in vce_v4_0_sriov_start()
263 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
266 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
273 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
276 (adev->vce.gpu_addr >> 40) & 0xff); in vce_v4_0_sriov_start()
279 adev->vce.gpu_addr >> 8); in vce_v4_0_sriov_start()
[all …]
Dvce_v2_0.c183 WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); in vce_v2_0_mc_resume()
243 ring = &adev->vce.ring[0]; in vce_v2_0_start()
250 ring = &adev->vce.ring[1]; in vce_v2_0_start()
405 adev->vce.num_rings = 2; in vce_v2_0_early_init()
420 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq); in vce_v2_0_sw_init()
433 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_sw_init()
436 ring = &adev->vce.ring[i]; in vce_v2_0_sw_init()
438 r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0, in vce_v2_0_sw_init()
469 for (i = 0; i < adev->vce.num_rings; i++) { in vce_v2_0_hw_init()
470 r = amdgpu_ring_test_helper(&adev->vce.ring[i]); in vce_v2_0_hw_init()
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Damdgpu_kms.c209 fw_info->ver = adev->vce.fw_version; in amdgpu_firmware_info()
210 fw_info->feature = adev->vce.fb_version; in amdgpu_firmware_info()
413 for (i = 0; i < adev->vce.num_rings; i++) in amdgpu_hw_ip_info()
414 if (adev->vce.ring[i].sched.ready) in amdgpu_hw_ip_info()
821 if (adev->vce.fw_version && in amdgpu_info_ioctl()
822 adev->vce.fw_version < AMDGPU_VCE_FW_53_45) in amdgpu_info_ioctl()
845 dev_info->vce_harvest_config = adev->vce.harvest_config; in amdgpu_info_ioctl()
Damdgpu_virt.c549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
Damdgpu_ucode.c684 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
Damdgpu.h941 struct amdgpu_vce vce; member
/drivers/gpu/drm/radeon/
Dradeon_vce.c65 INIT_DELAYED_WORK(&rdev->vce.idle_work, radeon_vce_idle_work_handler); in radeon_vce_init()
121 if (sscanf(c, "%2u]", &rdev->vce.fb_version) != 1) in radeon_vce_init()
125 start, mid, end, rdev->vce.fb_version); in radeon_vce_init()
127 rdev->vce.fw_version = (start << 24) | (mid << 16) | (end << 8); in radeon_vce_init()
130 if ((rdev->vce.fw_version != ((40 << 24) | (2 << 16) | (2 << 8))) && in radeon_vce_init()
131 (rdev->vce.fw_version != ((50 << 24) | (0 << 16) | (1 << 8))) && in radeon_vce_init()
132 (rdev->vce.fw_version != ((50 << 24) | (1 << 16) | (2 << 8)))) in radeon_vce_init()
143 &rdev->vce.vcpu_bo); in radeon_vce_init()
149 r = radeon_bo_reserve(rdev->vce.vcpu_bo, false); in radeon_vce_init()
151 radeon_bo_unref(&rdev->vce.vcpu_bo); in radeon_vce_init()
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Dvce_v1_0.c205 rdev->vce.keyselect = le32_to_cpu(sign->val[i].keyselect); in vce_v1_0_load_fw()
218 uint64_t addr = rdev->vce.gpu_addr; in vce_v1_0_resume()
254 WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect); in vce_v1_0_resume()
Dvce_v2_0.c160 uint64_t addr = rdev->vce.gpu_addr; in vce_v2_0_resume()
Dradeon_drv.c239 MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)");
240 module_param_named(vce, radeon_vce, int, 0444);
Dradeon_kms.c540 *value = rdev->vce.fw_version; in radeon_info_ioctl()
543 *value = rdev->vce.fb_version; in radeon_info_ioctl()
Dradeon.h2380 struct radeon_vce vce; member
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dsmu10_hwmgr.h111 uint32_t vce : 1; member
Dsmu8_hwmgr.h134 uint32_t vce : 1; member
/drivers/scsi/qla2xxx/
Dqla_isr.c2858 struct vp_ctrl_entry_24xx *vce) in qla_ctrlvp_completed() argument
2864 sp = qla2x00_get_sp_from_handle(vha, func, req, vce); in qla_ctrlvp_completed()
2868 if (vce->entry_status != 0) { in qla_ctrlvp_completed()
2871 sp->name, vce->entry_status); in qla_ctrlvp_completed()
2873 } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) { in qla_ctrlvp_completed()
2876 sp->name, le16_to_cpu(vce->comp_status), in qla_ctrlvp_completed()
2877 le16_to_cpu(vce->vp_idx_failed)); in qla_ctrlvp_completed()
Dqla_iocb.c3815 qla25xx_ctrlvp_iocb(srb_t *sp, struct vp_ctrl_entry_24xx *vce) in qla25xx_ctrlvp_iocb() argument
3819 vce->entry_type = VP_CTRL_IOCB_TYPE; in qla25xx_ctrlvp_iocb()
3820 vce->handle = sp->handle; in qla25xx_ctrlvp_iocb()
3821 vce->entry_count = 1; in qla25xx_ctrlvp_iocb()
3822 vce->command = cpu_to_le16(sp->u.iocb_cmd.u.ctrlvp.cmd); in qla25xx_ctrlvp_iocb()
3823 vce->vp_count = cpu_to_le16(1); in qla25xx_ctrlvp_iocb()
3831 vce->vp_idx_map[map] |= 1 << pos; in qla25xx_ctrlvp_iocb()