| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_ih.c | 70 ih->wptr_addr = dma_addr + ih->ring_size; in amdgpu_ih_ring_init()
97 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; in amdgpu_ih_ring_init()
133 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); in amdgpu_ih_ring_fini()
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| D | cik_ih.c | 136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
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| D | si_ih.c | 84 WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in si_ih_irq_init()
85 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in si_ih_irq_init()
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| D | iceland_ih.c | 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in iceland_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in iceland_ih_irq_init()
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| D | cz_ih.c | 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cz_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cz_ih_irq_init()
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| D | tonga_ih.c | 138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in tonga_ih_irq_init()
139 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in tonga_ih_irq_init()
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| D | amdgpu_ih.h | 62 uint64_t wptr_addr; member
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| D | vega10_ih.c | 237 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega10_ih_enable_ring()
238 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega10_ih_enable_ring()
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| D | ih_v6_0.c | 269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_0_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_0_enable_ring()
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| D | vega20_ih.c | 246 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega20_ih_enable_ring()
247 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega20_ih_enable_ring()
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| D | ih_v6_1.c | 269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_1_enable_ring()
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_1_enable_ring()
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| D | navi10_ih.c | 293 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in navi10_ih_enable_ring()
294 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in navi10_ih_enable_ring()
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| D | amdgpu_mes.h | 218 uint64_t wptr_addr; member
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| D | mes_v11_0.c | 193 mes_add_queue_pkt.wptr_addr = input->wptr_mc_addr; in mes_v11_0_add_hw_queue()
195 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v11_0_add_hw_queue()
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| D | mes_v10_1.c | 175 mes_add_queue_pkt.wptr_addr = input->wptr_addr; in mes_v10_1_add_hw_queue()
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| D | gfx_v9_4_3.c | 83 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); in gfx_v9_4_3_kiq_map_queues() local
105 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_4_3_kiq_map_queues()
106 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v9_4_3_kiq_map_queues()
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| D | amdgpu_mes.c | 652 queue_input.wptr_addr = qprops->wptr_gpu_addr; in amdgpu_mes_add_hw_queue()
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| D | gfx_v11_0.c | 152 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues() local
187 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx11_kiq_map_queues()
188 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx11_kiq_map_queues()
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| D | gfx_v8_0.c | 4354 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v8_0_kiq_kcq_enable() local
4368 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v8_0_kiq_kcq_enable()
4369 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v8_0_kiq_kcq_enable()
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| D | gfx_v9_0.c | 790 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v9_0_kiq_map_queues() local
812 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx_v9_0_kiq_map_queues()
813 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx_v9_0_kiq_map_queues()
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| D | gfx_v10_0.c | 3513 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx10_kiq_map_queues() local
3545 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); in gfx10_kiq_map_queues()
3546 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); in gfx10_kiq_map_queues()
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| /drivers/gpu/drm/amd/include/ |
| D | mes_api_def.h | 245 uint64_t wptr_addr; member
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| D | mes_v11_api_def.h | 255 uint64_t wptr_addr; member
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| /drivers/gpu/drm/amd/amdkfd/ |
| D | kfd_device_queue_manager.c | 215 queue_input.wptr_addr = (uint64_t)q->properties.write_ptr; in add_queue_mes()
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