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Searched refs:write_reg (Results 1 – 25 of 172) sorted by relevance

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/drivers/staging/fbtft/
Dfb_bd663474.c31 write_reg(par, 0x000, 0x0001); /*oscillator 0: stop, 1: operation */ in init_display()
35 write_reg(par, 0x100, 0x0000); /* power supply setup */ in init_display()
36 write_reg(par, 0x101, 0x0000); in init_display()
37 write_reg(par, 0x102, 0x3110); in init_display()
38 write_reg(par, 0x103, 0xe200); in init_display()
39 write_reg(par, 0x110, 0x009d); in init_display()
40 write_reg(par, 0x111, 0x0022); in init_display()
41 write_reg(par, 0x100, 0x0120); in init_display()
44 write_reg(par, 0x100, 0x3120); in init_display()
47 write_reg(par, 0x001, 0x0100); in init_display()
[all …]
Dfb_upd161704.c31 write_reg(par, 0x0003, 0x0001); /* Soft reset */ in init_display()
34 write_reg(par, 0x003A, 0x0001); /*Oscillator 0: stop, 1: operation */ in init_display()
38 write_reg(par, 0x0024, 0x007B); /* amplitude setting */ in init_display()
40 write_reg(par, 0x0025, 0x003B); /* amplitude setting */ in init_display()
41 write_reg(par, 0x0026, 0x0034); /* amplitude setting */ in init_display()
43 write_reg(par, 0x0027, 0x0004); /* amplitude setting */ in init_display()
44 write_reg(par, 0x0052, 0x0025); /* circuit setting 1 */ in init_display()
46 write_reg(par, 0x0053, 0x0033); /* circuit setting 2 */ in init_display()
47 write_reg(par, 0x0061, 0x001C); /* adjustment V10 positive polarity */ in init_display()
49 write_reg(par, 0x0062, 0x002C); /* adjustment V9 negative polarity */ in init_display()
[all …]
Dfb_ili9320.c26 write_reg(par, 0x0000); in read_devicecode()
49 write_reg(par, 0x00E5, 0x8000); in init_display()
52 write_reg(par, 0x0000, 0x0001); in init_display()
55 write_reg(par, 0x0001, 0x0100); in init_display()
58 write_reg(par, 0x0002, 0x0700); in init_display()
61 write_reg(par, 0x0004, 0x0000); in init_display()
64 write_reg(par, 0x0008, 0x0202); in init_display()
67 write_reg(par, 0x0009, 0x0000); in init_display()
70 write_reg(par, 0x000A, 0x0000); in init_display()
73 write_reg(par, 0x000C, 0x0000); in init_display()
[all …]
Dfb_s6d1121.c33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
41 write_reg(par, 0x0013, 0x674F); in init_display()
42 write_reg(par, 0x0011, 0x2003); in init_display()
[all …]
Dfb_ili9325.c96 write_reg(par, 0x00E3, 0x3008); /* Set internal timing */ in init_display()
97 write_reg(par, 0x00E7, 0x0012); /* Set internal timing */ in init_display()
98 write_reg(par, 0x00EF, 0x1231); /* Set internal timing */ in init_display()
99 write_reg(par, 0x0001, 0x0100); /* set SS and SM bit */ in init_display()
100 write_reg(par, 0x0002, 0x0700); /* set 1 line inversion */ in init_display()
101 write_reg(par, 0x0004, 0x0000); /* Resize register */ in init_display()
102 write_reg(par, 0x0008, 0x0207); /* set the back porch and front porch */ in init_display()
103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ in init_display()
104 write_reg(par, 0x000A, 0x0000); /* FMARK function */ in init_display()
105 write_reg(par, 0x000C, 0x0000); /* RGB interface setting */ in init_display()
[all …]
Dfb_ra8875.c55 write_reg(par, 0x88, 0x0A); in init_display()
56 write_reg(par, 0x89, 0x02); in init_display()
59 write_reg(par, 0x10, 0x0C); in init_display()
61 write_reg(par, 0x04, 0x03); in init_display()
64 write_reg(par, 0x14, 0x27); in init_display()
65 write_reg(par, 0x15, 0x00); in init_display()
66 write_reg(par, 0x16, 0x05); in init_display()
67 write_reg(par, 0x17, 0x04); in init_display()
68 write_reg(par, 0x18, 0x03); in init_display()
70 write_reg(par, 0x19, 0xEF); in init_display()
[all …]
Dfb_ssd1289.c30 write_reg(par, 0x00, 0x0001); in init_display()
31 write_reg(par, 0x03, 0xA8A4); in init_display()
32 write_reg(par, 0x0C, 0x0000); in init_display()
33 write_reg(par, 0x0D, 0x080C); in init_display()
34 write_reg(par, 0x0E, 0x2B00); in init_display()
35 write_reg(par, 0x1E, 0x00B7); in init_display()
36 write_reg(par, 0x01, in init_display()
38 write_reg(par, 0x02, 0x0600); in init_display()
39 write_reg(par, 0x10, 0x0000); in init_display()
40 write_reg(par, 0x05, 0x0000); in init_display()
[all …]
Dfb_hx8347d.c28 write_reg(par, 0xEA, 0x00); in init_display()
29 write_reg(par, 0xEB, 0x20); in init_display()
30 write_reg(par, 0xEC, 0x0C); in init_display()
31 write_reg(par, 0xED, 0xC4); in init_display()
32 write_reg(par, 0xE8, 0x40); in init_display()
33 write_reg(par, 0xE9, 0x38); in init_display()
34 write_reg(par, 0xF1, 0x01); in init_display()
35 write_reg(par, 0xF2, 0x10); in init_display()
36 write_reg(par, 0x27, 0xA3); in init_display()
39 write_reg(par, 0x1B, 0x1B); in init_display()
[all …]
Dfb_tinylcd.c24 write_reg(par, 0xB0, 0x80); in init_display()
25 write_reg(par, 0xC0, 0x0A, 0x0A); in init_display()
26 write_reg(par, 0xC1, 0x45, 0x07); in init_display()
27 write_reg(par, 0xC2, 0x33); in init_display()
28 write_reg(par, 0xC5, 0x00, 0x42, 0x80); in init_display()
29 write_reg(par, 0xB1, 0xD0, 0x11); in init_display()
30 write_reg(par, 0xB4, 0x02); in init_display()
31 write_reg(par, 0xB6, 0x00, 0x22, 0x3B); in init_display()
32 write_reg(par, 0xB7, 0x07); in init_display()
33 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0x58); in init_display()
[all …]
Dfb_ssd1306.c46 write_reg(par, 0xAE); in init_display()
49 write_reg(par, 0xD5); in init_display()
50 write_reg(par, 0x80); in init_display()
53 write_reg(par, 0xA8); in init_display()
55 write_reg(par, 0x3F); in init_display()
57 write_reg(par, 0x2F); in init_display()
59 write_reg(par, 0x1F); in init_display()
62 write_reg(par, 0xD3); in init_display()
63 write_reg(par, 0x0); in init_display()
66 write_reg(par, 0x40 | 0x0); in init_display()
[all …]
Dfb_seps525.c104 write_reg(par, SEPS525_REDUCE_CURRENT, 0x03); in init_display()
107 write_reg(par, SEPS525_REDUCE_CURRENT, 0x00); in init_display()
110 write_reg(par, SEPS525_SCREEN_SAVER_CONTEROL, 0x00); in init_display()
112 write_reg(par, SEPS525_OSC_CTL, 0x01); in init_display()
114 write_reg(par, SEPS525_CLOCK_DIV, 0x90); in init_display()
116 write_reg(par, SEPS525_IREF, 0x01); in init_display()
119 write_reg(par, SEPS525_PRECHARGE_TIME_R, 0x04); in init_display()
120 write_reg(par, SEPS525_PRECHARGE_TIME_G, 0x05); in init_display()
121 write_reg(par, SEPS525_PRECHARGE_TIME_B, 0x05); in init_display()
124 write_reg(par, SEPS525_PRECHARGE_CURRENT_R, 0x9D); in init_display()
[all …]
Dfb_ssd1305.c47 write_reg(par, 0xAE); in init_display()
50 write_reg(par, 0xD5); in init_display()
51 write_reg(par, 0x80); in init_display()
54 write_reg(par, 0xA8); in init_display()
56 write_reg(par, 0x3F); in init_display()
58 write_reg(par, 0x1F); in init_display()
61 write_reg(par, 0xD3); in init_display()
62 write_reg(par, 0x0); in init_display()
65 write_reg(par, 0x40 | 0x0); in init_display()
68 write_reg(par, 0x8D); in init_display()
[all …]
Dfb_ili9340.c25 write_reg(par, 0xEF, 0x03, 0x80, 0x02); in init_display()
26 write_reg(par, 0xCF, 0x00, 0XC1, 0X30); in init_display()
27 write_reg(par, 0xED, 0x64, 0x03, 0X12, 0X81); in init_display()
28 write_reg(par, 0xE8, 0x85, 0x00, 0x78); in init_display()
29 write_reg(par, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02); in init_display()
30 write_reg(par, 0xF7, 0x20); in init_display()
31 write_reg(par, 0xEA, 0x00, 0x00); in init_display()
34 write_reg(par, 0xC0, 0x23); in init_display()
37 write_reg(par, 0xC1, 0x10); in init_display()
40 write_reg(par, 0xC5, 0x3e, 0x28); in init_display()
[all …]
Dfb_ili9341.c34 write_reg(par, MIPI_DCS_SOFT_RESET); in init_display()
36 write_reg(par, MIPI_DCS_SET_DISPLAY_OFF); in init_display()
38 write_reg(par, 0xCF, 0x00, 0x83, 0x30); in init_display()
39 write_reg(par, 0xED, 0x64, 0x03, 0x12, 0x81); in init_display()
40 write_reg(par, 0xE8, 0x85, 0x01, 0x79); in init_display()
41 write_reg(par, 0xCB, 0x39, 0X2C, 0x00, 0x34, 0x02); in init_display()
42 write_reg(par, 0xF7, 0x20); in init_display()
43 write_reg(par, 0xEA, 0x00, 0x00); in init_display()
45 write_reg(par, 0xC0, 0x26); in init_display()
46 write_reg(par, 0xC1, 0x11); in init_display()
[all …]
Dfb_ssd1351.c36 write_reg(par, 0xfd, 0x12); /* Command Lock */ in init_display()
37 write_reg(par, 0xfd, 0xb1); /* Command Lock */ in init_display()
38 write_reg(par, 0xae); /* Display Off */ in init_display()
39 write_reg(par, 0xb3, 0xf1); /* Front Clock Div */ in init_display()
40 write_reg(par, 0xca, 0x7f); /* Set Mux Ratio */ in init_display()
41 write_reg(par, 0x15, 0x00, 0x7f); /* Set Column Address */ in init_display()
42 write_reg(par, 0x75, 0x00, 0x7f); /* Set Row Address */ in init_display()
43 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ in init_display()
44 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ in init_display()
45 write_reg(par, 0xb5, 0x00); /* Set GPIO */ in init_display()
[all …]
Dfb_ssd1325.c38 write_reg(par, 0xb3); in init_display()
39 write_reg(par, 0xf0); in init_display()
40 write_reg(par, 0xae); in init_display()
41 write_reg(par, 0xa1); in init_display()
42 write_reg(par, 0x00); in init_display()
43 write_reg(par, 0xa8); in init_display()
44 write_reg(par, 0x3f); in init_display()
45 write_reg(par, 0xa0); in init_display()
46 write_reg(par, 0x45); in init_display()
47 write_reg(par, 0xa2); in init_display()
[all …]
Dfb_ili9163.c79 write_reg(par, MIPI_DCS_SOFT_RESET); /* software reset */ in init_display()
81 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); /* exit sleep */ in init_display()
83 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); in init_display()
85 write_reg(par, MIPI_DCS_SET_GAMMA_CURVE, 0x02); in init_display()
87 write_reg(par, CMD_GAMRSEL, 0x01); /* Enable Gamma adj */ in init_display()
89 write_reg(par, MIPI_DCS_ENTER_NORMAL_MODE); in init_display()
90 write_reg(par, CMD_DFUNCTR, 0xff, 0x06); in init_display()
92 write_reg(par, CMD_FRMCTR1, 0x08, 0x02); in init_display()
93 write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */ in init_display()
95 write_reg(par, CMD_PWCTR1, 0x0A, 0x02); in init_display()
[all …]
Dfb_hx8357d.c30 write_reg(par, MIPI_DCS_SOFT_RESET); in init_display()
34 write_reg(par, HX8357D_SETC, 0xFF, 0x83, 0x57); in init_display()
38 write_reg(par, HX8357_SETRGB, 0x00, 0x00, 0x06, 0x06); in init_display()
41 write_reg(par, HX8357D_SETCOM, 0x25); in init_display()
44 write_reg(par, HX8357_SETOSC, 0x68); in init_display()
47 write_reg(par, HX8357_SETPANEL, 0x05); in init_display()
49 write_reg(par, HX8357_SETPWR1, in init_display()
57 write_reg(par, HX8357D_SETSTBA, in init_display()
65 write_reg(par, HX8357D_SETCYC, in init_display()
74 write_reg(par, HX8357D_SETGAMMA, in init_display()
[all …]
Dfb_uc1701.c68 write_reg(par, LCD_RESET_CMD); in init_display()
72 write_reg(par, LCD_START_LINE); in init_display()
75 write_reg(par, LCD_BOTTOMVIEW | 1); in init_display()
78 write_reg(par, LCD_SCAN_DIR | 0x00); in init_display()
81 write_reg(par, LCD_ALL_PIXEL | 0); in init_display()
84 write_reg(par, LCD_DISPLAY_INVERT | 0); in init_display()
87 write_reg(par, LCD_BIAS | 0); in init_display()
90 write_reg(par, LCD_POWER_CONTROL | 0x07); in init_display()
93 write_reg(par, LCD_VOLTAGE | 0x07); in init_display()
96 write_reg(par, LCD_VOLUME_MODE); in init_display()
[all …]
Dfb_ssd1331.c29 write_reg(par, 0xae); /* Display Off */ in init_display()
33 write_reg(par, 0xa0, 0x60 | (par->bgr << 2)); in init_display()
35 write_reg(par, 0xa0, 0x72 | (par->bgr << 2)); in init_display()
37 write_reg(par, 0x72); /* RGB colour */ in init_display()
38 write_reg(par, 0xa1, 0x00); /* Set Display Start Line */ in init_display()
39 write_reg(par, 0xa2, 0x00); /* Set Display Offset */ in init_display()
40 write_reg(par, 0xa4); /* NORMALDISPLAY */ in init_display()
41 write_reg(par, 0xa8, 0x3f); /* Set multiplex */ in init_display()
42 write_reg(par, 0xad, 0x8e); /* Set master */ in init_display()
44 write_reg(par, 0xb1, 0x31); /* Precharge */ in init_display()
[all …]
Dfb_uc1611.c81 write_reg(par, 0xE2); in init_display()
84 write_reg(par, 0xE8 | (ratio & 0x03)); in init_display()
87 write_reg(par, 0x81); in init_display()
88 write_reg(par, (gain & 0x03) << 6 | (pot & 0x3F)); in init_display()
91 write_reg(par, 0x24 | (temp & 0x03)); in init_display()
94 write_reg(par, 0x28 | (load & 0x03)); in init_display()
97 write_reg(par, 0x2C | (pump & 0x03)); in init_display()
100 write_reg(par, 0xA6 | 0x01); in init_display()
103 write_reg(par, 0xD0 | (0x02 & 0x03)); in init_display()
106 write_reg(par, 0xA8 | 0x07); in init_display()
[all …]
Dfb_hx8353d.c26 write_reg(par, 0xB9, 0xFF, 0x83, 0x53); in init_display()
29 write_reg(par, 0xB0, 0x3C, 0x01); in init_display()
32 write_reg(par, 0xB6, 0x94, 0x6C, 0x50); in init_display()
35 write_reg(par, 0xB1, 0x00, 0x01, 0x1B, 0x03, 0x01, 0x08, 0x77, 0x89); in init_display()
38 write_reg(par, 0x3A, 0x05); in init_display()
41 write_reg(par, MIPI_DCS_SET_ADDRESS_MODE, 0xC0); in init_display()
44 write_reg(par, MIPI_DCS_EXIT_SLEEP_MODE); in init_display()
48 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); in init_display()
51 write_reg(par, MIPI_DCS_WRITE_LUT, in init_display()
67 write_reg(par, 0x2a, xs >> 8, xs & 0xff, xe >> 8, xe & 0xff); in set_addr_win()
[all …]
Dfb_hx8340bn.c45 write_reg(par, 0xC1, 0xFF, 0x83, 0x40); in init_display()
53 write_reg(par, 0x11); in init_display()
57 write_reg(par, 0xCA, 0x70, 0x00, 0xD9); in init_display()
65 write_reg(par, 0xB0, 0x01, 0x11); in init_display()
68 write_reg(par, 0xC9, 0x90, 0x49, 0x10, 0x28, 0x28, 0x10, 0x00, 0x06); in init_display()
78 write_reg(par, 0xB5, 0x35, 0x20, 0x45); in init_display()
87 write_reg(par, 0xB4, 0x33, 0x25, 0x4C); in init_display()
96 write_reg(par, MIPI_DCS_SET_PIXEL_FORMAT, MIPI_DCS_PIXEL_FMT_16BIT); in init_display()
103 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); in init_display()
111 write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS, 0x00, xs, 0x00, xe); in set_addr_win()
[all …]
/drivers/media/dvb-frontends/
Dstv0910.c132 static int write_reg(struct stv *state, u16 reg, u8 val) in write_reg() function
184 status = write_reg(state, reg, (tmp & ~mask) | (val & mask)); in write_shared_reg()
202 return write_reg(state, field >> 16, new); in write_field()
210 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \
559 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp); in tracking_optimization()
572 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
575 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
577 write_reg(state, RSTV0910_P2_ACLC2S28 + in tracking_optimization()
580 write_reg(state, RSTV0910_P2_ACLC2S2Q + in tracking_optimization()
582 write_reg(state, RSTV0910_P2_ACLC2S216A + in tracking_optimization()
[all …]
/drivers/media/pci/ivtv/
Divtv-yuv.c167 write_reg(read_dec(i), 0x02804); in ivtv_yuv_filter()
168 write_reg(read_dec(i), 0x0281c); in ivtv_yuv_filter()
170 write_reg(read_dec(i), 0x02808); in ivtv_yuv_filter()
171 write_reg(read_dec(i), 0x02820); in ivtv_yuv_filter()
173 write_reg(read_dec(i), 0x0280c); in ivtv_yuv_filter()
174 write_reg(read_dec(i), 0x02824); in ivtv_yuv_filter()
176 write_reg(read_dec(i), 0x02810); in ivtv_yuv_filter()
177 write_reg(read_dec(i), 0x02828); in ivtv_yuv_filter()
179 write_reg(read_dec(i), 0x02814); in ivtv_yuv_filter()
180 write_reg(read_dec(i), 0x0282c); in ivtv_yuv_filter()
[all …]

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