Searched refs:have (Results 1 – 10 of 10) sorted by relevance
190 have = strm->avail_in; \201 strm->avail_in = have; \217 if (have == 0) goto inf_leave; \218 have--; \336 unsigned have, left; /* available input and output */ in zlib_inflate() local360 in = have; in zlib_inflate()453 if (copy > have) copy = have; in zlib_inflate()457 have -= copy; in zlib_inflate()481 state->have = 0; in zlib_inflate()485 while (state->have < state->ncode) { in zlib_inflate()[all …]
107 unsigned have; /* number of code lengths in lens[] */ member
18 * This can be run on systems which have both Altivec and vpermxor instruction.
115 /* This assumes either all CPUs have Altivec or none does */
14 to have negligible cost to permit enabling it in production
32 memory representation that can have any combination of these quirks:207 Most modern processors have enough cache to hold this table without211 you have a good reason not to.
278 If you have consumers of DWARF debug info that are not ready for279 newer revisions of DWARF, you may wish to choose this or have your465 to keep kernel developers who have to stare a lot at assembler listings593 If you say Y here, you will have some control over the system even617 Many embedded boards have a disconnected TTL level serial which can846 semantics of the generic MM. Platforms will have to opt in for1053 high-availability systems that have uptime guarantees and1087 for more than 10 seconds, without letting other interrupts have a1106 This hardlockup detector is useful on systems that don't have1201 high-availability systems that have uptime guarantees and[all …]
29 # Old GCC versions do not have proper support for no_sanitize_address.
151 If you don't enable this option, you have to explicitly specify
113 Interrupts have tighter latency requirements, and their delay should