Home
last modified time | relevance | path

Searched defs:divq (Results 1 – 7 of 7) sorted by relevance

/drivers/clk/
Dclk-highbank.c97 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
113 u32 divq, divf; in clk_pll_calc() local
137 u32 divq, divf; in clk_pll_round_rate() local
149 u32 divq, divf; in clk_pll_set_rate() local
/drivers/clk/analogbits/
Dwrpll-cln28hpc.c151 u8 divq = 0; in __wrpll_calc_divq() local
231 u8 fbdiv, divq, best_r, r; in wrpll_configure_for_rate() local
/drivers/clk/socfpga/
Dclk-pll-a10.c38 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
Dclk-pll.c42 unsigned long divf, divq, reg; in clk_pll_recalc_rate() local
/drivers/clk/imx/
Dclk-sscg-pll.c74 int divq; member
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
Dclk-frac-pll.c100 u32 val, divff, divfi, divq; in clk_pll_recalc_rate() local
/drivers/media/pci/solo6x10/
Dsolo6x10-core.c525 u32 divq, divf; in solo_pci_probe() local