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/drivers/net/wireless/realtek/rtw89/
Dfw.h341 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_IDX()
346 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_OFFSET()
351 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_LEN()
356 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_TYPE()
361 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_EXT_KEY()
366 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_SPP_MODE()
371 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_KEY0()
376 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_KEY1()
381 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_KEY2()
386 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) in RTW89_SET_FWCMD_SEC_KEY3()
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/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dtypes.h133 #define CONF_HAS(config, val) ((config) & (1 << (val))) argument
138 #define CONF_IS(config, val) ((config) == (1 << (val))) argument
139 #define CONF_GE(config, val) ((config) & (0-(1 << (val)))) argument
140 #define CONF_GT(config, val) ((config) & (0-2*(1 << (val)))) argument
141 #define CONF_LT(config, val) ((config) & ((1 << (val))-1)) argument
142 #define CONF_LE(config, val) ((config) & (2*(1 << (val))-1)) argument
146 #define NCONF_HAS(val) CONF_HAS(NCONF, val) argument
148 #define NCONF_IS(val) CONF_IS(NCONF, val) argument
149 #define NCONF_GE(val) CONF_GE(NCONF, val) argument
150 #define NCONF_GT(val) CONF_GT(NCONF, val) argument
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/drivers/gpu/drm/msm/adreno/
Da6xx.xml.h1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START()
1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START()
1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
1155 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE()
1182 static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A6XX_CP_PROTECT_REG_BASE_ADDR()
1188 static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A6XX_CP_PROTECT_REG_MASK_LEN()
1257 static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) in A6XX_CP_ROQ_RB_STAT_RPTR()
1263 static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) in A6XX_CP_ROQ_RB_STAT_WPTR()
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Dadreno_pm4.xml.h526 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) in CP_LOAD_STATE_0_DST_OFF()
532 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) in CP_LOAD_STATE_0_STATE_SRC()
538 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) in CP_LOAD_STATE_0_STATE_BLOCK()
544 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE_0_NUM_UNIT()
552 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) in CP_LOAD_STATE_1_STATE_TYPE()
558 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) in CP_LOAD_STATE_1_EXT_SRC_ADDR()
566 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) in CP_LOAD_STATE4_0_DST_OFF()
572 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) in CP_LOAD_STATE4_0_STATE_SRC()
578 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) in CP_LOAD_STATE4_0_STATE_BLOCK()
584 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) in CP_LOAD_STATE4_0_NUM_UNIT()
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Da3xx.xml.h947 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) in A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES()
955 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ()
961 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) in A3XX_GRAS_CL_GB_CLIP_ADJ_VERT()
969 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) in A3XX_GRAS_CL_VPORT_XOFFSET()
977 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) in A3XX_GRAS_CL_VPORT_XSCALE()
985 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) in A3XX_GRAS_CL_VPORT_YOFFSET()
993 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) in A3XX_GRAS_CL_VPORT_YSCALE()
1001 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) in A3XX_GRAS_CL_VPORT_ZOFFSET()
1009 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) in A3XX_GRAS_CL_VPORT_ZSCALE()
1017 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) in A3XX_GRAS_SU_POINT_MINMAX_MIN()
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Da4xx.xml.h845 static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) in A4XX_CGC_HLSQ_EARLY_CYC()
902 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH()
908 static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) in A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT()
924 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) in A4XX_RB_MODE_CONTROL_WIDTH()
930 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) in A4XX_RB_MODE_CONTROL_HEIGHT()
944 static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val) in A4XX_RB_MSAA_CONTROL_SAMPLES()
952 static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val) in A4XX_RB_RENDER_CONTROL2_COORD_MASK()
961 static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) in A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES()
980 static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) in A4XX_RB_MRT_CONTROL_ROP_CODE()
986 static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) in A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE()
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Dadreno_common.xml.h230 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) in AXXX_CP_RB_CNTL_BUFSZ()
236 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) in AXXX_CP_RB_CNTL_BLKSZ()
242 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) in AXXX_CP_RB_CNTL_BUF_SWAP()
253 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_SWAP()
259 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) in AXXX_CP_RB_RPTR_ADDR_ADDR()
277 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START()
283 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) in AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START()
289 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) in AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START()
297 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) in AXXX_CP_MEQ_THRESHOLDS_MEQ_END()
303 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) in AXXX_CP_MEQ_THRESHOLDS_ROQ_END()
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Da5xx.xml.h1043 static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) in A5XX_CP_PROTECT_REG_BASE_ADDR()
1049 static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) in A5XX_CP_PROTECT_REG_MASK_LEN()
1055 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_WRITE()
1061 static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) in A5XX_CP_PROTECT_REG_TRAP_READ()
1838 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB()
1844 static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val) in A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP()
1850 static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val) in A5XX_RBBM_STATUS_HLSQ_BUSY()
1856 static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val) in A5XX_RBBM_STATUS_VSC_BUSY()
1862 static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val) in A5XX_RBBM_STATUS_TPL1_BUSY()
1868 static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val) in A5XX_RBBM_STATUS_SP_BUSY()
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Da2xx.xml.h1172 static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR()
1178 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR()
1184 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR()
1190 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR()
1196 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR()
1202 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR()
1208 static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR()
1214 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR()
1220 static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR()
1226 static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) in A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR()
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/drivers/gpu/drm/panel/
Dpanel-abt-y030xx067a.c23 #define REG00_VBRT_CTRL(val) (val) argument
25 #define REG01_COM_DC(val) (val) argument
27 #define REG02_DA_CONTRAST(val) (val) argument
28 #define REG02_VESA_SEL(val) ((val) << 5) argument
31 #define REG03_VPOSITION(val) (val) argument
36 #define REG04_HPOSITION1(val) (val) argument
41 #define REG05_SLBRCHARGE(val) ((val) << 3) argument
42 #define REG05_PRECHARGE_LEVEL(val) ((val) << 6) argument
49 #define REG06_GAMMA_SEL(val) ((val) << 5) argument
58 #define REG07_AMPTST(val) ((val) << 6) argument
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/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h146 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR()
152 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR()
158 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP()
213 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL()
219 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT()
225 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) in DSI_VID_CFG0_TRAFFIC_MODE()
242 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) in DSI_VID_CFG1_RGB_SWAP()
250 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) in DSI_ACTIVE_H_START()
256 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) in DSI_ACTIVE_H_END()
264 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) in DSI_ACTIVE_V_START()
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/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5.xml.h191 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
197 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
203 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
218 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
224 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
230 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
238 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
244 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
250 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
256 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
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/drivers/gpu/drm/msm/disp/mdp4/
Dmdp4.xml.h120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
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/drivers/hwtracing/coresight/
Dcoresight-etm3x-sysfs.c16 unsigned long val; in nr_addr_cmp_show() local
26 { unsigned long val; in nr_cntr_show() local
37 unsigned long val; in nr_ctxid_cmp_show() local
48 unsigned long flags, val; in etmsr_show() local
70 unsigned long val; in reset_store() local
99 unsigned long val; in mode_show() local
112 unsigned long val; in mode_store() local
184 unsigned long val; in trigger_event_show() local
197 unsigned long val; in trigger_event_store() local
214 unsigned long val; in enable_event_show() local
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Dcoresight-etm4x-sysfs.c61 unsigned long val; in nr_pe_cmp_show() local
73 unsigned long val; in nr_addr_cmp_show() local
85 unsigned long val; in nr_cntr_show() local
97 unsigned long val; in nr_ext_inp_show() local
109 unsigned long val; in numcidc_show() local
121 unsigned long val; in numvmidc_show() local
133 unsigned long val; in nrseqstate_show() local
145 unsigned long val; in nr_resource_show() local
157 unsigned long val; in nr_ss_cmp_show() local
170 unsigned long val; in reset_store() local
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/drivers/gpu/drm/i915/soc/
Dintel_dram.c142 u32 val; in chv_detect_mem_freq() local
160 u32 val; in vlv_detect_mem_freq() local
201 static int skl_get_dimm_size(u16 val) in skl_get_dimm_size()
206 static int skl_get_dimm_width(u16 val) in skl_get_dimm_width()
223 static int skl_get_dimm_ranks(u16 val) in skl_get_dimm_ranks()
234 static int icl_get_dimm_size(u16 val) in icl_get_dimm_size()
239 static int icl_get_dimm_width(u16 val) in icl_get_dimm_width()
256 static int icl_get_dimm_ranks(u16 val) in icl_get_dimm_ranks()
276 int channel, char dimm_name, u16 val) in skl_dram_get_dimm_info()
297 int channel, u32 val) in skl_dram_get_channel_info()
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/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4_tc_u32_parse.h41 int (*val)(struct ch_filter_specification *f, __be32 val, __be32 mask); member
46 __be32 val, __be32 mask) in cxgb4_fill_ipv4_tos()
55 __be32 val, __be32 mask) in cxgb4_fill_ipv4_frag()
77 __be32 val, __be32 mask) in cxgb4_fill_ipv4_proto()
86 __be32 val, __be32 mask) in cxgb4_fill_ipv4_src_ip()
95 __be32 val, __be32 mask) in cxgb4_fill_ipv4_dst_ip()
114 __be32 val, __be32 mask) in cxgb4_fill_ipv6_tos()
123 __be32 val, __be32 mask) in cxgb4_fill_ipv6_proto()
132 __be32 val, __be32 mask) in cxgb4_fill_ipv6_src_ip0()
141 __be32 val, __be32 mask) in cxgb4_fill_ipv6_src_ip1()
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/drivers/gpu/drm/i915/
Dvlv_sideband.c79 u32 addr, u32 *val) in vlv_sideband_rw()
129 u32 val = 0; in vlv_punit_read() local
137 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val) in vlv_punit_write()
145 u32 val = 0; in vlv_bunit_read() local
153 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) in vlv_bunit_write()
161 u32 val = 0; in vlv_nc_read() local
171 u32 val = 0; in vlv_iosf_sb_read() local
180 u8 port, u32 reg, u32 val) in vlv_iosf_sb_write()
188 u32 val = 0; in vlv_cck_read() local
196 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val) in vlv_cck_write()
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/drivers/dma/ti/
Dk3-udma.h41 #define UDMA_CAP2_TCHAN_CNT(val) ((val) & 0x1ff) argument
42 #define UDMA_CAP2_ECHAN_CNT(val) (((val) >> 9) & 0x1ff) argument
43 #define UDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) argument
44 #define UDMA_CAP3_RFLOW_CNT(val) ((val) & 0x3fff) argument
45 #define UDMA_CAP3_HCHAN_CNT(val) (((val) >> 14) & 0x1ff) argument
46 #define UDMA_CAP3_UCHAN_CNT(val) (((val) >> 23) & 0x1ff) argument
48 #define BCDMA_CAP2_BCHAN_CNT(val) ((val) & 0x1ff) argument
49 #define BCDMA_CAP2_TCHAN_CNT(val) (((val) >> 9) & 0x1ff) argument
50 #define BCDMA_CAP2_RCHAN_CNT(val) (((val) >> 18) & 0x1ff) argument
51 #define BCDMA_CAP3_HBCHAN_CNT(val) (((val) >> 14) & 0x1ff) argument
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/drivers/accel/ivpu/
Divpu_hw_reg_io.h21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__) argument
22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__) argument
27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) argument
28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) argument
30 #define REGV_WR32I(reg, stride, index, val) \ argument
37 #define REG_GET_FLD(REG, FLD, val) \ argument
39 #define REG_CLR_FLD(REG, FLD, val) \ argument
41 #define REG_SET_FLD(REG, FLD, val) \ argument
43 #define REG_SET_FLD_NUM(REG, FLD, num, val) \ argument
45 #define REG_TEST_FLD(REG, FLD, val) \ argument
[all …]
Divpu_hw_40xx.c163 u32 val; in ivpu_pll_cmd_send() local
270 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_RST_EN); in ivpu_boot_host_ss_rst_drive() local
287 u32 val = REGV_RD32(VPU_40XX_HOST_SS_CPR_CLK_EN); in ivpu_boot_host_ss_clk_drive() local
304 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in ivpu_boot_noc_qreqn_check() local
314 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QACCEPTN); in ivpu_boot_noc_qacceptn_check() local
324 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); in ivpu_boot_noc_qdeny_check() local
334 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in ivpu_boot_top_noc_qrenqn_check() local
345 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QACCEPTN); in ivpu_boot_top_noc_qacceptn_check() local
356 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QDENY); in ivpu_boot_top_noc_qdeny_check() local
367 u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_IDLE_GEN); in ivpu_boot_idle_gen_drive() local
[all …]
/drivers/net/wireless/silabs/wfx/
Dhwio.c20 static int wfx_read32(struct wfx_dev *wdev, int reg, u32 *val) in wfx_read32()
37 static int wfx_write32(struct wfx_dev *wdev, int reg, u32 val) in wfx_write32()
52 static int wfx_read32_locked(struct wfx_dev *wdev, int reg, u32 *val) in wfx_read32_locked()
63 static int wfx_write32_locked(struct wfx_dev *wdev, int reg, u32 val) in wfx_write32_locked()
74 static int wfx_write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val) in wfx_write32_bits_locked()
184 static int wfx_indirect_read32_locked(struct wfx_dev *wdev, int reg, u32 addr, u32 *val) in wfx_indirect_read32_locked()
200 static int wfx_indirect_write32_locked(struct wfx_dev *wdev, int reg, u32 addr, u32 val) in wfx_indirect_write32_locked()
264 int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val) in wfx_sram_reg_read()
269 int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val) in wfx_ahb_reg_read()
274 int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val) in wfx_sram_reg_write()
[all …]
/drivers/gpu/drm/i915/display/
Dintel_cx0_phy_regs.h26 #define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) argument
29 #define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) argument
40 #define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) argument
76 #define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val) argument
88 #define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_M… argument
90 #define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_M… argument
91 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ argument
96 #define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val) argument
104 #define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MA… argument
106 #define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val) argument
[all …]
/drivers/media/pci/cx18/
Dcx18-io.h30 void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel_noretry()
35 static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_raw_writel()
52 void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel_noretry()
57 static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr) in cx18_writel()
68 void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr, in cx18_writel_expect()
90 void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) in cx18_writew_noretry()
95 static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) in cx18_writew()
111 void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) in cx18_writeb_noretry()
116 static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) in cx18_writeb()
137 static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg) in cx18_write_reg_noretry()
[all …]
/drivers/net/wireless/mediatek/mt76/mt7615/
Ddebugfs.c6 mt7615_reg_set(void *data, u64 val) in mt7615_reg_set()
18 mt7615_reg_get(void *data, u64 *val) in mt7615_reg_get()
33 mt7615_radar_pattern_set(void *data, u64 val) in mt7615_radar_pattern_set()
51 static int mt7615_config(void *data, u64 val) in mt7615_config()
66 mt7615_scs_set(void *data, u64 val) in mt7615_scs_set()
83 mt7615_scs_get(void *data, u64 *val) in mt7615_scs_get()
96 mt7615_pm_set(void *data, u64 val) in mt7615_pm_set()
137 mt7615_pm_get(void *data, u64 *val) in mt7615_pm_get()
169 mt7615_pm_idle_timeout_set(void *data, u64 val) in mt7615_pm_idle_timeout_set()
179 mt7615_pm_idle_timeout_get(void *data, u64 *val) in mt7615_pm_idle_timeout_get()
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