| /drivers/net/wireless/realtek/rtw89/ |
| D | cam.h | 15 static inline void FWCMD_SET_ADDR_IDX(void *cmd, u32 value) in FWCMD_SET_ADDR_IDX()
20 static inline void FWCMD_SET_ADDR_OFFSET(void *cmd, u32 value) in FWCMD_SET_ADDR_OFFSET()
25 static inline void FWCMD_SET_ADDR_LEN(void *cmd, u32 value) in FWCMD_SET_ADDR_LEN()
30 static inline void FWCMD_SET_ADDR_VALID(void *cmd, u32 value) in FWCMD_SET_ADDR_VALID()
35 static inline void FWCMD_SET_ADDR_NET_TYPE(void *cmd, u32 value) in FWCMD_SET_ADDR_NET_TYPE()
40 static inline void FWCMD_SET_ADDR_BCN_HIT_COND(void *cmd, u32 value) in FWCMD_SET_ADDR_BCN_HIT_COND()
45 static inline void FWCMD_SET_ADDR_HIT_RULE(void *cmd, u32 value) in FWCMD_SET_ADDR_HIT_RULE()
50 static inline void FWCMD_SET_ADDR_BB_SEL(void *cmd, u32 value) in FWCMD_SET_ADDR_BB_SEL()
55 static inline void FWCMD_SET_ADDR_ADDR_MASK(void *cmd, u32 value) in FWCMD_SET_ADDR_ADDR_MASK()
60 static inline void FWCMD_SET_ADDR_MASK_SEL(void *cmd, u32 value) in FWCMD_SET_ADDR_MASK_SEL()
[all …]
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| /drivers/gpu/drm/meson/ |
| D | meson_overlay.c | 42 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value) argument
43 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value) argument
46 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value) argument
47 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value) argument
50 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value) argument
53 #define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value) argument
56 #define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value) argument
57 #define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value) argument
61 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value) argument
62 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \ argument
[all …]
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| /drivers/net/wireless/realtek/rtw88/ |
| D | fw.h | 387 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
389 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
391 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
393 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
403 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
405 #define GENERAL_INFO_SET_FW_TX_BOUNDARY(h2c_pkt, value) \ argument
408 #define PHYDM_INFO_SET_REF_TYPE(h2c_pkt, value) \ argument
410 #define PHYDM_INFO_SET_RF_TYPE(h2c_pkt, value) \ argument
412 #define PHYDM_INFO_SET_CUT_VER(h2c_pkt, value) \ argument
414 #define PHYDM_INFO_SET_RX_ANT_STATUS(h2c_pkt, value) \ argument
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument
66 #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value) argument
[all …]
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| /drivers/net/wwan/t7xx/ |
| D | t7xx_dpmaif.c | 37 u32 value, ul_intr_enable, dl_intr_enable; in t7xx_dpmaif_init_intr() local
85 u32 value, ul_int_que_done; in t7xx_dpmaif_mask_ulq_intr() local
105 u32 value, ul_int_que_done; in t7xx_dpmaif_unmask_ulq_intr() local
136 u32 value; in t7xx_update_dlq_intr() local
145 u32 value, q_done; in t7xx_mask_dlq_intr() local
228 unsigned long value; in t7xx_dpmaif_hw_check_tx_intr() local
396 u32 value; in t7xx_dpmaif_sram_init() local
459 unsigned int value; in t7xx_dpmaif_hw_hpc_cntl_set() local
469 unsigned int value; in t7xx_dpmaif_hw_agg_cfg_set() local
488 unsigned int value, i; in t7xx_dpmaif_hw_dlq_timeout_thres_set() local
[all …]
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| /drivers/net/ethernet/sfc/falcon/ |
| D | io.h | 67 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value, in _ef4_writeq()
78 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value, in _ef4_writed()
89 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo()
113 const ef4_qword_t *value, unsigned int index) in ef4_sram_writeq()
133 static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value, in ef4_writed()
145 static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value, in ef4_reado()
164 ef4_qword_t *value, unsigned int index) in ef4_sram_readq()
184 static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value, in ef4_readd()
195 ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo_table()
202 static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value, in ef4_reado_table()
[all …]
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| /drivers/net/ethernet/sfc/siena/ |
| D | io.h | 84 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq()
95 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed()
106 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo()
130 const efx_qword_t *value, unsigned int index) in efx_sram_writeq()
150 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value, in efx_writed()
162 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value, in efx_reado()
181 efx_qword_t *value, unsigned int index) in efx_sram_readq()
201 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value, in efx_readd()
212 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo_table()
219 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value, in efx_reado_table()
[all …]
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| /drivers/net/ethernet/sfc/ |
| D | io.h | 60 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq()
71 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed()
82 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo()
105 static inline void efx_writed(struct efx_nic *efx, const efx_dword_t *value, in efx_writed()
117 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value, in efx_reado()
135 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value, in efx_readd()
146 efx_writeo_table(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo_table()
153 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value, in efx_reado_table()
173 static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, in _efx_writeo_page()
192 #define efx_writeo_page(efx, value, reg, page) \ argument
[all …]
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| /drivers/media/platform/allegro-dvt/ |
| D | nal-rbsp.c | 99 static inline int rbsp_write_bit(struct rbsp *rbsp, bool value) in rbsp_write_bit()
127 static inline int rbsp_read_bits(struct rbsp *rbsp, int n, unsigned int *value) in rbsp_read_bits()
149 static int rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int value) in rbsp_write_bits()
165 static int rbsp_read_uev(struct rbsp *rbsp, unsigned int *value) in rbsp_read_uev()
188 static int rbsp_write_uev(struct rbsp *rbsp, unsigned int *value) in rbsp_write_uev()
205 static int rbsp_read_sev(struct rbsp *rbsp, int *value) in rbsp_read_sev()
224 static int rbsp_write_sev(struct rbsp *rbsp, int *value) in rbsp_write_sev()
239 static int __rbsp_write_bit(struct rbsp *rbsp, int *value) in __rbsp_write_bit()
244 static int __rbsp_write_bits(struct rbsp *rbsp, int n, unsigned int *value) in __rbsp_write_bits()
256 static int __rbsp_read_bit(struct rbsp *rbsp, int *value) in __rbsp_read_bit()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_opp_csc_v.c | 127 uint32_t value = 0; in program_color_matrix_v() local
145 uint32_t value = 0; in program_color_matrix_v() local
163 uint32_t value = 0; in program_color_matrix_v() local
181 uint32_t value = 0; in program_color_matrix_v() local
199 uint32_t value = 0; in program_color_matrix_v() local
217 uint32_t value = 0; in program_color_matrix_v() local
241 uint32_t value = 0; in program_color_matrix_v() local
259 uint32_t value = 0; in program_color_matrix_v() local
277 uint32_t value = 0; in program_color_matrix_v() local
295 uint32_t value = 0; in program_color_matrix_v() local
[all …]
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| D | dce110_timing_generator.c | 95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
516 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_get_vblank_counter() local
536 uint32_t value; in dce110_timing_generator_get_position() local
579 uint32_t value = dm_read_reg(tg->ctx, in dce110_timing_generator_get_crtc_scanoutpos() local
614 uint32_t value = 0; in dce110_timing_generator_program_blanking() local
712 uint32_t value; in dce110_timing_generator_set_test_pattern() local
1221 uint32_t value; in dce110_timing_generator_setup_global_swap_lock() local
1322 uint32_t value; in dce110_timing_generator_tear_down_global_swap_lock() local
[all …]
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| D | dce110_timing_generator_v.c | 59 uint32_t value; in dce110_timing_generator_v_enable_crtc() local
82 uint32_t value; in dce110_timing_generator_v_disable_crtc() local
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc() local
122 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_unblank_crtc() local
143 uint32_t value = 0; in dce110_timing_generator_v_is_in_vertical_blank() local
154 uint32_t value; in dce110_timing_generator_v_is_counter_moving() local
254 uint32_t value = 0; in dce110_timing_generator_v_program_blanking() local
389 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_enable_advanced_request() local
455 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_program_blank_color() local
482 uint32_t value = 0; in dce110_timing_generator_v_set_overscan_color_black() local
[all …]
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| /drivers/net/ethernet/microchip/vcap/ |
| D | vcap_api_client.h | 24 u8 value; member
29 u32 value; member
34 u8 value[6]; member
39 u8 value[7]; member
44 u8 value[8]; member
49 u8 value[9]; member
54 u8 value[14]; member
59 u8 value[16]; member
91 u8 value; member
95 u32 value; member
[all …]
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2_dma.c | 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
40 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
55 u32 value; in dwxgmac2_dma_init_rx_chan() local
72 u32 value; in dwxgmac2_dma_init_tx_chan() local
86 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
149 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
215 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
259 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq() local
273 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq() local
[all …]
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| D | dwxgmac2_core.c | 70 u32 value; in dwxgmac2_rx_ipc() local
86 u32 value; in dwxgmac2_rx_queue_enable() local
141 u32 value, reg; in dwxgmac2_tx_queue_prio() local
158 u32 value; in dwxgmac2_rx_queue_routing() local
188 u32 value; in dwxgmac2_prog_mtl_rx_algorithms() local
211 u32 value; in dwxgmac2_prog_mtl_tx_algorithms() local
257 u32 value, reg; in dwxgmac2_map_mtl_to_dma() local
276 u32 value; in dwxgmac2_config_cbs() local
366 u32 value = XGMAC_TFE; in dwxgmac2_flow_ctrl() local
399 u32 value; in dwxgmac2_set_umac_addr() local
[all …]
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| D | dwmac4_core.c | 27 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init() local
83 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0); in dwmac4_rx_queue_enable() local
140 u32 value; in dwmac4_tx_queue_priority() local
159 u32 value; in dwmac4_rx_queue_routing() local
192 u32 value = readl(ioaddr + MTL_OPERATION_MODE); in dwmac4_prog_mtl_rx_algorithms() local
213 u32 value = readl(ioaddr + MTL_OPERATION_MODE); in dwmac4_prog_mtl_tx_algorithms() local
242 u32 value = readl(ioaddr + mtl_txqx_weight_base_addr(dwmac4_addrs, in dwmac4_set_mtl_tx_queue_weight() local
253 u32 value; in dwmac4_map_mtl_dma() local
275 u32 value; in dwmac4_config_cbs() local
325 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_rx_ipc_enable() local
[all …]
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| D | dwmac_lib.c | 19 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset() local
39 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq() local
52 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq() local
65 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx() local
72 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx() local
80 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx() local
87 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx() local
214 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt() local
270 u32 old_val, value; in stmmac_set_mac() local
|
| /drivers/gpu/drm/i915/gt/ |
| D | intel_mocs.c | 32 #define _LE_CACHEABILITY(value) ((value) << 0) argument
33 #define _LE_TGT_CACHE(value) ((value) << 2) argument
34 #define LE_LRUM(value) ((value) << 4) argument
35 #define LE_AOM(value) ((value) << 6) argument
36 #define LE_RSC(value) ((value) << 7) argument
37 #define LE_SCC(value) ((value) << 8) argument
38 #define LE_PFM(value) ((value) << 11) argument
39 #define LE_SCF(value) ((value) << 14) argument
40 #define LE_COS(value) ((value) << 15) argument
41 #define LE_SSE(value) ((value) << 17) argument
[all …]
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| /drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_vcap_debugfs.c | 16 static const char *sparx5_vcap_is0_etype_str(u32 value) in sparx5_vcap_is0_etype_str()
40 static const char *sparx5_vcap_is0_mpls_str(u32 value) in sparx5_vcap_is0_mpls_str()
64 static const char *sparx5_vcap_is0_mlbs_str(u32 value) in sparx5_vcap_is0_mlbs_str()
82 u32 value, val; in sparx5_vcap_is0_port_keys() local
125 u32 value; in sparx5_vcap_is2_port_keys() local
237 u32 value; in sparx5_vcap_is2_port_stickies() local
292 u32 value; in sparx5_vcap_es0_port_keys() local
331 u32 value; in sparx5_vcap_es2_port_keys() local
410 u32 value; in sparx5_vcap_es2_port_stickies() local
|
| /drivers/gpu/drm/amd/amdgpu/ |
| D | soc15_common.h | 40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument
82 #define WREG32_SOC15(ip, inst, reg, value) \ argument
86 #define WREG32_SOC15_IP(ip, reg, value) \ argument
89 #define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \ argument
92 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ argument
96 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ argument
110 #define WREG32_RLC(reg, value) \ argument
113 #define WREG32_RLC_EX(prefix, reg, value, inst) \ argument
138 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ argument
145 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ argument
[all …]
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| /drivers/usb/fotg210/ |
| D | fotg210-udc.c | 34 u32 value = ioread32(fotg210->reg + offset); in fotg210_ack_int() local
42 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_disable_fifo_int() local
53 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR1); in fotg210_enable_fifo_int() local
64 u32 value = ioread32(fotg210->reg + FOTG210_DCFESR); in fotg210_set_cxdone() local
188 u32 value; in fotg210_reset_tseq() local
268 u32 value; in fotg210_enable_dma() local
306 u32 value; in fotg210_wait_dma_done() local
397 u32 value = ioread32(ep->fotg210->reg + FOTG210_DMISGR0); in fotg210_ep0_queue() local
458 u32 value; in fotg210_set_epnstall() local
479 u32 value; in fotg210_clear_epnstall() local
[all …]
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| /drivers/xen/xen-pciback/ |
| D | conf_space_header.c | 26 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO)) argument
27 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER) argument
51 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data) in command_read()
62 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data) in command_write()
127 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data) in rom_write()
160 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data) in bar_write()
196 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data) in bar_read()
260 u16 *value, void *data) in xen_pcibk_read_vendor()
268 u16 *value, void *data) in xen_pcibk_read_device()
275 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value, in interrupt_read()
[all …]
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| /drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| D | dr_ste_v0.c | 704 dr_ste_v0_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_src_dst_bit_mask()
736 dr_ste_v0_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_src_dst_tag()
792 dr_ste_v0_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l3_ipv6_dst_tag()
818 dr_ste_v0_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l3_ipv6_src_tag()
844 dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag()
881 dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()
932 dr_ste_v0_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_src_or_dst_tag()
993 dr_ste_v0_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_src_bit_mask()
1005 dr_ste_v0_build_eth_l2_src_tag(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_src_tag()
1028 dr_ste_v0_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value, in dr_ste_v0_build_eth_l2_dst_bit_mask()
[all …]
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| /drivers/media/pci/cx25821/ |
| D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() local
80 u32 value = 0; in medusa_initialize_ntsc() local
215 u32 value = 0, tmp = 0; in medusa_PALCombInit() local
247 u32 value = 0; in medusa_initialize_pal() local
386 u32 value = 0, tmp = 0; in medusa_set_videostandard() local
554 int value = 0; in medusa_set_brightness() local
575 int value = 0; in medusa_set_contrast() local
596 int value = 0; in medusa_set_hue() local
620 int value = 0; in medusa_set_saturation() local
650 u32 value = 0, tmp = 0; in medusa_video_init() local
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| /drivers/media/usb/cx231xx/ |
| D | cx231xx-avcore.c | 65 u32 value = 0; in initGPIO() local
86 u8 value[4] = { 0, 0, 0, 0 }; in uninitGPIO() local
262 u8 value = 0; in cx231xx_afe_set_input_mux() local
629 u32 value = 0; in cx231xx_set_decoder_video_input() local
1113 u32 value = 0; in cx231xx_set_audio_decoder_input() local
1253 u32 value; in cx231xx_init_ctrl_pin_status() local
1286 u8 value[4] = { 0, 0, 0, 0 }; in cx231xx_enable_i2c_port_3() local
1343 u32 value = 0; in cx231xx_dump_HH_reg() local
1480 u8 value = 0; in cx231xx_Setup_AFE_for_LowIF() local
1539 u8 value[4] = { 0, 0, 0, 0 }; in cx231xx_set_Colibri_For_LowIF() local
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