| /drivers/dma/ |
| D | fsldma.c | 39 #define chan_dbg(chan, fmt, arg...) \ argument
40 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
41 #define chan_err(chan, fmt, arg...) \ argument
42 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
50 static void set_sr(struct fsldma_chan *chan, u32 val) in set_sr() argument
52 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32); in set_sr()
55 static u32 get_sr(struct fsldma_chan *chan) in get_sr() argument
57 return FSL_DMA_IN(chan, &chan->regs->sr, 32); in get_sr()
60 static void set_mr(struct fsldma_chan *chan, u32 val) in set_mr() argument
62 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32); in set_mr()
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| D | stm32-dma.c | 233 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; member
236 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) in stm32_dma_get_dev() argument
238 return container_of(chan->vchan.chan.device, struct stm32_dma_device, in stm32_dma_get_dev()
244 return container_of(c, struct stm32_dma_chan, vchan.chan); in to_stm32_dma_chan()
252 static struct device *chan2dev(struct stm32_dma_chan *chan) in chan2dev() argument
254 return &chan->vchan.chan.dev->device; in chan2dev()
267 static int stm32_dma_get_width(struct stm32_dma_chan *chan, in stm32_dma_get_width() argument
278 dev_err(chan2dev(chan), "Dma bus width not supported\n"); in stm32_dma_get_width()
365 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) in stm32_dma_get_burst() argument
378 dev_err(chan2dev(chan), "Dma burst size not supported\n"); in stm32_dma_get_burst()
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| D | dmaengine.c | 86 struct dma_chan *chan; in dmaengine_dbg_summary_show() local
88 list_for_each_entry(chan, &dma_dev->channels, device_node) { in dmaengine_dbg_summary_show()
89 if (chan->client_count) { in dmaengine_dbg_summary_show()
90 seq_printf(s, " %-13s| %s", dma_chan_name(chan), in dmaengine_dbg_summary_show()
91 chan->dbg_client_name ?: "in-use"); in dmaengine_dbg_summary_show()
93 if (chan->router) in dmaengine_dbg_summary_show()
95 dev_name(chan->router->dev)); in dmaengine_dbg_summary_show()
159 return chan_dev->chan; in dev_to_dma_chan()
165 struct dma_chan *chan; in memcpy_count_show() local
171 chan = dev_to_dma_chan(dev); in memcpy_count_show()
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| D | nbpfaxi.c | 154 struct nbpf_channel *chan; member
236 struct nbpf_channel chan[]; member
304 static inline u32 nbpf_chan_read(struct nbpf_channel *chan, in nbpf_chan_read() argument
307 u32 data = ioread32(chan->base + offset); in nbpf_chan_read()
308 dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n", in nbpf_chan_read()
309 __func__, chan->base, offset, data); in nbpf_chan_read()
313 static inline void nbpf_chan_write(struct nbpf_channel *chan, in nbpf_chan_write() argument
316 iowrite32(data, chan->base + offset); in nbpf_chan_write()
317 dev_dbg(chan->dma_chan.device->dev, "%s(0x%p + 0x%x) = 0x%x\n", in nbpf_chan_write()
318 __func__, chan->base, offset, data); in nbpf_chan_write()
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_chan.c | 44 nouveau_channel_kill(struct nouveau_channel *chan) in nouveau_channel_kill() argument
46 atomic_set(&chan->killed, 1); in nouveau_channel_kill()
47 if (chan->fence) in nouveau_channel_kill()
48 nouveau_fence_context_kill(chan->fence, -ENODEV); in nouveau_channel_kill()
54 struct nouveau_channel *chan = container_of(event, typeof(*chan), kill); in nouveau_channel_killed() local
55 struct nouveau_cli *cli = (void *)chan->user.client; in nouveau_channel_killed()
57 NV_PRINTK(warn, cli, "channel %d killed!\n", chan->chid); in nouveau_channel_killed()
59 if (unlikely(!atomic_read(&chan->killed))) in nouveau_channel_killed()
60 nouveau_channel_kill(chan); in nouveau_channel_killed()
66 nouveau_channel_idle(struct nouveau_channel *chan) in nouveau_channel_idle() argument
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| D | nouveau_dma.c | 41 READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout) in READ_GET() argument
45 val = nvif_rd32(chan->userd, chan->user_get); in READ_GET()
46 if (chan->user_get_hi) in READ_GET()
47 val |= (uint64_t)nvif_rd32(chan->userd, chan->user_get_hi) << 32; in READ_GET()
64 if (val < chan->push.addr || in READ_GET()
65 val > chan->push.addr + (chan->dma.max << 2)) in READ_GET()
68 return (val - chan->push.addr) >> 2; in READ_GET()
72 nv50_dma_push(struct nouveau_channel *chan, u64 offset, u32 length, in nv50_dma_push() argument
75 struct nvif_user *user = &chan->drm->client.device.user; in nv50_dma_push()
76 struct nouveau_bo *pb = chan->push.buffer; in nv50_dma_push()
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| /drivers/gpu/drm/nouveau/nvkm/engine/fifo/ |
| D | chan.c | 42 nvkm_chan_cctx_bind(struct nvkm_chan *chan, struct nvkm_engn *engn, struct nvkm_cctx *cctx) in nvkm_chan_cctx_bind() argument
44 struct nvkm_cgrp *cgrp = chan->cgrp; in nvkm_chan_cctx_bind()
51 CHAN_TRACE(chan, "%sbind cctx %d[%s]", cctx ? "" : "un", engn->id, engine->subdev.name); in nvkm_chan_cctx_bind()
59 nvkm_chan_block(chan); in nvkm_chan_cctx_bind()
60 nvkm_chan_preempt(chan, true); in nvkm_chan_cctx_bind()
63 engn->func->bind(engn, cctx, chan); in nvkm_chan_cctx_bind()
69 nvkm_chan_allow(chan); in nvkm_chan_cctx_bind()
73 nvkm_chan_cctx_put(struct nvkm_chan *chan, struct nvkm_cctx **pcctx) in nvkm_chan_cctx_put() argument
80 if (refcount_dec_and_mutex_lock(&cctx->refs, &chan->cgrp->mutex)) { in nvkm_chan_cctx_put()
81 CHAN_TRACE(chan, "dtor cctx %d[%s]", engn->id, engn->engine->subdev.name); in nvkm_chan_cctx_put()
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| /drivers/dma/xilinx/ |
| D | zynqmp_dma.c | 141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size) argument
143 #define to_chan(chan) container_of(chan, struct zynqmp_dma_chan, \ argument
251 struct zynqmp_dma_chan *chan; member
256 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg, in zynqmp_dma_writeq() argument
259 lo_hi_writeq(value, chan->regs + reg); in zynqmp_dma_writeq()
267 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan, in zynqmp_dma_update_desc_to_ctrlr() argument
273 zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr); in zynqmp_dma_update_desc_to_ctrlr()
275 zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr); in zynqmp_dma_update_desc_to_ctrlr()
283 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan, in zynqmp_dma_desc_config_eod() argument
302 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan, in zynqmp_dma_config_sg_ll_desc() argument
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| D | xilinx_dma.c | 451 void (*start_transfer)(struct xilinx_dma_chan *chan);
452 int (*stop_transfer)(struct xilinx_dma_chan *chan);
507 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; member
524 #define to_xilinx_chan(chan) \ argument
525 container_of(chan, struct xilinx_dma_chan, common)
528 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ argument
529 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
533 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) in dma_read() argument
535 return ioread32(chan->xdev->regs + reg); in dma_read()
538 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) in dma_write() argument
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| D | xilinx_dpdma.c | 200 struct xilinx_dpdma_chan *chan; member
249 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan)
268 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN]; member
299 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan) in xilinx_dpdma_debugfs_desc_done_irq() argument
301 if (IS_ENABLED(CONFIG_DEBUG_FS) && chan->id == dpdma_debugfs.chan_id) in xilinx_dpdma_debugfs_desc_done_irq()
554 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan) in xilinx_dpdma_chan_alloc_sw_desc() argument
559 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr); in xilinx_dpdma_chan_alloc_sw_desc()
576 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan, in xilinx_dpdma_chan_free_sw_desc() argument
579 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr); in xilinx_dpdma_chan_free_sw_desc()
589 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan, in xilinx_dpdma_chan_dump_tx_desc() argument
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| /drivers/video/fbdev/savage/ |
| D | savagefb-i2c.c | 47 struct savagefb_i2c_chan *chan = data; in savage4_gpio_setscl() local
50 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setscl()
55 writel(r, chan->ioaddr + chan->reg); in savage4_gpio_setscl()
56 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setscl()
61 struct savagefb_i2c_chan *chan = data; in savage4_gpio_setsda() local
64 r = readl(chan->ioaddr + chan->reg); in savage4_gpio_setsda()
69 writel(r, chan->ioaddr + chan->reg); in savage4_gpio_setsda()
70 readl(chan->ioaddr + chan->reg); /* flush posted write */ in savage4_gpio_setsda()
75 struct savagefb_i2c_chan *chan = data; in savage4_gpio_getscl() local
77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN)); in savage4_gpio_getscl()
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| /drivers/mailbox/ |
| D | mailbox.c | 27 static int add_to_rbuf(struct mbox_chan *chan, void *mssg) in add_to_rbuf() argument
32 spin_lock_irqsave(&chan->lock, flags); in add_to_rbuf()
35 if (chan->msg_count == MBOX_TX_QUEUE_LEN) { in add_to_rbuf()
36 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
40 idx = chan->msg_free; in add_to_rbuf()
41 chan->msg_data[idx] = mssg; in add_to_rbuf()
42 chan->msg_count++; in add_to_rbuf()
45 chan->msg_free = 0; in add_to_rbuf()
47 chan->msg_free++; in add_to_rbuf()
49 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
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| /drivers/video/fbdev/i810/ |
| D | i810-i2c.c | 44 struct i810fb_i2c_chan *chan = data; in i810i2c_setscl() local
45 struct i810fb_par *par = chan->par; in i810i2c_setscl()
49 i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
51 i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK); in i810i2c_setscl()
52 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setscl()
57 struct i810fb_i2c_chan *chan = data; in i810i2c_setsda() local
58 struct i810fb_par *par = chan->par; in i810i2c_setsda()
62 i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
64 i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK); in i810i2c_setsda()
65 i810_readl(mmio, chan->ddc_base); /* flush posted write */ in i810i2c_setsda()
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| /drivers/staging/media/tegra-video/ |
| D | tegra20.c | 151 static void tegra20_vi_write(struct tegra_vi_channel *chan, unsigned int addr, u32 val) in tegra20_vi_write() argument
153 writel(val, chan->vi->iomem + addr); in tegra20_vi_write()
160 static void tegra20_vi_get_input_formats(struct tegra_vi_channel *chan, in tegra20_vi_get_input_formats() argument
164 unsigned int input_mbus_code = chan->fmtinfo->code; in tegra20_vi_get_input_formats()
188 static void tegra20_vi_get_output_formats(struct tegra_vi_channel *chan, in tegra20_vi_get_output_formats() argument
192 u32 output_fourcc = chan->format.pixelformat; in tegra20_vi_get_output_formats()
250 static int tegra20_channel_host1x_syncpt_init(struct tegra_vi_channel *chan) in tegra20_channel_host1x_syncpt_init() argument
252 struct tegra_vi *vi = chan->vi; in tegra20_channel_host1x_syncpt_init()
259 chan->mw_ack_sp[0] = out_sp; in tegra20_channel_host1x_syncpt_init()
264 static void tegra20_channel_host1x_syncpt_free(struct tegra_vi_channel *chan) in tegra20_channel_host1x_syncpt_free() argument
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| D | vi.c | 112 struct tegra_vi_channel *chan = vb2_get_drv_priv(vq); in tegra_channel_queue_setup() local
115 return sizes[0] < chan->format.sizeimage ? -EINVAL : 0; in tegra_channel_queue_setup()
118 sizes[0] = chan->format.sizeimage; in tegra_channel_queue_setup()
119 alloc_devs[0] = chan->vi->dev; in tegra_channel_queue_setup()
121 if (chan->vi->ops->channel_queue_setup) in tegra_channel_queue_setup()
122 chan->vi->ops->channel_queue_setup(chan); in tegra_channel_queue_setup()
129 struct tegra_vi_channel *chan = vb2_get_drv_priv(vb->vb2_queue); in tegra_channel_buffer_prepare() local
132 unsigned long size = chan->format.sizeimage; in tegra_channel_buffer_prepare()
135 v4l2_err(chan->video.v4l2_dev, in tegra_channel_buffer_prepare()
142 buf->chan = chan; in tegra_channel_buffer_prepare()
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| /drivers/gpu/drm/gma500/ |
| D | oaktrail_lvds_i2c.c | 63 #define LPC_READ_REG(chan, r) inl((chan)->reg + (r)) argument
64 #define LPC_WRITE_REG(chan, r, val) outl((val), (chan)->reg + (r)) argument
68 struct gma_i2c_chan *chan = data; in get_clock() local
71 val = LPC_READ_REG(chan, RGIO); in get_clock()
73 LPC_WRITE_REG(chan, RGIO, val); in get_clock()
74 LPC_READ_REG(chan, RGLVL); in get_clock()
75 val = (LPC_READ_REG(chan, RGLVL) & GPIO_CLOCK) ? 1 : 0; in get_clock()
82 struct gma_i2c_chan *chan = data; in get_data() local
85 val = LPC_READ_REG(chan, RGIO); in get_data()
87 LPC_WRITE_REG(chan, RGIO, val); in get_data()
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| D | intel_i2c.c | 25 struct gma_i2c_chan *chan = data; in get_clock() local
26 struct drm_device *dev = chan->drm_dev; in get_clock()
29 val = REG_READ(chan->reg); in get_clock()
35 struct gma_i2c_chan *chan = data; in get_data() local
36 struct drm_device *dev = chan->drm_dev; in get_data()
39 val = REG_READ(chan->reg); in get_data()
45 struct gma_i2c_chan *chan = data; in set_clock() local
46 struct drm_device *dev = chan->drm_dev; in set_clock()
51 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
59 REG_WRITE(chan->reg, reserved | clock_bits); in set_clock()
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| /drivers/dma/sf-pdma/ |
| D | sf-pdma.c | 44 return container_of(dchan, struct sf_pdma_chan, vchan.chan); in to_sf_pdma_chan()
52 static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) in sf_pdma_alloc_desc() argument
60 desc->chan = chan; in sf_pdma_alloc_desc()
74 static void sf_pdma_disclaim_chan(struct sf_pdma_chan *chan) in sf_pdma_disclaim_chan() argument
76 struct pdma_regs *regs = &chan->regs; in sf_pdma_disclaim_chan()
85 struct sf_pdma_chan *chan = to_sf_pdma_chan(dchan); in sf_pdma_prep_dma_memcpy() local
89 if (chan && (!len || !dest || !src)) { in sf_pdma_prep_dma_memcpy()
90 dev_err(chan->pdma->dma_dev.dev, in sf_pdma_prep_dma_memcpy()
95 desc = sf_pdma_alloc_desc(chan); in sf_pdma_prep_dma_memcpy()
100 desc->async_tx = vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); in sf_pdma_prep_dma_memcpy()
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | nv25.c | 25 struct nv20_gr_chan *chan; in nv25_gr_chan_new() local
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) in nv25_gr_chan_new()
30 nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); in nv25_gr_chan_new()
31 chan->gr = gr; in nv25_gr_chan_new()
32 chan->chid = fifoch->id; in nv25_gr_chan_new()
33 *pobject = &chan->object; in nv25_gr_chan_new()
37 &chan->inst); in nv25_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv25_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv25_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x035c, 0xffff0000); in nv25_gr_chan_new()
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| D | nv35.c | 25 struct nv20_gr_chan *chan; in nv35_gr_chan_new() local
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) in nv35_gr_chan_new()
30 nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); in nv35_gr_chan_new()
31 chan->gr = gr; in nv35_gr_chan_new()
32 chan->chid = fifoch->id; in nv35_gr_chan_new()
33 *pobject = &chan->object; in nv35_gr_chan_new()
37 &chan->inst); in nv35_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv35_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv35_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x00000101); in nv35_gr_chan_new()
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| D | nv34.c | 25 struct nv20_gr_chan *chan; in nv34_gr_chan_new() local
28 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) in nv34_gr_chan_new()
30 nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); in nv34_gr_chan_new()
31 chan->gr = gr; in nv34_gr_chan_new()
32 chan->chid = fifoch->id; in nv34_gr_chan_new()
33 *pobject = &chan->object; in nv34_gr_chan_new()
37 &chan->inst); in nv34_gr_chan_new()
41 nvkm_kmap(chan->inst); in nv34_gr_chan_new()
42 nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); in nv34_gr_chan_new()
43 nvkm_wo32(chan->inst, 0x040c, 0x01000101); in nv34_gr_chan_new()
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| /drivers/soc/fsl/qe/ |
| D | qmc.c | 257 int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info) in qmc_chan_get_info() argument
263 ret = tsa_serial_get_info(chan->qmc->tsa_serial, &tsa_info); in qmc_chan_get_info()
267 info->mode = chan->mode; in qmc_chan_get_info()
270 info->nb_tx_ts = hweight64(chan->tx_ts_mask); in qmc_chan_get_info()
273 info->nb_rx_ts = hweight64(chan->rx_ts_mask); in qmc_chan_get_info()
279 int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param *param) in qmc_chan_set_param() argument
281 if (param->mode != chan->mode) in qmc_chan_set_param()
290 qmc_write16(chan->qmc->scc_pram + QMC_GBL_MRBLR, in qmc_chan_set_param()
292 qmc_write16(chan->s_param + QMC_SPE_MFLR, in qmc_chan_set_param()
295 qmc_setbits16(chan->s_param + QMC_SPE_CHAMR, in qmc_chan_set_param()
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| /drivers/dma/dw-axi-dmac/ |
| D | dw-axi-dmac-platform.c | 66 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) in axi_chan_iowrite32() argument
68 iowrite32(val, chan->chan_regs + reg); in axi_chan_iowrite32()
71 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) in axi_chan_ioread32() argument
73 return ioread32(chan->chan_regs + reg); in axi_chan_ioread32()
77 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) in axi_chan_iowrite64() argument
83 iowrite32(lower_32_bits(val), chan->chan_regs + reg); in axi_chan_iowrite64()
84 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); in axi_chan_iowrite64()
87 static inline void axi_chan_config_write(struct axi_dma_chan *chan, in axi_chan_config_write() argument
94 if (chan->chip->dw->hdata->reg_map_8_channels && in axi_chan_config_write()
95 !chan->chip->dw->hdata->use_cfg2) { in axi_chan_config_write()
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| /drivers/video/fbdev/nvidia/ |
| D | nv_i2c.c | 30 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_setscl() local
31 struct nvidia_par *par = chan->par; in nvidia_gpio_setscl()
34 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setscl()
41 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setscl()
46 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_setsda() local
47 struct nvidia_par *par = chan->par; in nvidia_gpio_setsda()
50 val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0; in nvidia_gpio_setsda()
57 NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01); in nvidia_gpio_setsda()
62 struct nvidia_i2c_chan *chan = data; in nvidia_gpio_getscl() local
63 struct nvidia_par *par = chan->par; in nvidia_gpio_getscl()
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| /drivers/video/fbdev/riva/ |
| D | rivafb-i2c.c | 29 struct riva_i2c_chan *chan = data; in riva_gpio_setscl() local
30 struct riva_par *par = chan->par; in riva_gpio_setscl()
33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
47 struct riva_i2c_chan *chan = data; in riva_gpio_setsda() local
48 struct riva_par *par = chan->par; in riva_gpio_setsda()
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
59 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
65 struct riva_i2c_chan *chan = data; in riva_gpio_getscl() local
66 struct riva_par *par = chan->par; in riva_gpio_getscl()
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