| /drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_dcn30.c | 62 uint64_t *fb_offset) in dmub_dcn30_get_fb_base_offset() argument
66 if (dmub->fb_base || dmub->fb_offset) { in dmub_dcn30_get_fb_base_offset()
68 *fb_offset = dmub->fb_offset; in dmub_dcn30_get_fb_base_offset()
76 *fb_offset = (uint64_t)tmp << 24; in dmub_dcn30_get_fb_base_offset()
81 uint64_t fb_offset, in dmub_dcn30_translate_addr() argument
84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn30_translate_addr()
92 uint64_t fb_base, fb_offset; in dmub_dcn30_backdoor_load() local
94 dmub_dcn30_get_fb_base_offset(dmub, &fb_base, &fb_offset); in dmub_dcn30_backdoor_load()
100 dmub_dcn30_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
109 dmub_dcn30_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn30_backdoor_load()
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| D | dmub_dcn20.c | 62 uint64_t *fb_offset) in dmub_dcn20_get_fb_base_offset() argument
66 if (dmub->fb_base || dmub->fb_offset) { in dmub_dcn20_get_fb_base_offset()
68 *fb_offset = dmub->fb_offset; in dmub_dcn20_get_fb_base_offset()
76 *fb_offset = (uint64_t)tmp << 24; in dmub_dcn20_get_fb_base_offset()
81 uint64_t fb_offset, in dmub_dcn20_translate_addr() argument
84 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn20_translate_addr()
159 uint64_t fb_base, fb_offset; in dmub_dcn20_backdoor_load() local
161 dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset); in dmub_dcn20_backdoor_load()
167 dmub_dcn20_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
176 dmub_dcn20_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn20_backdoor_load()
[all …]
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| D | dmub_dcn31.c | 58 uint64_t *fb_offset) in dmub_dcn31_get_fb_base_offset() argument
62 if (dmub->fb_base || dmub->fb_offset) { in dmub_dcn31_get_fb_base_offset()
64 *fb_offset = dmub->fb_offset; in dmub_dcn31_get_fb_base_offset()
72 *fb_offset = (uint64_t)tmp << 24; in dmub_dcn31_get_fb_base_offset()
77 uint64_t fb_offset, in dmub_dcn31_translate_addr() argument
80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn31_translate_addr()
157 uint64_t fb_base, fb_offset; in dmub_dcn31_backdoor_load() local
159 dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset); in dmub_dcn31_backdoor_load()
163 dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn31_backdoor_load()
172 dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn31_backdoor_load()
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| D | dmub_dcn32.c | 59 uint64_t *fb_offset) in dmub_dcn32_get_fb_base_offset() argument
63 if (dmub->fb_base || dmub->fb_offset) { in dmub_dcn32_get_fb_base_offset()
65 *fb_offset = dmub->fb_offset; in dmub_dcn32_get_fb_base_offset()
73 *fb_offset = (uint64_t)tmp << 24; in dmub_dcn32_get_fb_base_offset()
78 uint64_t fb_offset, in dmub_dcn32_translate_addr() argument
81 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; in dmub_dcn32_translate_addr()
151 uint64_t fb_base, fb_offset; in dmub_dcn32_backdoor_load() local
153 dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset); in dmub_dcn32_backdoor_load()
157 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); in dmub_dcn32_backdoor_load()
166 dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); in dmub_dcn32_backdoor_load()
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| D | dmub_srv.c | 553 dmub->fb_offset = params->fb_offset; in dmub_srv_hw_init()
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| /drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_hwseq.c | 93 addr->quad_part += hwseq->fb_offset.quad_part; in gpu_addr_to_uma()
95 } else if (hwseq->fb_offset.quad_part <= addr->quad_part && in gpu_addr_to_uma()
203 uint32_t fb_offset = REG_READ(MC_VM_FB_OFFSET); in read_mmhub_vm_setup() local
214 hws->fb_offset.low_part = fb_offset; in read_mmhub_vm_setup()
215 hws->fb_offset.quad_part <<= 24; in read_mmhub_vm_setup()
218 - hws->fb_base.quad_part + hws->fb_offset.quad_part; in read_mmhub_vm_setup()
265 if (hws->fb_offset.quad_part == 0) in dcn201_init_hw()
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| /drivers/gpu/drm/logicvc/ |
| D | logicvc_layer.c | 275 u32 fb_offset; in logicvc_layer_buffer_find_setup() local
290 fb_offset = (u32) (fb_addr - logicvc->reserved_mem_base); in logicvc_layer_buffer_find_setup()
292 if (fb_offset < base_offset) { in logicvc_layer_buffer_find_setup()
298 gap = fb_offset - base_offset; in logicvc_layer_buffer_find_setup()
330 layer->index, fb_offset - base_offset); in logicvc_layer_buffer_find_setup()
335 layer->index, fb_offset - base_offset); in logicvc_layer_buffer_find_setup()
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| /drivers/gpu/drm/vboxvideo/ |
| D | vbox_mode.c | 59 vbox_crtc->fb_offset / pitch < 0xffff - crtc->y && in vbox_do_modeset()
60 vbox_crtc->fb_offset % (bpp / 8) == 0) { in vbox_do_modeset()
67 vbox_crtc->fb_offset % pitch / bpp * 8 + vbox_crtc->x); in vbox_do_modeset()
69 vbox_crtc->fb_offset / pitch + vbox_crtc->y); in vbox_do_modeset()
105 p->view_offset = vbox_crtc->fb_offset; in vbox_set_view()
106 p->view_size = vbox->available_vram_size - vbox_crtc->fb_offset + in vbox_set_view()
108 p->max_screen_size = vbox->available_vram_size - vbox_crtc->fb_offset; in vbox_set_view()
195 vbox_crtc->fb_offset = drm_gem_vram_offset(gbo); in vbox_crtc_set_base_and_mode()
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| D | vbox_drv.h | 97 u32 fb_offset; member
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hwseq.c | 72 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; in dcn21_init_sys_ctx()
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| D | dcn21_hubbub.c | 118 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); in hubbub21_init_dchub()
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| /drivers/gpu/drm/amd/display/dmub/ |
| D | dmub_srv.h | 259 uint64_t fb_offset; member
465 uint64_t fb_offset; member
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| /drivers/video/fbdev/ |
| D | platinumfb.h | 60 int fb_offset; member
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| D | platinumfb.c | 138 info->screen_base = pinfo->frame_buffer + init->fb_offset + offset; in platinumfb_set_par()
140 info->fix.smem_start = (pinfo->frame_buffer_phys) + init->fb_offset + offset; in platinumfb_set_par()
285 out_be32(&platinum_regs->reg[16].r, (unsigned) pinfo->frame_buffer_phys+init->fb_offset+0x10); in platinum_set_hardware()
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| D | ps3fb.c | 133 unsigned int fb_offset; /* start of actual DDR fb */ member
497 ddr_base + par->fb_offset, xdr_base + par->pan_offset, in ps3fb_sync()
639 par->fb_offset = GPU_ALIGN_UP(offset); in ps3fb_set_par()
640 par->full_offset = par->fb_offset - offset; in ps3fb_set_par()
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| D | au1200fb.c | 705 uint32 winctrl0, winctrl1, winenable, fb_offset = 0; in au1200_setlocation() local
733 fb_offset += (((0 - xpos) * winbpp(lcd->window[plane].winctrl1))/8); in au1200_setlocation()
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| /drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_hwseq.c | 483 config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset; in dcn31_init_sys_ctx()
495 pa_config->system_aperture.fb_offset; in dcn31_init_sys_ctx()
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| D | dcn31_hubbub.c | 891 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); in hubbub31_init_dchub_sys_ctx()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dchubbub.h | 76 uint64_t fb_offset; member
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| /drivers/video/fbdev/via/ |
| D | via-core.c | 149 u32 fb_offset; /* Offset into FB memory */ member
259 descr->fb_offset = offset; in viafb_dma_copy_out_sg()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | hw_sequencer_private.h | 180 PHYSICAL_ADDRESS_LOC fb_offset; member
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| /drivers/media/platform/via/ |
| D | via-camera.c | 80 u32 fb_offset; /* Reserved memory offset (FB) */ member
420 offset = cam->fb_offset; in viacam_ctlr_cbufs()
1181 cam->fb_offset = viadev->camera_fbmem_offset; in viacam_probe()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_hubbub.c | 75 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); in hubbub3_init_dchub_sys_ctx()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubbub.c | 384 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24); in hubbub2_init_dchub_sys_ctx()
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| /drivers/gpu/drm/amd/display/dc/ |
| D | dc.h | 690 uint64_t fb_offset; member
|